coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

1 participants
1699 discussions

Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29959 Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... qcs405:Add SPI_RAM_SIMULATION support for QCS405 Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/flash_controller.c A src/soc/qualcomm/qcs405/include/soc/flash_controller.h M src/soc/qualcomm/qcs405/include/soc/mmu.h M src/soc/qualcomm/qcs405/mmu.c M src/soc/qualcomm/qcs405/spi.c 8 files changed, 172 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29959/1 diff --git a/src/mainboard/google/mistral/romstage.c b/src/mainboard/google/mistral/romstage.c index 079e20b..71968fc 100644 --- a/src/mainboard/google/mistral/romstage.c +++ b/src/mainboard/google/mistral/romstage.c @@ -21,6 +21,12 @@ #include <timestamp.h> #include <arch/stages.h> +#ifdef CONFIG_QC_SOC_SIMULATE +extern void qcs405_mmu_dram_config_c(void); +#endif void platform_romstage_main(void) { +#ifdef CONFIG_QC_SOC_SIMULATE + qcs405_mmu_dram_config_c(); +#endif } diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 492e80e..b24dc9e 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -20,4 +20,10 @@ select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_BOOTBLOCK + +config QC_SOC_SIMULATE + bool + prompt "Build for Early Simulation Environment" + default y + endif diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 158ce34..17ba0f1 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -8,17 +8,20 @@ bootblock-y += timer.c bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c +bootblock-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ verstage-y += spi.c verstage-y += timer.c verstage-y += gpio.c +verstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ romstage-y += spi.c romstage-y += cbmem.c romstage-y += timer.c romstage-y += gpio.c +romstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ ramstage-y += soc.c @@ -26,6 +29,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += gpio.c +ramstage-$(CONFIG_QC_SOC_SIMULATE) += flash_controller.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/flash_controller.c b/src/soc/qualcomm/qcs405/flash_controller.c new file mode 100644 index 0000000..1cb2aeb --- /dev/null +++ b/src/soc/qualcomm/qcs405/flash_controller.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* NOR Flash is clocked with 26MHz, from CLK26M -> TOP_SPINFI_IFR */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <symbols.h> +#include <timer.h> + +static struct spi_flash *ram_flash; +static struct spi_ctrlr *ram_ctrlr; + +#define ROM_BASE 0xA0000000 /* Above cbmem_top() */ + +int spi_simulate_ram_flash_probe(const struct spi_slave *spi, + struct spi_flash *flash); + +static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) +{ + void *ap = (void *)ROM_BASE; + ap += addr; + memcpy(buf, ap, len); + return 0; +} + +static int ram_write(const struct spi_flash *flash, u32 addr, size_t len, + const void *buf) +{ + void *ap = (void *)ROM_BASE; + ap += addr; + memcpy(ap, buf, len); + return 0; +} + +static int ram_erase(const struct spi_flash *flash, u32 offset, size_t len) +{ + void *ap = (void *)ROM_BASE; + ap += offset; + memset(ap, 0xFF, len); + return 0; +} + +static int ram_status(const struct spi_flash *flash, u8 *reg) +{ + return 0; +} + +static struct spi_flash_ops ram_ops = +{ + .read = ram_read, + .write = ram_write, + .erase = ram_erase, + .status = ram_status, +}; + +int spi_simulate_ram_flash_probe(const struct spi_slave *spi, + struct spi_flash *flash) +{ + static char name[] = "ram_flash"; + + printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__); + + printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__); + + ram_flash = flash; + ram_ctrlr = (struct spi_ctrlr *)spi->ctrlr; + ram_ctrlr->max_xfer_size = 0x10000; + flash->spi.bus = spi->bus; + flash->spi.cs = spi->cs; + flash->spi.ctrlr = ram_ctrlr; + flash->name = name; + flash->size = 0x800000; + flash->sector_size = 0x200; + flash->erase_cmd = 0x10; + flash->status_cmd = 0x20; + flash->ops = &ram_ops; + + return 0; +} diff --git a/src/soc/qualcomm/qcs405/include/soc/flash_controller.h b/src/soc/qualcomm/qcs405/include/soc/flash_controller.h new file mode 100644 index 0000000..0641928 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/flash_controller.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_QCS405_FLASH_CONTROLLER_H__ +#define __SOC_QUALCOMM_QCS405_FLASH_CONTROLLER_H__ + +#include <cbfs.h> +#include <spi-generic.h> +#include <stdint.h> + +struct spi_flash *qcs405_nor_flash_probe(struct spi_slave *spi); +#endif /* __SOC_QUALCOMM_QCS405_FLASH_CONTROLLER_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index 75cb320..3951f96 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -19,5 +19,8 @@ #define DRAMSIZE4GB 0x100000000 void qcs405_mmu_init(void); +#ifdef CONFIG_QC_SOC_SIMULATE +void qcs405_mmu_dram_config_c(void); +#endif #endif // _SOC_QUALCOMM_QCS405_MMU_H_ diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c index b47de42..bebca24 100644 --- a/src/soc/qualcomm/qcs405/mmu.c +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -27,6 +27,16 @@ MA_DEV | MA_S | MA_RW); mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW); mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW); +#ifdef CONFIG_QC_SOC_SIMULATE + mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_S | MA_RW); +#endif mmu_enable(); } + +#ifdef CONFIG_QC_SOC_SIMULATE +void qcs405_mmu_dram_config_c(void) +{ + mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); +} +#endif diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index c04b15d..73e538e 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -16,6 +16,25 @@ #include <spi-generic.h> #include <spi_flash.h> +#if IS_ENABLED(CONFIG_QC_SOC_SIMULATE) + +extern int spi_simulate_ram_flash_probe(const struct spi_slave *spi, + struct spi_flash *flash); + +static const struct spi_ctrlr spi_ctrlr = { + .flash_probe = spi_simulate_ram_flash_probe, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + } +}; + +#else + static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { return 0; @@ -47,4 +66,6 @@ }, }; +#endif + const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Combine BB with QC-Sec for ROM boot
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29958 Change subject: qcs405: Combine BB with QC-Sec for ROM boot ...................................................................... qcs405: Combine BB with QC-Sec for ROM boot TEST=build & run Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29958/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index f05c987..158ce34 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -31,8 +31,34 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/qcs405/include +QCS405_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/qcs405 + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin +################################################################################ +QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn +qc_sec_file := $(shell ls $(QC_SEC_FILE)) +ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf + @util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 32 -c 32 +ifeq ($(CONFIG_QC_FLASH_SIMULATE_SDCARD),y) + @printf "\nqgpt.py 512 sector size\n" + @util/qualcomm/qgpt.py -s 512 $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin +else + @printf "\nqgpt.py 4K sector size\n" + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin +endif + +else +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin +endif + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Gerrit-Change-Number: 29958 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29957 Change subject: libpayload: Add UART for qcs405 ...................................................................... libpayload: Add UART for qcs405 TEST=build Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.mistral M payloads/libpayload/drivers/Makefile.inc 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29957/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 3cd8ba6..4ab83cb 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -258,6 +258,11 @@ depends on SERIAL_CONSOLE default n +config QCS405_SERIAL_CONSOLE + bool "QCS405 SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config BG4CD_SERIAL_CONSOLE bool "Serial port driver for Marvell's BG4CD" depends on SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral index 5f60392..23bf54e 100644 --- a/payloads/libpayload/configs/config.mistral +++ b/payloads/libpayload/configs/config.mistral @@ -1,3 +1,8 @@ CONFIG_LP_CHROMEOS=y CONFIG_LP_ARCH_ARM64=y CONFIG_LP_TIMER_ARM64_ARCH=y +CONFIG_LP_SERIAL_CONSOLE=y +CONFIG_LP_QCS405_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 2d70856..99de283 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -37,6 +37,7 @@ libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c serial/serial.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c serial/serial.c libc-$(CONFIG_LP_IPQ40XX_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c +libc-$(CONFIG_LP_QCS405_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c libc-$(CONFIG_LP_BG4CD_SERIAL_CONSOLE) += serial/bg4cd.c serial/serial.c libc-$(CONFIG_LP_PC_KEYBOARD) += i8042/keyboard.c libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Implement bitbang UART for bootblock
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29956 Change subject: qcs405: Implement bitbang UART for bootblock ...................................................................... qcs405: Implement bitbang UART for bootblock This patch replaces the UART in the bootblock of QCS405 with a bitbang implementation. Since QCS405 hardware UART needs a firmware blob loaded into it before it becomes usable, it is not really suited for use in the bootblock (since by the time we can read blobs from SPI, the bootblock is essentially over anyway). This solution allows us to still have some console output during early SoC initialization. Change-Id: Ib631929f6194d0da8571a930230f0eb460fefaa6 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/uart_bitbang.c 3 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29956/1 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 83c3996..492e80e 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -11,6 +11,7 @@ select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select ARM64_USE_ARCH_TIMER + select HAVE_UART_SPECIAL if SOC_QUALCOMM_QCS405 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 131f204..f05c987 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += gpio.c +bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ################################################################################ verstage-y += spi.c diff --git a/src/soc/qualcomm/qcs405/uart_bitbang.c b/src/soc/qualcomm/qcs405/uart_bitbang.c new file mode 100644 index 0000000..8827bc4 --- /dev/null +++ b/src/soc/qualcomm/qcs405/uart_bitbang.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <gpio.h> +#include <types.h> + +#define UART_TX_PIN GPIO(17) + +static void set_tx(int line_state) +{ + gpio_set(UART_TX_PIN, line_state); +} + +void uart_init(int idx) +{ + gpio_output(UART_TX_PIN, 1); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + uart_bitbang_tx_byte(data, set_tx); +} + +void uart_tx_flush(int idx) +{ + /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ +} + +unsigned char uart_rx_byte(int idx) +{ + return 0; /* not implemented */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib631929f6194d0da8571a930230f0eb460fefaa6 Gerrit-Change-Number: 29956 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add GPIO API
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29955 Change subject: qcs405: Add GPIO API ...................................................................... qcs405: Add GPIO API Introduces new and required GPIO APIs, using common pinmux definitions for GPIO configuration. TEST=build & run Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/gpio.c A src/soc/qualcomm/qcs405/include/soc/addressmap.h M src/soc/qualcomm/qcs405/include/soc/gpio.h 4 files changed, 436 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29955/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index b47a61e..131f204 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -6,21 +6,25 @@ bootblock-y += spi.c bootblock-y += mmu.c bootblock-y += timer.c +bootblock-y += gpio.c ################################################################################ verstage-y += spi.c verstage-y += timer.c +verstage-y += gpio.c ################################################################################ romstage-y += spi.c romstage-y += cbmem.c romstage-y += timer.c +romstage-y += gpio.c ################################################################################ ramstage-y += soc.c ramstage-y += spi.c ramstage-y += cbmem.c ramstage-y += timer.c +ramstage-y += gpio.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c new file mode 100644 index 0000000..edbb3b9 --- /dev/null +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <types.h> +#include <console/console.h> +#include <delay.h> +#include <timer.h> +#include <timestamp.h> + +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + uint32_t reg_val; + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | + ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | + ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + + write32(&regs->cfg, reg_val); +} + +void gpio_set(gpio_t gpio, int value) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); +} + +int gpio_get(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & + GPIO_IO_IN_BMSK); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_DISABLE, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_DISABLE, + GPIO_PULL_UP, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set(gpio, value); + gpio_configure(gpio, GPIO_FUNC_DISABLE, + GPIO_NO_PULL, GPIO_2MA, GPIO_ENABLE); +} diff --git a/src/soc/qualcomm/qcs405/include/soc/addressmap.h b/src/soc/qualcomm/qcs405/include/soc/addressmap.h new file mode 100644 index 0000000..435b680 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/addressmap.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ +#define __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ + +#include <stdint.h> + +#define QSPI_BASE 0x88DF000 +#define TLMM_EAST_TILE_BASE 0x7B00000 +#define TLMM_NORTH_TILE_BASE 0x1300000 +#define TLMM_SOUTH_TILE_BASE 0x1000000 + +#endif /* __SOC_QUALCOMM_QCS405_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/gpio.h b/src/soc/qualcomm/qcs405/include/soc/gpio.h index e1ad453..f436595 100644 --- a/src/soc/qualcomm/qcs405/include/soc/gpio.h +++ b/src/soc/qualcomm/qcs405/include/soc/gpio.h @@ -17,7 +17,336 @@ #define _SOC_QUALCOMM_QCS405_GPIO_H_ #include <types.h> +#include <soc/addressmap.h> -typedef u32 gpio_t; +typedef struct { + u32 addr; +} gpio_t; + +#define TLMM_TILE_SIZE 0x00400000 +#define TLMM_GPIO_OFF_DELTA 0x00001000 +#define TLMM_GPIO_TILE_NUM 3 + +#define TLMM_GPIO_IN_OUT_OFF 0x4 +#define TLMM_GPIO_ID_STATUS_OFF 0x10 + +#define GPIO_FUNC_ENABLE 1 +#define GPIO_FUNC_DISABLE 0 + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_DISABLE 0 +#define GPIO_ENABLE 1 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_BMSK 0x3 +#define GPIO_CFG_FUNC_BMSK 0xF +#define GPIO_CFG_DRV_BMSK 0x7 +#define GPIO_CFG_OE_BMSK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHFT 0 +#define GPIO_CFG_FUNC_SHFT 2 +#define GPIO_CFG_DRV_SHFT 6 +#define GPIO_CFG_OE_SHFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_BMSK 0x1 +#define GPIO_IO_OUT_BMSK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHFT 0 +#define GPIO_IO_OUT_SHFT 1 + +/* GPIO ID STATUS: Mask */ +#define GPIO_ID_STATUS_BMSK 0x1 + +/* GPIO MAX Valid # */ +#define GPIO_NUM_MAX 149 + +#define GPIO_FUNC_GPIO 0 + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ +GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4, \ +GPIO##index##_FUNC_##func5 = 5, \ +GPIO##index##_FUNC_##func6 = 6, \ +GPIO##index##_FUNC_##func7 = 7 + +enum { + PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5, + RES_6, RES_7), + PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(17, NORTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3, + RES_4, RES_5, RES_6, RES_7), + PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5, + RES_6, RES_7), + PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0, + MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT), + PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA, + RES_5, RES_6, RES_7), + PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA, + RES_5, RES_6, RES_7), + PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA, + RES_5, RES_6, RES_7), + PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA, + RES_5, RES_6, RES_7), + PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK, + RES_5, RES_6, RES_7), + PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4, + RES_5, RES_6, RES_7), + PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB, + RES_4, RES_5, RES_6, RES_7), + PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3, + RES_4, RES_5, RES_6, RES_7), + PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5, + RES_6, RES_7), + PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5, + RES_6, RES_7), + PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5, + RES_6, RES_7), + PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3, + RES_4, RES_5, RES_6, RES_7), + PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE, + RES_5, RES_6, RES_7), + PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF, + RES_5, RES_6, RES_7), + PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4, + RES_5, RES_6, RES_7), + PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4, + RES_5, RES_6, RES_7), + PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD, + RES_5, RES_6, RES_7), + PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4, + RES_5, RES_6, RES_7), + PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), + PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5, + RES_6, RES_7), +}; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; +}; + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); #endif // _SOC_QUALCOMM_QCS405_GPIO_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/29955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Gerrit-Change-Number: 29955 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add DRAM resources
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29954 Change subject: qcs405: Add DRAM resources ...................................................................... qcs405: Add DRAM resources TEST=build Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/mmu.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/soc.c 4 files changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29954/1 diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index c0f5759..03c6edb 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -45,7 +45,9 @@ REGION(pmic, 0x8D8F000, 0xA000, 4096)*/ BSRAM_END(0x8D80000) - DRAM_START(0x90000000) - POSTRAM_CBFS_CACHE(0x90000000, 384K) - RAMSTAGE(0x90800000, 128K) + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_reserved, 0x85000000, 0x1A800000, 4096) + POSTRAM_CBFS_CACHE(0x9F800000, 384K) + RAMSTAGE(0x9F860000, 128K) } diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h index bc42e72..75cb320 100644 --- a/src/soc/qualcomm/qcs405/include/soc/mmu.h +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -16,6 +16,8 @@ #ifndef _SOC_QUALCOMM_QCS405_MMU_H__ #define _SOC_QUALCOMM_QCS405_MMU_H__ +#define DRAMSIZE4GB 0x100000000 + void qcs405_mmu_init(void); #endif // _SOC_QUALCOMM_QCS405_MMU_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 7b35c55..f7cdc8d 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -26,4 +26,8 @@ extern u8 _ebsram[]; #define _bsram_size (_ebsram - _bsram) +extern u8 _dram_reserved[]; +extern u8 _edram_reserved[]; +#define _dram_reserved_size (_edram_reserved - _dram_reserved) + #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index 7870219..c97822a 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -13,12 +13,17 @@ * GNU General Public License for more details. */ +#include <symbols.h> #include <device/device.h> #include <timestamp.h> +#include <soc/mmu.h> +#include <soc/symbols.h> static void soc_read_resources(device_t dev) { - + ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, + _dram_reserved_size / KiB); } static void soc_init(device_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/29954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185 Gerrit-Change-Number: 29954 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: qcs405: Add Timer support
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29952 Change subject: qcs405: Add Timer support ...................................................................... qcs405: Add Timer support Init frequency to 19.2 MHz TEST=build Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/timer.c 3 files changed, 8 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29952/1 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 560d988..83c3996 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -10,6 +10,7 @@ select GENERIC_GPIO_LIB select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER if SOC_QUALCOMM_QCS405 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 2d1f842..b47a61e 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -3,24 +3,24 @@ ################################################################################ bootblock-y += bootblock.c -bootblock-y += timer.c bootblock-y += spi.c bootblock-y += mmu.c +bootblock-y += timer.c ################################################################################ -verstage-y += timer.c verstage-y += spi.c +verstage-y += timer.c ################################################################################ -romstage-y += timer.c romstage-y += spi.c romstage-y += cbmem.c +romstage-y += timer.c ################################################################################ ramstage-y += soc.c -ramstage-y += timer.c ramstage-y += spi.c ramstage-y += cbmem.c +ramstage-y += timer.c ################################################################################ diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/qcs405/timer.c index 8fb84c8..5df2430 100644 --- a/src/soc/qualcomm/qcs405/timer.c +++ b/src/soc/qualcomm/qcs405/timer.c @@ -13,15 +13,11 @@ * GNU General Public License for more details. */ -#include <timer.h> #include <delay.h> - -void timer_monotonic_get(struct mono_time *mt) -{ - -} +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> void init_timer(void) { - + raw_write_cntfrq_el0(19200*KHz); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab Gerrit-Change-Number: 29952 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: libpayload: Add Timer for qcs405
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29953 Change subject: libpayload: Add Timer for qcs405 ...................................................................... libpayload: Add Timer for qcs405 Use ARCH64 Timer TEST=build Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A payloads/libpayload/configs/config.mistral 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29953/1 diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral new file mode 100644 index 0000000..5f60392 --- /dev/null +++ b/payloads/libpayload/configs/config.mistral @@ -0,0 +1,3 @@ +CONFIG_LP_CHROMEOS=y +CONFIG_LP_ARCH_ARM64=y +CONFIG_LP_TIMER_ARM64_ARCH=y -- To view, visit https://review.coreboot.org/c/coreboot/+/29953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97 Gerrit-Change-Number: 29953 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: util/qualcomm: Add T32 debug scripts
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29951 Change subject: util/qualcomm: Add T32 debug scripts ...................................................................... util/qualcomm: Add T32 debug scripts T32 scripts that allow debug of any coreboot stage on qcs405 Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- A util/qualcomm/scripts/cmm/clear_bss.cmm A util/qualcomm/scripts/cmm/debug_cb_405.cmm M util/qualcomm/scripts/cmm/debug_cb_common.cmm A util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm 4 files changed, 212 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29951/1 diff --git a/util/qualcomm/scripts/cmm/clear_bss.cmm b/util/qualcomm/scripts/cmm/clear_bss.cmm new file mode 100755 index 0000000..16eaac7 --- /dev/null +++ b/util/qualcomm/scripts/cmm/clear_bss.cmm @@ -0,0 +1,16 @@ +d.a 0x80000000 mov x0,#0x8c +d.a 0x80000004 lsl x0, x0, #0x14 +d.a 0x80000008 mov x1,#0x18 +d.a 0x8000000c lsl x1,x1, #0x10 +d.a 0x80000010 mov x2,#0x0 +d.a 0x80000014 mov x3,#0x80 +d.a 0x80000018 lsl x3, x3, #0x18 +d.a 0x8000001c add x3, x3, #0x14 +d.a 0x80000020 str x2,[x0] +d.a 0x80000024 sub x1, x1, #0x8 +d.a 0x80000028 add x0, x0, #0x8 +d.a 0x8000002c cmp x1,0x0 +d.a 0x80000030 b.ne 0x20 +d.a 0x80000034 b 0x34 +r.s pc 0x80000000 +go diff --git a/util/qualcomm/scripts/cmm/debug_cb_405.cmm b/util/qualcomm/scripts/cmm/debug_cb_405.cmm new file mode 100644 index 0000000..166d2aa --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_405.cmm @@ -0,0 +1,165 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2018, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_cb_405.cmm +; +; Description: +; Debug coreboot 405 front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry +GLOBAL &KernelEntryAddr // Kernel Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +GLOBAL &debug + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName + + // Later these can be parameterized + &TargetPkg="Qcs405Pkg" + + // These settings come from .../src/soc/qualcomm/qcs405/include/soc/memlayout.ld + &BBEntryAddr=0x8c2f000 + &VEREntryAddr=0x8C00000 + &ROMEntryAddr=0x8C00000 + &QCLEntryAddr=0x1485AC00 + &RAMEntryAddr=0x9F860000 + &BL31EntryAddr=0x06820000 + &DCEntryAddr=0xf1104800 + &KernelEntryAddr=0x90080000 + + &PreRamConsoleAddr=0x8C4F400 + &VBoot2Work=0x8C47000 + &Stack=0x8C4B000 + &Ttb=0x8C39000 + &Timestamp=0x8C4F000 + &PreRamCbfsCache=0x8C57400 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + b.sel PROGRAM onchip + ;sys.u + + b.d /all + + ;go &BBEntryAddr + ;wait !run() + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + ;winclear + ;b.d /all + + if FILE.EXIST("C:\TEMP\WIN.CMM") + do C:\TEMP\WIN.CMM + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + PRINT "pbl32_to_bootblock64 jump" + do pbl32_to_bootblock64_jump.cmm + do clear_bss.cmm + WAIT 5s + b + + // Make parsing simple, upper-case parameters + &Imagename=STRING.UPR("&Imagename") + IF (STR.CP("&ImageName","DEBUG,*")) + ( + &debug="DEBUG" + ) + ELSE + ( + &debug="" + ) + &Imagename=STR.CUT("&ImageName",6) + IF "&debug"=="" + ( + PRINT "SPI_RAM LOAD" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,BB" //for RAM load Bootblock only and jump till DC + ) + PRINT "&ImageName" + ) + ELSE + ( + if (STR.CP("&debug","DEBUG")) + ( + PRINT "DEBUG" + &ImageName=STRING.UPR("&ImageName") + IF "&ImageName"=="" + ( + &ImageName="RAM,ALL" //for RAM loading all the images + ) + PRINT "&ImageName" + ) + ) + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index bdb0097..5959ee1 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -104,6 +104,10 @@ if &BBStage ( + IF "&debug"=="" + ( + d.load.binary build/coreboot.rom 0xA0000000 + ) &imgpath="build\cbfs\fallback\bootblock.elf" if (&RAMLoad) d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath @@ -114,9 +118,17 @@ ;b.s run_romstage /o ;d.set &PreRamConsoleAddr++0x8000 0 d.dump &PreRamConsoleAddr /spotlight - print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" - print %String "Press enter to go to next stage" - enter + IF (STR.CP("&debug","DEBUG")) + ( + print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter + ) + ELSE + ( + go + enddo + ) ) go &VEREntryAddr diff --git a/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm new file mode 100644 index 0000000..de01bad --- /dev/null +++ b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm @@ -0,0 +1,16 @@ +PER.Set.simple SPR:0x36100 %Long 00c5183C +D.S AZSD:0x8600034 %LE %Long 0x8600000 +D.S AZSD:0x8600000 %LE %Long 0x1400000 +d.a 0x8600004 ldr r0,0x8600034 +d.a 0x8600008 mcr p15,0x0,r0,c12,c0,1 +d.a 0x860000c dsb +d.a 0x8600010 isb +d.a 0x8600014 mrc p15,0x0,r1,c12,c0,2 +d.a 0x8600018 orr r1,r1,0x3 +d.a 0x860001c mcr p15,0x0,r1,c12,c0,2 +d.a 0x8600020 isb +d.a 0x8600024 wfi +r.s pc 0x8600004 +go +b + -- To view, visit https://review.coreboot.org/c/coreboot/+/29951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Gerrit-Change-Number: 29951 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/qualcomm/qcs405: Add MMU support
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29950 Change subject: soc/qualcomm/qcs405: Add MMU support ...................................................................... soc/qualcomm/qcs405: Add MMU support Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/bootblock.c A src/soc/qualcomm/qcs405/include/soc/mmu.h A src/soc/qualcomm/qcs405/include/soc/symbols.h A src/soc/qualcomm/qcs405/mmu.c 5 files changed, 85 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29950/1 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 15f5a0c..2d1f842 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -5,6 +5,7 @@ bootblock-y += bootblock.c bootblock-y += timer.c bootblock-y += spi.c +bootblock-y += mmu.c ################################################################################ verstage-y += timer.c diff --git a/src/soc/qualcomm/qcs405/bootblock.c b/src/soc/qualcomm/qcs405/bootblock.c index 3ed37ae..5e63f13 100644 --- a/src/soc/qualcomm/qcs405/bootblock.c +++ b/src/soc/qualcomm/qcs405/bootblock.c @@ -14,8 +14,9 @@ */ #include <bootblock_common.h> +#include <soc/mmu.h> void bootblock_soc_init(void) { - + qcs405_mmu_init(); } diff --git a/src/soc/qualcomm/qcs405/include/soc/mmu.h b/src/soc/qualcomm/qcs405/include/soc/mmu.h new file mode 100644 index 0000000..bc42e72 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/mmu.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_MMU_H__ +#define _SOC_QUALCOMM_QCS405_MMU_H__ + +void qcs405_mmu_init(void); + +#endif // _SOC_QUALCOMM_QCS405_MMU_H_ diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h new file mode 100644 index 0000000..7b35c55 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCS405_SYMBOLS_H_ +#define _SOC_QUALCOMM_QCS405_SYMBOLS_H_ + +#include <types.h> + +extern u8 _ssram[]; +extern u8 _essram[]; +#define _ssram_size (_essram - _ssram) + +extern u8 _bsram[]; +extern u8 _ebsram[]; +#define _bsram_size (_ebsram - _bsram) + +#endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ diff --git a/src/soc/qualcomm/qcs405/mmu.c b/src/soc/qualcomm/qcs405/mmu.c new file mode 100644 index 0000000..b47de42 --- /dev/null +++ b/src/soc/qualcomm/qcs405/mmu.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/symbols.h> + +void qcs405_mmu_init() +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), + MA_DEV | MA_S | MA_RW); + mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW); + mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW); + + mmu_enable(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Gerrit-Change-Number: 29950 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

1 0

← Newer
1
...
7
8
9
10
11
12
13
...
170
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2018