coreboot-gerrit November 2018

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Change in ...coreboot[master]: Coreboot: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: Coreboot: Add support for USB host mode for mistral platform ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c@137 PS2, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c@138 PS2, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c@139 PS2, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/2/src/soc/qualcomm/qcs405/usb.c@140 PS2, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:08:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp uart driver
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 ) Change subject: qcs405: Add blsp uart driver ...................................................................... Patch Set 2: (25 comments) https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/cdp.h: https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 36: unsigned smem_get_board_machtype(void); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 89: SPI_CS_0 , space prohibited before that ',' (ctx:WxE) https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 119: unsigned count; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 124: unsigned base; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 126: unsigned is_macsec; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 127: unsigned mac_pwr0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 128: unsigned mac_pwr1; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 129: unsigned mac_conn_to_phy; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 172: unsigned int get_board_index(unsigned machid); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 173: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count); Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/iomap.h: https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 49: #define writel_i(v,a) write32((void *)a, v) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c File src/soc/qualcomm/qcs405/uart.c: https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@50 PS2, Line 50: unsigned blsp_uart; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@54 PS2, Line 54: void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@56 PS2, Line 56: int i; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@56 PS2, Line 56: int i; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@58 PS2, Line 58: for (i = 0; i < count; i++) { code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@58 PS2, Line 58: for (i = 0; i < count; i++) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@59 PS2, Line 59: gpio_configure(gpio->gpio, gpio->func, code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@59 PS2, Line 59: gpio_configure(gpio->gpio, gpio->func, please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@60 PS2, Line 60: gpio->pull, gpio->drvstr, gpio->enable); code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@60 PS2, Line 60: gpio->pull, gpio->drvstr, gpio->enable); please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@61 PS2, Line 61: gpio++; code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@61 PS2, Line 61: gpio++; please, no spaces at the start of a line https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@62 PS2, Line 62: } code indent should use tabs where possible https://review.coreboot.org/#/c/29964/2/src/soc/qualcomm/qcs405/uart.c@62 PS2, Line 62: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:07:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29959 ) Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... Patch Set 2: (6 comments) https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… File src/soc/qualcomm/qcs405/flash_controller.c: https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 37: static int ram_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) line over 80 characters https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 68: { that open brace { should be on the previous line https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 78: static char name[] = "ram_flash"; static char array declaration should probably be static const char https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 80: printk(BIOS_INFO, "[%s]..CONFIG_QC_SOC_SIMULATE\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/flash_contr… PS2, Line 82: printk(BIOS_INFO, "[%s]..ram_flash\n", __FUNCTION__); __func__ should be used instead of gcc specific __FUNCTION__ https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29959/2/src/soc/qualcomm/qcs405/mmu.c@40 PS2, Line 40: mmu_config_range((void *)0x80000000, 0x40000000, MA_MEM | MA_NS | MA_RW); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:07:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add GPIO API
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29955 ) Change subject: qcs405: Add GPIO API ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29955/2/src/soc/qualcomm/qcs405/include/soc… File src/soc/qualcomm/qcs405/include/soc/gpio.h: https://review.coreboot.org/#/c/29955/2/src/soc/qualcomm/qcs405/include/soc… PS2, Line 90: #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/29955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8 Gerrit-Change-Number: 29955 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:06:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/lynxpoint: Allow the flash chip to be write-protected
by Patrick Rudolph (Code Review) 30 Nov '18

30 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29977 ) Change subject: sb/intel/lynxpoint: Allow the flash chip to be write-protected ...................................................................... Patch Set 1: While technically correct I don't see why we need to duplicate code and Kconfig options. Can you move the bd82x6x code to sb/intel/common and just use that instead ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Gerrit-Change-Number: 29977 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 14:05:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Add MMU support
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29950 ) Change subject: soc/qualcomm/qcs405: Add MMU support ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29950/2/src/soc/qualcomm/qcs405/mmu.c File src/soc/qualcomm/qcs405/mmu.c: https://review.coreboot.org/#/c/29950/2/src/soc/qualcomm/qcs405/mmu.c@22 PS2, Line 22: void qcs405_mmu_init() Bad function definition - void qcs405_mmu_init() should probably be void qcs405_mmu_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/29950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d Gerrit-Change-Number: 29950 Gerrit-PatchSet: 2 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Fri, 30 Nov 2018 14:05:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add bl31 stage and elf
by Name of user not set (Code Review) 30 Nov '18

30 Nov '18

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29981 Change subject: qcs405: Add bl31 stage and elf ...................................................................... qcs405: Add bl31 stage and elf Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/arch/arm64/Makefile.inc M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/bl31_plat_params.c A src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/symbols.h 7 files changed, 124 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29981/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6bb7196..bf2f01b 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -157,6 +157,8 @@ ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) +ifneq ($(CONFIG_SOC_QUALCOMM_QCS405),y) + ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"") BL31_SOURCE := $(top)/3rdparty/arm-trusted-firmware @@ -235,6 +237,8 @@ endif # CONFIG_ARM64_USE_SECURE_OS +endif # CONFIG_SOC_QUALCOMM_QCS405 + endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index 29960d4..6704d79 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -6,6 +6,7 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select GENERIC_GPIO_LIB select GENERIC_UDELAY diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 40dcb9b..a5f9779 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += rpm_load_reset.c ramstage-y += usb.c ramstage-y += flash_controller.c +ramstage-y += bl31_plat_params.c ################################################################################ @@ -86,6 +87,18 @@ endif ################################################################################ + +BL31_FILE := $(QCS405_BLOB)/bl31.elf +bl31_file := $(shell ls $(BL31_FILE)) +ifneq (,$(findstring $(BL31_FILE),$(bl31_file))) + BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 + $(BL31_CBFS)-file := $(BL31_FILE) + $(BL31_CBFS)-type := payload + $(BL31_CBFS)-compression := none + cbfs-files-y += $(BL31_CBFS) +endif +################################################################################ + QC_SEC_FILE := $(QCS405_BLOB)/qc_sec.mbn qc_sec_file := $(shell ls $(QC_SEC_FILE)) ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) diff --git a/src/soc/qualcomm/qcs405/bl31_plat_params.c b/src/soc/qualcomm/qcs405/bl31_plat_params.c new file mode 100644 index 0000000..68a3c14 --- /dev/null +++ b/src/soc/qualcomm/qcs405/bl31_plat_params.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arm_tf.h> +#include <assert.h> +#include <cbmem.h> +#include <soc/bl31_plat_params.h> + +static struct bl31_plat_param *plat_params; + +void register_bl31_param(struct bl31_plat_param *param) +{ + param->next = plat_params; + plat_params = param; +} + +void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +{ + static struct bl31_u64_param cbtable_param = { + .h = { .type = PARAM_COREBOOT_TABLE, }, + }; + if (!cbtable_param.value) { + cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); + if (cbtable_param.value) + register_bl31_param(&cbtable_param.h); + } + return plat_params; +} diff --git a/src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h b/src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h new file mode 100644 index 0000000..d7a8e28 --- /dev/null +++ b/src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BL31_PLAT_PARAMS_H__ +#define __BL31_PLAT_PARAMS_H__ + +#if 0 +#include <arm-trusted-firmware/plat/qti/common/inc/qti_plat_params.h> +#else +/* param type */ +enum { + PARAM_NONE = 0, + PARAM_COREBOOT_TABLE, +}; + +/* common header for all plat parameter type */ +struct bl31_plat_param { + uint64_t type; + void *next; +}; + +struct bl31_u64_param { + struct bl31_plat_param h; + uint64_t value; +}; +#endif + +void register_bl31_param(struct bl31_plat_param *param); + +#endif/* __BL31_PLAT_PARAMS_H__ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 9e7df11..46d4673 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -51,6 +51,7 @@ REGION(qclib, 0x8C6a000, 0x80000, 4096) //REGION(dcb, 0x8CEa000, 0x4000, 4096) REGION(pmic, 0x8CED000, 0x10000, 4096) + REGION(el3_stack_canary, 0x8CFD000, 0x8, 0x10) BSRAM_END(0x8D80000) DRAM_START(0x80000000) diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 74ba170..28b93f9 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_QUALCOMM_QCS405_SYMBOLS_H_ -#define _SOC_QUALCOMM_QCS405_SYMBOLS_H_ +#ifndef _SOC_QUALCOMM_SDM845_SYMBOLS_H_ +#define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ #include <types.h> @@ -42,4 +42,24 @@ extern u8 _erpm[]; #define _rpm_size (_erpm - _rpm) -#endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ +extern u8 _el3_stack_canary[]; +extern u8 _eel3_stack_canary[]; +#define _el3_stack_canary_size (_eel3_stack_canary - _el3_stack_canary) + +extern u8 _ddr_training[]; +extern u8 _eddr_training[]; +#define _ddr_training_size (_eddr_training - _ddr_training) + +extern u8 _qclib_serial_log[]; +extern u8 _eqclib_serial_log[]; +#define _qclib_serial_log_size (_eqclib_serial_log - _qclib_serial_log) + +extern u8 _limits_cfg[]; +extern u8 _elimits_cfg[]; +#define _limits_cfg_size (_elimits_cfg - _limits_cfg) + +extern u8 _ddr_information[]; +extern u8 _eddr_information[]; +#define _ddr_information_size (_eddr_information - _ddr_information) + +#endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/lynxpoint: Make the finalise handler common
by Patrick Rudolph (Code Review) 30 Nov '18

30 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29975 ) Change subject: sb/intel/lynxpoint: Make the finalise handler common ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Gerrit-Change-Number: 29975 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 14:01:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by Patrick Rudolph (Code Review) 30 Nov '18

30 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 13:59:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: MAINTAINERS: Add Philipp Hug as reviewer for RISC-V
by Jonathan Neuschäfer (Code Review) 30 Nov '18

30 Nov '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29980 Change subject: MAINTAINERS: Add Philipp Hug as reviewer for RISC-V ...................................................................... MAINTAINERS: Add Philipp Hug as reviewer for RISC-V Philipp has been reviewing and writing RISC-V-related code for a while. Change-Id: I3f2d3a61f66343a6e0350909edfe466d2ee6c089 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M MAINTAINERS 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29980/1 diff --git a/MAINTAINERS b/MAINTAINERS index 3df572c..40b4911 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -136,6 +136,7 @@ RISC-V ARCHITECTURE M: Ronald Minnich <rminnich(a)gmail.com> M: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> +R: Philipp Hug <philipp(a)hug.cx> S: Maintained F: src/arch/riscv/ F: src/soc/sifive/ -- To view, visit https://review.coreboot.org/c/coreboot/+/29980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f2d3a61f66343a6e0350909edfe466d2ee6c089 Gerrit-Change-Number: 29980 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newchange

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coreboot-gerrit November 2018