coreboot-gerrit November 2018

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Furquan Shaikh (Code Review) 30 Nov '18

30 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 22:25:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group
by Furquan Shaikh (Code Review) 30 Nov '18

30 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29872 ) Change subject: mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B group ...................................................................... Patch Set 2: > Patch Set 2: Code-Review+1 > > my test result is same as shelley now by > correct the HW re-work > > Would you help to +2 ? > We need it to build the EVT Does APIC_INVERT fail for you too? -- To view, visit https://review.coreboot.org/c/coreboot/+/29872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Gerrit-Change-Number: 29872 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 30 Nov 2018 22:24:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ACPI: Rename FADT model and set it to zero
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29986 Change subject: ACPI: Rename FADT model and set it to zero ...................................................................... ACPI: Rename FADT model and set it to zero INT_MODEL defined in ACPI 1.0 and renamed to reserved in upper versions. The value for this field is zero but 1 is allowed to maintain compatibility with ACPI 1.0. So set this value to zero as we are using ACPI upper than 1.0 Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/acpi.h M src/mainboard/aopen/dxplplusu/fadt.c M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/cyan/fadt.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/rambi/fadt.c M src/mainboard/intel/harcuvar/fadt.c M src/mainboard/intel/strago/fadt.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/lenovo/t400/fadt.c M src/mainboard/lenovo/x200/fadt.c M src/mainboard/purism/librem_bdw/fadt.c M src/mainboard/roda/rk9/fadt.c M src/mainboard/scaleway/tagada/fadt.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 26 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29986/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index cd86e83..b766465 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -489,7 +489,7 @@ struct acpi_table_header header; u32 firmware_ctrl; u32 dsdt; - u8 model; /* Eliminated in ACPI 2.0. Platforms should set + u8 reserved; /* Eliminated in ACPI 2.0. Platforms should set * this field to zero but field values of one * are also allowed to maintain compatibility * with ACPI 1.0. diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index b78a3ed..b6c3d9e 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -45,7 +45,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ fadt->sci_int = 0x9; diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 5a36cb1..736b0db 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -57,7 +57,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = 0; diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index 9ee5c95..e614ce4 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c index 7455d4b..3087dd9 100644 --- a/src/mainboard/google/cyan/fadt.c +++ b/src/mainboard/google/cyan/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index 9ee5c95..e614ce4 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c index d02609b..01b6add 100644 --- a/src/mainboard/google/rambi/fadt.c +++ b/src/mainboard/google/rambi/fadt.c @@ -31,7 +31,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/harcuvar/fadt.c b/src/mainboard/intel/harcuvar/fadt.c index 9f41f64..bc47c59 100644 --- a/src/mainboard/intel/harcuvar/fadt.c +++ b/src/mainboard/intel/harcuvar/fadt.c @@ -36,7 +36,7 @@ fadt->firmware_ctrl = (unsigned long)facs; fadt->dsdt = (unsigned long)dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c index e0e7d44..a8ed861 100644 --- a/src/mainboard/intel/strago/fadt.c +++ b/src/mainboard/intel/strago/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 6f1553c..b3351d9 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -31,7 +31,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index 5596115..3175c7d 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -35,7 +35,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index 5596115..3175c7d 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -35,7 +35,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index fbce9d7..147937b 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -31,7 +31,7 @@ fadt->firmware_ctrl = (u32)facs; fadt->dsdt = (u32)dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (u32)facs; diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index 5596115..3175c7d 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -35,7 +35,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c index 9f41f64..bc47c59 100644 --- a/src/mainboard/scaleway/tagada/fadt.c +++ b/src/mainboard/scaleway/tagada/fadt.c @@ -36,7 +36,7 @@ fadt->firmware_ctrl = (unsigned long)facs; fadt->dsdt = (unsigned long)dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 645aff4..cb4f95d 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -86,7 +86,7 @@ fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 2640a80..2abc7ca 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -198,7 +198,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ /* System Management */ diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index d5bee64..370279c 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -176,7 +176,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = 0; fadt->sci_int = acpi_sci_irq(); diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index e8483a0..20af86e 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -65,7 +65,7 @@ else fadt->dsdt = (uintptr_t)dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 15e05c3..5313b7d 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -69,7 +69,7 @@ else fadt->dsdt = (uintptr_t)dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 - ACPI SCI */ fadt->smi_cmd = 0; /* disable system management mode */ diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index c2d5d19..0a6bc77 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -57,7 +57,7 @@ fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7ae538e..efbe688 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -743,7 +743,7 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index efe5412..be5595d 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -58,7 +58,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ /* System Management */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7dcec50..db49180 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -576,7 +576,7 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ba79e73..6ad6929 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -589,7 +589,7 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e5cbc59..455c785 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -652,7 +652,7 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; -- To view, visit https://review.coreboot.org/c/coreboot/+/29986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Gerrit-Change-Number: 29986 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Makefile.inc: Avoid race condition when using 'make -j<N>'
by Nico Huber (Code Review) 30 Nov '18

30 Nov '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29984 ) Change subject: Makefile.inc: Avoid race condition when using 'make -j<N>' ...................................................................... Patch Set 1: I guess the the now earlier triggered build of `conf` could still col- lide with the one triggered by the oldconfig rule in Makefile. So add the same dependency to the other rule, too? -- To view, visit https://review.coreboot.org/c/coreboot/+/29984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie93eda567f88ca08c97df7e70cdff5b07442747d Gerrit-Change-Number: 29984 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 30 Nov 2018 20:15:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/29917/11/src/northbridge/intel/x4x/early_in… File src/northbridge/intel/x4x/early_init.c: https://review.coreboot.org/#/c/29917/11/src/northbridge/intel/x4x/early_in… PS11, Line 227: reg32 = RCBA32(0x2010); is it needed to read RCBA 0x2010 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 11 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 20:09:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 30 Nov '18

30 Nov '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 ) Change subject: mb/google/sarien: Program HD Audio SVID/SSID ...................................................................... Patch Set 1: > Patch Set 1: > > Could we do this at the SOC level? > > If we had a Kconfig entry in the SOC that allowed the mainboard to define an HDA codec device ID then the SOC level code could have this structure (filled with CONFIG_SUBSYSTEM_VENDOR_ID and something like CONFIG_HDA_CODEC_ID) and pass it to FSP if HDA is enabled. Sure, thought about that before that sounds better. -- To view, visit https://review.coreboot.org/c/coreboot/+/29651 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488 Gerrit-Change-Number: 29651 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 19:29:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/(device/lib/soc): Remove unused variables
by Richard Spiegel (Code Review) 30 Nov '18

30 Nov '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29985 Change subject: src/(device/lib/soc): Remove unused variables ...................................................................... src/(device/lib/soc): Remove unused variables When building grunt with flags set to detect variables that get a value but then are unused, there are 7 instances that causes error (unused variable). In most cases it's enough to simply remove the variable. In one instance, the variable is used to receive the return of a function. For this instance, add a debug print that will use it. On another instance, the variable will be used depending on build options, so the variable must only be created and set if this build option is set. BUG=b:120260448 TEST=Build and boot grunt. Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/device/dram/ddr3.c M src/lib/selfboot.c M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 6 files changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/29985/1 diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index f27fdcb..1f5b7eb 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -136,7 +136,10 @@ u8 reg8; u32 mtb; /* medium time base */ u32 ftb; /* fine time base */ - unsigned int val, param; + unsigned int val; +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) + unsigned int param; +#endif ret = SPD_STATUS_OK; @@ -173,7 +176,9 @@ printram(" Invalid number of memory banks\n"); ret = SPD_STATUS_INVALID_FIELD; } +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) param = 1 << (val + 3); +#endif printram(" Banks : %u\n", param); /* SDRAM capacity */ capacity_shift = reg8 & 0x0f; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 9c52cd6..f1c2ba4 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -144,9 +144,9 @@ { uint8_t *dest; size_t memsz; - struct cbfs_payload_segment *first_segment, *seg, segment; + struct cbfs_payload_segment *seg, segment; - for (first_segment = seg = cbfssegs;; ++seg) { + for (seg = cbfssegs;; ++seg) { printk(BIOS_DEBUG, "Checking segment from ROM address 0x%p\n", seg); cbfs_decode_payload_segment(&segment, seg); dest = (uint8_t *)(uintptr_t)segment.load_addr; diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index 0fffaf3..693c7c5 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -116,10 +116,8 @@ { AGESA_STATUS Status; uintptr_t ResetType; - AMD_CONFIG_PARAMS *StdHeader; ResetType = Data; - StdHeader = ConfigPtr; /* * This should perform the RESET based upon the ResetType, but coreboot diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 317574b..efc948d 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -145,6 +145,7 @@ /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + printk(BIOS_DEBUG, "ACPI GNVS at %p\n", gnvs); } static void lpc_set_resources(struct device *dev) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 749eefe..94242da 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -226,12 +226,9 @@ acpi_header_t *ssdt; acpi_header_t *alib; acpi_header_t *ivrs; - acpi_hest_t *hest; - acpi_bert_t *bert; /* HEST */ current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; acpi_write_hest((void *)current, acpi_fill_hest); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; @@ -249,7 +246,6 @@ printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); } else { current = ALIGN(current, 8); - bert = (acpi_bert_t *)current; acpi_write_bert((void *)current, (uintptr_t)rgn, size); acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 6157e50..bbebf6c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -217,13 +217,10 @@ */ int sb_find_wideio_range(uint16_t start, uint16_t size) { - uint32_t enable_register; int i, index = WIDEIO_RANGE_ERROR; uint16_t end, current_size, start_wideio, end_wideio; end = start + size; - enable_register = pci_read_config32(SOC_LPC_DEV, - LPC_IO_OR_MEM_DECODE_ENABLE); for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { current_size = sb_wideio_size(i); if (current_size == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/29985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead Gerrit-Change-Number: 29985 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove not used variable
by build bot (Jenkins) (Code Review) 30 Nov '18

30 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/29917/11/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/init_cpus.c: https://review.coreboot.org/#/c/29917/11/src/cpu/amd/family_10h-family_15h/… PS11, Line 1061: if ((get_option(&nvram, "cpu_c_states") == CB_SUCCESS) && line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 11 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 16:31:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

Hello Patrick Rudolph, Huang Jin, Julius Werner, Angel Pons, York Yang, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#11). Change subject: src: Remove not used variable ...................................................................... src: Remove not used variable Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm64/boot.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/early_init.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/quark/i2c.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 22 files changed, 25 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 11 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src: Remove not used variable
by HAOUAS Elyes (Code Review) 30 Nov '18

30 Nov '18

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Remove not used variable ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/29917/10/src/northbridge/intel/x4x/early_in… File src/northbridge/intel/x4x/early_init.c: https://review.coreboot.org/#/c/29917/10/src/northbridge/intel/x4x/early_in… PS10, Line 227: reg32 = RCBA32(0x2010); is it needed to read RCBA32(0x2010) ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 10 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Nov 2018 16:23:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2018