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Change in coreboot[master]: mb/intel/coffeelake_rvp: Add HDA controller driver support for coffee...
by PraveenX Hodagatta Pranesh (Code Review) 12 Oct '18

12 Oct '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/29067 Change subject: mb/intel/coffeelake_rvp: Add HDA controller driver support for coffee lake ...................................................................... mb/intel/coffeelake_rvp: Add HDA controller driver support for coffee lake this patch adds following changes - Select common coreboot HDA driver in CNL soc Kconfig. - Add Audio controller device id to common HDA driver. - Add audio … [View More]verb table for coffee lake RVP11 & RVP8. BUG: None TEST: boot to yocto linux and windows os on CFL RVP11 & RVP8. verified audio playback and record functionality over anolog audio jack & HDMI display. Change-Id: I567e317c0e9ac9f91e159866c7f896e4c101712b Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Makefile.inc A src/mainboard/intel/coffeelake_rvp/hda_verb.c A src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h A src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/hda/hda.c 7 files changed, 422 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29067/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 83ab9c5..f69bb71 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -14,6 +14,7 @@ select SOC_INTEL_COFFEELAKE select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 config MAINBOARD_DIR string diff --git a/src/mainboard/intel/coffeelake_rvp/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/Makefile.inc index 2746453..0b70fdd 100644 --- a/src/mainboard/intel/coffeelake_rvp/Makefile.inc +++ b/src/mainboard/intel/coffeelake_rvp/Makefile.inc @@ -24,6 +24,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-y += hda_verb.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include diff --git a/src/mainboard/intel/coffeelake_rvp/hda_verb.c b/src/mainboard/intel/coffeelake_rvp/hda_verb.c new file mode 100644 index 0000000..077c8ed --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/hda_verb.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) +#include "variant/hda_verb.h" +#endif diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h new file mode 100644 index 0000000..f921f3f --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/include/variant/hda_verb.h @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Damien Zammit <damien(a)zamaudio.com> + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + + /* + * VerbTable: CFL Display Audio Codec + * Revision ID = 0xFF + * Codec Vendor: 0x8086280B + */ + + 0x8086280B, + 0xFFFFFFFF, + 0x00000005, + + /* + * Display Audio Verb Table + * For GEN9, the Vendor Node ID is 08h + * Port to be exposed to the inbox driver in the vanilla mode + * PORT C - BIT[7:6] = 01b + */ + 0x00878140, + 0x00878140, + 0x00878140, + 0x00878140, + /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ + 0x00571C10, + 0x00571D00, + 0x00571E56, + 0x00571F18, + /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ + 0x00671C20, + 0x00671D00, + 0x00671E56, + 0x00671F18, + /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ + 0x00771C30, + 0x00771D00, + 0x00771E56, + 0x00771F18, + /* Disable the third converter and third Pin (NID 08h) */ + 0x00878140, + 0x00878140, + 0x00878140, + 0x00878140, + + /* ALC700 */ + 0x10EC0700, + 0xFFFFFFFF, + 0x00000015, + + /* + * HDA Codec Subsystem ID Verb-table + * HDA Codec Subsystem ID : 0x10EC112C + */ + 0x0017202C, + 0x00172111, + 0x001722EC, + 0x00172310, + + /* + * Pin Widget Verb-table + * Widget node 0x01 + */ + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + /* Pin widget 0x12 - DMIC */ + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + /* Pin widget 0x13 - DMIC */ + 0x01371CF0, + 0x01371D11, + 0x01371E11, + 0x01371F41, + /* Pin widget 0x14 - FRONT (Port-D) */ + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + /* Pin widget 0x15 - I2S-OUT */ + 0x01571C10, + 0x01571D01, + 0x01571E17, + 0x01571F90, + /* Pin widget 0x16 - LINE3 (Port-B) */ + 0x01671C20, + 0x01671D10, + 0x01671E01, + 0x01671F01, + /* Pin widget 0x17 - I2S-OUT */ + 0x01771CF0, + 0x01771D11, + 0x01771E11, + 0x01771F41, + /* Pin widget 0x18 - I2S-IN */ + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971C30, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01B71C40, + 0x01B71D90, + 0x01B71EA1, + 0x01B71F01, + /* Pin widget 0x1D - PC-BEEP */ + 0x01D71C69, + 0x01D71D84, + 0x01D71E45, + 0x01D71F40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + /* Pin widget 0x21 - P-OUT (Port-I) */ + 0x02171C2F, + 0x02171D10, + 0x02171E21, + 0x02171F02, + /* Pin widget 0x29 - I2S-IN */ + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + /* + * Widget node 0x20 : MIC2-Vrefo-R and MIC2-vrefo-L + * to independent control + */ + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + /* + * Widget node 0x20 - 2 : Line2-JD gating MIC2-Vrefo-R, + * P-JD gating MIC2-vrefo-L + */ + 0x0205006B, + 0x02044260, + 0x05B50010, + 0x05B45C1D, + + /* Widget node 0X20 for ALC1305 */ + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h new file mode 100644 index 0000000..f921f3f --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/include/variant/hda_verb.h @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Damien Zammit <damien(a)zamaudio.com> + * Copyright 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + + /* + * VerbTable: CFL Display Audio Codec + * Revision ID = 0xFF + * Codec Vendor: 0x8086280B + */ + + 0x8086280B, + 0xFFFFFFFF, + 0x00000005, + + /* + * Display Audio Verb Table + * For GEN9, the Vendor Node ID is 08h + * Port to be exposed to the inbox driver in the vanilla mode + * PORT C - BIT[7:6] = 01b + */ + 0x00878140, + 0x00878140, + 0x00878140, + 0x00878140, + /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */ + 0x00571C10, + 0x00571D00, + 0x00571E56, + 0x00571F18, + /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */ + 0x00671C20, + 0x00671D00, + 0x00671E56, + 0x00671F18, + /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */ + 0x00771C30, + 0x00771D00, + 0x00771E56, + 0x00771F18, + /* Disable the third converter and third Pin (NID 08h) */ + 0x00878140, + 0x00878140, + 0x00878140, + 0x00878140, + + /* ALC700 */ + 0x10EC0700, + 0xFFFFFFFF, + 0x00000015, + + /* + * HDA Codec Subsystem ID Verb-table + * HDA Codec Subsystem ID : 0x10EC112C + */ + 0x0017202C, + 0x00172111, + 0x001722EC, + 0x00172310, + + /* + * Pin Widget Verb-table + * Widget node 0x01 + */ + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + /* Pin widget 0x12 - DMIC */ + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + /* Pin widget 0x13 - DMIC */ + 0x01371CF0, + 0x01371D11, + 0x01371E11, + 0x01371F41, + /* Pin widget 0x14 - FRONT (Port-D) */ + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + /* Pin widget 0x15 - I2S-OUT */ + 0x01571C10, + 0x01571D01, + 0x01571E17, + 0x01571F90, + /* Pin widget 0x16 - LINE3 (Port-B) */ + 0x01671C20, + 0x01671D10, + 0x01671E01, + 0x01671F01, + /* Pin widget 0x17 - I2S-OUT */ + 0x01771CF0, + 0x01771D11, + 0x01771E11, + 0x01771F41, + /* Pin widget 0x18 - I2S-IN */ + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + /* Pin widget 0x19 - MIC2 (Port-F) */ + 0x01971C30, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + /* Pin widget 0x1A - LINE1 (Port-C) */ + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + /* Pin widget 0x1B - LINE2 (Port-E) */ + 0x01B71C40, + 0x01B71D90, + 0x01B71EA1, + 0x01B71F01, + /* Pin widget 0x1D - PC-BEEP */ + 0x01D71C69, + 0x01D71D84, + 0x01D71E45, + 0x01D71F40, + /* Pin widget 0x1E - S/PDIF-OUT */ + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + /* Pin widget 0x1F - S/PDIF-IN */ + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + /* Pin widget 0x21 - P-OUT (Port-I) */ + 0x02171C2F, + 0x02171D10, + 0x02171E21, + 0x02171F02, + /* Pin widget 0x29 - I2S-IN */ + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + /* + * Widget node 0x20 : MIC2-Vrefo-R and MIC2-vrefo-L + * to independent control + */ + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + /* Widget node 0x20 - 1 */ + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + /* + * Widget node 0x20 - 2 : Line2-JD gating MIC2-Vrefo-R, + * P-JD gating MIC2-vrefo-L + */ + 0x0205006B, + 0x02044260, + 0x05B50010, + 0x05B45C1D, + + /* Widget node 0X20 for ALC1305 */ + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 3f5210a..bca3618 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -7,6 +7,7 @@ bool default n select SOC_INTEL_CANNONLAKE + select SOC_INTEL_COMMON_BLOCK_HDA help Intel Coffeelake support diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 2409b75..50f847e 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -75,6 +75,7 @@ PCI_DEVICE_ID_INTEL_SKL_AUDIO, PCI_DEVICE_ID_INTEL_KBL_AUDIO, PCI_DEVICE_ID_INTEL_CNL_AUDIO, + PCI_DEVICE_ID_INTEL_CNP_H_AUDIO, 0 }; -- To view, visit https://review.coreboot.org/29067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I567e317c0e9ac9f91e159866c7f896e4c101712b Gerrit-Change-Number: 29067 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> [View Less]

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Add support for new coffee lake RVP8
by PraveenX Hodagatta Pranesh (Code Review) 12 Oct '18

12 Oct '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/29066 Change subject: mb/intel/coffeelake_rvp: Add support for new coffee lake RVP8 ...................................................................... mb/intel/coffeelake_rvp: Add support for new coffee lake RVP8 - Add new mainboard variant coffee lake RVP8, which is CRB for coffee lake-s processor, support U-DIMM DDR4 memory module. - Modify cfl_h devicetree to enable IO devices, configure … [View More]PCIE root port clock source, usb over current pin as per board schematics. - Select cannonlake PCH-H chipset config for both cfl_h & cfl_s. - Add GPIO table as per board schematics. BUG= None TEST= Build and flash, confirm boot into yocoto & windows OS on both cfl RVP11 & RVP8 platform. verified PCI, USB, ethernet, SATA, display, power functionalities. Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb 5 files changed, 531 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29066/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 311f6d1..83ab9c5 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP +if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -13,6 +13,7 @@ select DRIVERS_I2C_GENERIC select SOC_INTEL_COFFEELAKE select SOC_INTEL_CANNONLAKE_MEMCFG_INIT + select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 config MAINBOARD_DIR string @@ -23,6 +24,7 @@ default "cfl_u" if BOARD_INTEL_COFFEELAKE_RVPU default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11 default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP + default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8 config MAINBOARD_PART_NUMBER string @@ -38,6 +40,7 @@ config MAX_CPUS int + default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 default 8 config DEVICETREE diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index f9f82a2..773c83a 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -6,3 +6,5 @@ bool "-> Coffeelake H SO-DIMM DDR4 RVP11" config BOARD_INTEL_WHISKEYLAKE_RVP bool "-> Whiskeylake U DDR4 RVP" +config BOARD_INTEL_COFFEELAKE_RVP8 + bool "-> Coffeelake S U-DIMM DDR4 RVP8" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index 821cba3..fc35050 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -17,6 +17,7 @@ #include <baseboard/variants.h> #include <commonlib/helpers.h> +#if !IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) static const struct pad_config gpio_table[] = { /* GPPC */ /* A0 : RCINB_TIME_SYNC_1 */ @@ -285,6 +286,310 @@ /* GPD_11 : LANPHYPC */ }; +#else +static const struct pad_config gpio_table[] = { + /* GPPC */ + /* A0 : RCIN_ESPI_ALERT1 */ + /* A1 : ESPI_IO_0 */ + /* A2 : ESPI_IO_1 */ + /* A3 : ESPI_IO_2 */ + /* A4 : ESPI_IO_3 */ + /* A5 : ESPI_CSB */ + /* A6 : SERIRQ */ + /* A7 : PRIQAB_ESPI_ALERT0 */ + /* A8 : CLKRUNB */ + PAD_CFG_GPO(GPP_A8, 1, PLTRST), + /* A9 : CLKOUT_LPC_0_ESPI_CLK */ + /* A10 : CLKOUT_LPC_1 */ + /* A11 : I2S_CODEC_INT */ + PAD_CFG_GPI_APIC_LOW(GPP_A11, UP_20K, PLTRST), + /* A12 : BM_BUSYB_ISH__GP_6 */ + /* A13 : SUSWARNB_SUSPWRDNACK */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* A14 : SUS_STATB_ESPI_RESETB */ + /* A15 : SUSACKB */ + PAD_CFG_GPO(GPP_A15, 1, PLTRST), + /* A16 : TCH_PAD_INT_N */ + PAD_CFG_GPI_APIC(GPP_A16, NONE, PLTRST, LEVEL, INVERT), + /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */ + /* A18 : ISH_GP_0 */ + /* A19 : ISH_GP_1 */ + /* A20 : ISH_GP_2 */ + /* A21 : ISH_GP_3 */ + /* A22 : ISH_GP_4 */ + /* A23 : ISH_GP_5 */ + + /* B0 : SPI_TPM_INIT */ + PAD_CFG_GPI_SCI_LOW(GPP_B0, UP_20K, DEEP, EDGE_SINGLE), + /* B1 : GSPI1_CS1 */ + /* B2 : VRALERTB */ + PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE), + /* B3 : BT_RF_KILL */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), + /* B4 : WIFI_RF_KILL */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B5 : SRCCLKREQB_0 */ + /* B6 : SRCCLKREQB_1 */ + /* B7 : SRCCLKREQB_2 */ + /* B8 : SRCCLKREQB_3 */ + /* B9 : SRCCLKREQB_4 */ + /* B10 : SRCCLKREQB_5 */ + /* B11 : I2S_MCLK */ + /* B12 : SLP_S0B */ + /* B13 : PLTRSTB */ + /* B14 : SPKR */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + /* B15 : GSPI0_CS0B */ + PAD_CFG_GPO(GPP_B15, 0, DEEP), + /* B16 : GSPI0_CLK */ + PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE), + /* B17 : GSPI0_MISO */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), + /* B18 : I2C_TCH_PNL_PWREN */ + PAD_CFG_GPO(GPP_B18, 1, PLTRST), + /* B19 : GSPI1_CS0B */ + /* B20 : GSPI1_CLK */ + /* B21 : GSPI1_MISO */ + /* B22 : GSP1_MOSI */ + /* B23 : EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + + /* C0 : SMBCLK */ + /* C1 : SMBDATA */ + /* C2 : SMBALERTB */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), + /* C3 : SML0CLK */ + /* C4 : SML0DATA */ + /* C5 : WIFI_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL), + /* C6 : SML1CLK */ + /* C7 : SML1DATA */ + /* C8 : UART0_RXD */ + PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT), + /* C9 : UART0_TXD */ + PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE), + /* C10 : UART0_RTSB */ + PAD_CFG_GPO(GPP_C10, 0, PLTRST), + /* C11 : UART0_CTSB */ + PAD_CFG_TERM_GPO(GPP_C11, 1, UP_20K, DEEP), + /* C12 : UART1_RXD_ISH_UART1_RXD */ + PAD_CFG_GPO(GPP_C12, 1, PLTRST), + /* C13 : UART1_RXD_ISH_UART1_TXD */ + /* C14 : SSD1_RESET */ + PAD_CFG_GPO(GPP_C14, 1, PLTRST), + /* C15 : SSD2_RESET */ + PAD_CFG_GPO(GPP_C15, 1, PLTRST), + /* C16 : I2C0_SDA */ + /* C17 : I2C0_SCL */ + /* C18 : I2C1_SDA */ + /* C19 : I2C1_SCL */ + /* C20 : UART2_RXD */ + /* C21 : UART2_TXD */ + /* C22 : UART2_RTSB */ + /* C23 : UART2_CTSB */ + + /* D0 : SPI1_CSB_BK_0 */ + /* D1 : SPI1_CLK_BK_1 */ + /* D2 : SPI1_MISO_IO_1_BK_2 */ + /* D3 : SPI1_MOSI_IO_0_BK_3 */ + /* D4 : IMGCLKOUT_0_BK_4 */ + /* D5 : ISH_I2C0_SDA */ + /* D6 : ISH_I2C0_SCL */ + /* D7 : SSP2_RXD */ + PAD_CFG_GPI_INT(GPP_D7, NONE, PLTRST, LEVEL), + /* D8 : SSP2_SCLK */ + PAD_CFG_GPI_INT(GPP_D8, NONE, PLTRST, LEVEL), + /* D9 : ISH_SPI_CSB */ + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + /* D10 : ISH_SPI_CLK */ + PAD_CFG_GPI_APIC(GPP_D10, UP_20K, PLTRST, LEVEL, INVERT), + /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */ + PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL), + /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */ + /* D13 : ISH_UART0_RXD_SML0BDATA */ + PAD_CFG_GPO(GPP_D13, 1, DEEP), + /* D14 : ISH_UART0_TXD_SML0BCLK */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */ + /* D16 : ISH_UART0_CTSB_SML0BALERTB */ + PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL), + /* D17 : DMIC_CLK_1_SNDW3_CLK */ + /* D18 : DMIC_DATA_1_SNDW3_DATA */ + /* D19 : DMIC_CLK_0_SNDW4_CLK */ + /* D20 : DMIC_DATA_0_SNDW4_DATA */ + /* D21 : SPI1_IO_2 */ + PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), + /* D22 : SPI1_IO_3 */ + PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), + /* D23 : ISH_I2C2_SCL_I2C3_SCL */ + + /* E0 : SATAXPCIE_0_SATAGP_0 */ + /* E1 : SATAXPCIE_1_SATAGP_1 */ + /* E2 : SATAXPCIE_2_SATAGP_2 */ + PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST), + /* E3 : EC_SMI_N */ + PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), + /* E4 : SATA_DEVSLP_0 */ + PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP_1 */ + /* E6 : SATA_DEVSLP_2 */ + PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE), + /* E7 : CPU_GP_1 */ + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE), + /* E8 : SATA_LEDB */ + /* E9 : USB2_OCB_0 */ + /* E10 : USB2_OCB_1 */ + /* E11 : USB2_OCB_2 */ + /* E12 : USB2_OCB_3 */ + + /* F0 : SATAXPCIE_3_SATAGP_3 */ + /* F1 : SATAXPCIE_4_SATAGP_4 */ + /* F2 : SATAXPCIE_5_SATAGP_5 */ + /* F3 : SATAXPCIE_6_SATAGP_6 */ + /* F4 : SLOT2_RST_N */ + PAD_CFG_GPO(GPP_F4, 1, PLTRST), + /* F5 : SATA_DEVSLP_3 */ + /* F6 : SATA_DEVSLP_4 */ + /* F7 : ME_PG_LED */ + PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, LEVEL), + /* F8 : SATA_DEVSLP_6 */ + /* F9 : PEG_SLOT_RST */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* F10 : BIOS_RECOVERY */ + PAD_CFG_GPI_INT(GPP_F10, NONE, PLTRST, LEVEL), + /* F11 : SATA_SLOAD */ + /* F12 : SATA_S-DATA_OUT1 */ + /* F13 : SATA_S-DATA_OUT0 */ + /* F14 : PS_ON */ + /* F15 : USB2_OC_4 */ + /* F16 : USB2_OC_5 */ + /* F17 : USB2_OC_6 */ + /* F18 : USB2_OC_7 */ + /* F19 : EDP_VDDEN */ + /* F20 : EDP_BKLTEN */ + /* F21 : EDP_BKLTCTL */ + /* F22 : DDPF_C_TRLCLK */ + /* F23 : DDPF_C_TRLDATA */ + + /* G0 : SD_DATA */ + /* G1 : SD_DATA0 */ + /* G2 : SD_DATA1 */ + /* G3 : SD_DATA2 */ + /* G4 : SD_DATA3 */ + /* G5 : GPP_G_5_SD3_CDB */ + PAD_CFG_NF(GPP_G5, UP_20K, DEEP, GPIO), + /* G6 : SD_CLK */ + /* G7 : GPP_G_7_SD3_WP */ + PAD_CFG_NF(GPP_G7, UP_20K, DEEP, GPIO), + + /* H0 : SRCCLKREQB_6 */ + /* H1 : SRCCLKREQB_7 */ + /* H2 : SRCCLKREQB_8 */ + /* H3 : SRCCLKREQB_9 */ + /* H4 : SRCCLKREQB_10 */ + /* H5 : SRCCLKREQB_11 */ + /* H6 : SRCCLKREQB_12 */ + /* H7 : SRCCLKREQB_13 */ + /* H8 : SRCCLKREQB_14 */ + /* H9 : SRCCLKREQB_15 */ + /* H10 : Audio Power Enable */ + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + /* H11 : SML_2_DATA */ + /* H12 : SML_2_ALERT */ + /* H13 : SML_3_CLK */ + /* H14 : SML_3_DATA */ + /* H15 : SML_3_ALERT */ + /* H16 : TBT_CIO_PWREN */ + PAD_CFG_GPO(GPP_H16, 1, PLTRST), + /* H17 : TBT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + /* H18 : SML_4_ALERT */ + /* H19 : ISH_I2C0_SDA */ + /* H20 : ISH_I2C0_SCL */ + /* H21 : ISH_I2C1_SDA */ + /* H22 : ISH_I2C1_SCL */ + /* H23 : TBT_CIO_PLUG_EVENT_N */ + PAD_CFG_GPI_SCI_LOW(GPP_H23, NONE, PLTRST, EDGE_SINGLE), + + /* I0 : DDPB_HPD_0 */ + /* I1 : DDPC_HPD_1 */ + /* I2 : DPPD_HPD_2 */ + /* I3 : DPPE_HPD_3 */ + /* I4 : EDP_HPD */ + /* I5 : DDPB_C_TRLCLK */ + /* I6 : DDPB_C_TRLDATA */ + /* I7 : DDPC_C_TRLCLK */ + /* I8 : DDPC_C_TRLDATA */ + /* I9 : DDPD_C_TRLCLK */ + /* I10 : DDPD_C_TRLDATA */ + /* I11 : M2_SKT2_C_FG0 */ + /* I12 : M2_SKT2_CFG1 */ + /* I13 : M2_SKT2_C_FG2 */ + /* I14 : M2_SKT2_C_FG3 */ + + /* J0 : I2C_TCH_PNL_INT */ + PAD_CFG_GPI_APIC(GPP_J0, UP_20K, PLTRST, EDGE_SINGLE, INVERT), + /* J1 : CPU_C10_GATE */ + /* J2 : FPS_INT_N */ + PAD_CFG_GPI_APIC(GPP_J2, NONE, PLTRST, EDGE_SINGLE, NONE), + /* J3 : FPS_RST_N */ + PAD_CFG_GPO(GPP_J3, 1, PLTRST), + /* J4 : CNV_BRI_DT_UART0_RTS */ + /* J5 : CNV_BRI_RSP_UART0_RXD */ + /* J6 : CNV_RGI_DT_UART0_TXD */ + /* J7 : CNV_RGI_RSP_UART0_CTS */ + /* J8 : CNV_M_FUART2_RXD */ + /* J9 : CNV_M_FUART2_TXD */ + /* J10 : I2C_TCH_PNL_RST_N */ + PAD_CFG_GPO(GPP_J10, 1, PLTRST), + /* J11 : SPEAKER_PD */ + PAD_CFG_GPO(GPP_J11, 1, PLTRST), + + /* K0 : GPP_K0 */ + /* K1 : SATA_ODD_PWRGT_R */ + PAD_CFG_GPO(GPP_K1, 1, PLTRST), + /* K2 : SATA_ODD_DA_N */ + PAD_CFG_GPI_SCI_HIGH(GPP_K2, NONE, PLTRST, EDGE_SINGLE), + /* K3 : GPP_K3 */ + /* K4 : GPP_K4 */ + /* K5 : GPP_K5 */ + /* K6 : GPP_K6 */ + /* K7 : GPP_K7 */ + /* K8 : GPP_K8 */ + /* K9 : GPP_K9 */ + /* K10 : GPP_K10 */ + /* K11 : RUNTIME_SCI */ + PAD_CFG_GPI_SCI_LOW(GPP_K11, UP_20K, PLTRST, LEVEL), + /* K12 : GSXDOUT */ + /* K13 : GSXSLOAD */ + /* K14 : GSXDIN */ + /* K15 : GSXSRESET */ + /* K16 : GSXCLK */ + /* K17 : ADR_COMPLETE */ + /* K18 : SLOT2_WAKE_N */ + PAD_CFG_GPI_SCI_LOW(GPP_K18, NONE, PLTRST, LEVEL), + /* K19 : SMI */ + /* K20 : GPP_K20 */ + /* K21 : GPP_K21 */ + /* K22 : IMGCLKOUT_0 */ + /* K23 : IMGCLKOUT_1 */ + + /* GPD */ + /* GPD_0 : BATLOWB */ + /* GPD_1 : ACPRESENT */ + /* GPD_2 : LAN_WAKEB */ + /* GPD_3 : PWRBTNB */ + /* GPD_4 : SLP_S3B */ + /* GPD_5 : SLP_S4B */ + /* GPD_6 : SLP_AB */ + /* GPD_7 : GPD_7 */ + /* GPD-8 : SUSCLK */ + /* GPD-9 : SLP_WLANB */ + /* GPD-10 : SLP_5B */ + /* GPD_11 : LANPHYPC */ +}; +#endif + /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 9115fd9..4a2fad9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -6,31 +6,48 @@ # FSP configuration register "SaGv" = "3" + register "RMT" = "1" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC7)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC7)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC7)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC4)" register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC7)" - register "PchHdaDspEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" @@ -46,13 +63,25 @@ register "PcieRpEnable[11]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[17]" = "1" + register "PcieRpEnable[18]" = "1" + register "PcieRpEnable[19]" = "1" + register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[21]" = "1" + register "PcieRpEnable[22]" = "1" + register "PcieRpEnable[23]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" - register "PcieClkSrcUsage[3]" = "14" - register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[5]" = "1" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "0x6" + register "PcieClkSrcUsage[4]" = "0x18" + register "PcieClkSrcUsage[5]" = "14" + register "PcieClkSrcUsage[8]" = "0x40" + register "PcieClkSrcUsage[9]" = "PCIE_CLK_LAN" register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" @@ -60,15 +89,14 @@ register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # GPIO for SD card detect - register "sdcard_cd_gpio" = "GPP_G5" - - # Enable S0ix - register "s0ix_enable" = "1" + # HECI + register "HeciEnabled" = "1" device domain 0 on device pci 00.0 on end # Host Bridge @@ -79,29 +107,19 @@ device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on end # CNVi wifi device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ALPS0001"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "hid_desc_reg_offset" = "0x1" - device i2c 2C on end - end - end # I2C 0 + device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 off end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 @@ -128,9 +146,9 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA + device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 on end # GbE end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb new file mode 100644 index 0000000..5a3d4ce --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb @@ -0,0 +1,161 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "3" + register "RMT" = "1" + register "SmbusEnable" = "1" + register "ScsEmmcHs400Enabled" = "1" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC5)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC6)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC6)" + register "usb2_ports[13]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC3)" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" + register "PcieRpEnable[16]" = "1" + register "PcieRpEnable[17]" = "1" + register "PcieRpEnable[18]" = "1" + register "PcieRpEnable[19]" = "1" + register "PcieRpEnable[20]" = "1" + register "PcieRpEnable[21]" = "1" + register "PcieRpEnable[22]" = "1" + register "PcieRpEnable[23]" = "1" + + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "0x6" + register "PcieClkSrcUsage[4]" = "0x18" + register "PcieClkSrcUsage[5]" = "1" + register "PcieClkSrcUsage[6]" = "0x8" + register "PcieClkSrcUsage[8]" = "0x40" + register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[10]" = "0x14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[6]" = "6" + register "PcieClkSrcClkReq[8]" = "8" + register "PcieClkSrcClkReq[9]" = "9" + register "PcieClkSrcClkReq[10]" = "10" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # HECI + register "HeciEnabled" = "1" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on end # CNVi wifi + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C 0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 X4 SLOT 1 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1b.0 on end # PCI Express Port 17 + device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end -- To view, visit https://review.coreboot.org/29066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14 Gerrit-Change-Number: 29066 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> [View Less]

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Change in coreboot[master]: cpu/amd{family15}: Use common SMM_BASE_MSR
by Elyes HAOUAS (Code Review) 12 Oct '18

12 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29065 Change subject: cpu/amd{family15}: Use common SMM_BASE_MSR ...................................................................... cpu/amd{family15}: Use common SMM_BASE_MSR Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/pi/00630F01/model_15_init.c M src/include/cpu/amd/amdfam15.h 3 … [View More]files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29065/1 diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index fdcb9a2..ce0a257 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -15,7 +15,9 @@ #include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/amd/msr.h> #include <cpu/x86/smm.h> +#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <device/device.h> #include <string.h> @@ -24,7 +26,6 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/agesa_helper.h> @@ -108,9 +109,9 @@ printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); /* Set SMM base address for this CPU */ - msr = rdmsr(MSR_SMM_BASE); + msr = rdmsr(SMM_BASE_MSR); msr.lo = SMM_BASE - (cpu_idx * 0x400); - wrmsr(MSR_SMM_BASE, msr); + wrmsr(SMM_BASE_MSR, msr); /* Enable the SMM memory window */ msr = rdmsr(MSR_SMM_MASK); diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 0269a1e..803919a 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -15,8 +15,10 @@ #include <console/console.h> #include <cpu/x86/msr.h> -#include <cpu/x86/smm.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <string.h> @@ -25,7 +27,6 @@ #include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> @@ -105,9 +106,9 @@ printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); /* Set SMM base address for this CPU */ - msr = rdmsr(MSR_SMM_BASE); + msr = rdmsr(SMM_BASE_MSR); msr.lo = SMM_BASE - (cpu_idx * 0x400); - wrmsr(MSR_SMM_BASE, msr); + wrmsr(SMM_BASE_MSR, msr); /* Enable the SMM memory window */ msr = rdmsr(MSR_SMM_MASK); diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 271af8a..164ca22 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -189,7 +189,6 @@ return MCA_ERRTYPE_UNKNOWN; } -#define MSR_SMM_BASE 0xC0010111 #define MSR_TSEG_BASE 0xC0010112 #define MSR_SMM_MASK 0xC0010113 # define SMM_TSEG_VALID (1 << 1) -- To view, visit https://review.coreboot.org/29065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Gerrit-Change-Number: 29065 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> [View Less]

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Change in coreboot[master]: riscv: add support to block smp in each stage
by Xiang Wang (Code Review) 12 Oct '18

12 Oct '18

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29024 to look at the new patch set (#11). Change subject: riscv: add support to block smp in each stage ...................................................................... riscv: add support to block smp in each stage Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/… [View More]

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by Xiang Wang (Code Review) 12 Oct '18

12 Oct '18

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29023 to look at the new patch set (#7). Change subject: riscv: add support smp_pause / smp_resume ...................................................................... riscv: add support smp_pause / smp_resume See https://doc.coreboot.org/arch/riscv/ we know that we need to execute smp_pause at the start of each stage and smp_resume … [View More]

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Change in coreboot[master]: mb/lenovo/*/acpi: Store the requested state wake state for bluetooth ...
by Peter Lemenkov (Code Review) 12 Oct '18

12 Oct '18

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/29064 to review the following change. Change subject: mb/lenovo/*/acpi: Store the requested state wake state for bluetooth and WWAN. ...................................................................... mb/lenovo/*/acpi: Store the requested state wake state for bluetooth and WWAN. L520 and T420 should also use it - platforms are very similar to t420s and t530. Z61t is based on T60/X60, … [View More]X131e is based on X230 so commit with Change-Id I13c08b8c6b1bf0f3deb25a464b26880d8469c005 should be applied as well. All four platforms are using ec/lenovo/h8 embedded controller. Change-Id: Ib177f024871e82979dd430da86f1551aef14d446 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/l520/acpi/platform.asl M src/mainboard/lenovo/t420/acpi/platform.asl M src/mainboard/lenovo/x131e/acpi/platform.asl M src/mainboard/lenovo/z61t/acpi/platform.asl 4 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/29064/1 diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl index c7aea62..2d016fa 100644 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -19,6 +19,11 @@ /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) + + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl index 6f26c5a..e4c8a24 100644 --- a/src/mainboard/lenovo/t420/acpi/platform.asl +++ b/src/mainboard/lenovo/t420/acpi/platform.asl @@ -32,6 +32,9 @@ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl index 9cd327a..bf686f4 100644 --- a/src/mainboard/lenovo/x131e/acpi/platform.asl +++ b/src/mainboard/lenovo/x131e/acpi/platform.asl @@ -32,6 +32,9 @@ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/z61t/acpi/platform.asl b/src/mainboard/lenovo/z61t/acpi/platform.asl index 006b6f0..f9e991b 100644 --- a/src/mainboard/lenovo/z61t/acpi/platform.asl +++ b/src/mainboard/lenovo/z61t/acpi/platform.asl @@ -29,6 +29,9 @@ Method(_WAK,1) { + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + // CPU specific part // Notify PCI Express slots in case a card -- To view, visit https://review.coreboot.org/29064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib177f024871e82979dd430da86f1551aef14d446 Gerrit-Change-Number: 29064 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> [View Less]

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Change in coreboot[master]: mediatek/mt8183: Add AUXADC driver
by Tristan Hsieh (Code Review) 12 Oct '18

12 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29061 to look at the new patch set (#2). Change subject: mediatek/mt8183: Add AUXADC driver ...................................................................... mediatek/mt8183: Add AUXADC driver We plan to get board id and ram code from AUXADC on Kukui. Add AUXADC driver to support it. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: … [View More]

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Change in coreboot[master]: google/kukui: Add board id support
by Tristan Hsieh (Code Review) 12 Oct '18

12 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29062 to look at the new patch set (#2). Change subject: google/kukui: Add board id support ...................................................................... google/kukui: Add board id support Get board id from AUXIN4 and ram code from AUXIN3. BUG=b:80501386 BRANCH=none TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0. AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1. Change-… [View More]

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Change in coreboot[master]: tpm2/tlcl_send_startup: should pass on TPM_E_INVALID_POSTINIT
by Joel Kitching (Code Review) 12 Oct '18

12 Oct '18

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/29063 Change subject: tpm2/tlcl_send_startup: should pass on TPM_E_INVALID_POSTINIT ...................................................................... tpm2/tlcl_send_startup: should pass on TPM_E_INVALID_POSTINIT In src/security/tpm/tspi/tspi.c:tpm_setup(), different S3 resume cases are handled. One of those is when TPM returns TPM_E_INVALID_POSTINIT, in which case we can assume that TPM maintains power … [View More]

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by Xiang Wang (Code Review) 12 Oct '18

12 Oct '18

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29023 to look at the new patch set (#6). Change subject: riscv: add support smp_pause / smp_resume ...................................................................... riscv: add support smp_pause / smp_resume See https://doc.coreboot.org/arch/riscv/ we know that we need to execute smp_pause at the start of each stage and smp_resume … [View More]

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coreboot-gerrit October 2018