coreboot-gerrit October 2018

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Change in coreboot[master]: amdfam10: Convert to `board_reset()`
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29058 Change subject: amdfam10: Convert to `board_reset()` ...................................................................... amdfam10: Convert to `board_reset()` And here comes the mess... This just renames do_hard_reset() to do_board_reset() and keeps current behaviour. As these are never called from chipset or board code but only from common code, it's likely that their implementations are untested and not what we actually want. Also note, that sometimes implementations for rom- and ramstage differ considerably. Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/asus/kcma-d8/Kconfig M src/mainboard/asus/kfsn4-dre/Kconfig M src/mainboard/asus/kgpe-d16/Kconfig M src/southbridge/amd/amd8111/Kconfig M src/southbridge/amd/amd8111/early_ctrl.c M src/southbridge/amd/amd8111/reset.c M src/southbridge/amd/sb700/Kconfig M src/southbridge/amd/sb700/reset.c M src/southbridge/amd/sb800/Kconfig M src/southbridge/amd/sb800/early_setup.c M src/southbridge/amd/sb800/reset.c M src/southbridge/broadcom/bcm5785/Kconfig M src/southbridge/broadcom/bcm5785/early_setup.c M src/southbridge/broadcom/bcm5785/reset.c M src/southbridge/nvidia/ck804/Kconfig M src/southbridge/nvidia/ck804/early_setup.c M src/southbridge/nvidia/ck804/early_setup_car.c M src/southbridge/nvidia/ck804/reset.c M src/southbridge/nvidia/mcp55/Kconfig M src/southbridge/nvidia/mcp55/early_ctrl.c M src/southbridge/nvidia/mcp55/reset.c 21 files changed, 12 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29058/1 diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 2d341db..f20cf21 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -17,7 +17,6 @@ select HAVE_ROMSTAGE_CONSOLE_SPINLOCK select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 3e9f3f3..55bd5c3 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -9,7 +9,6 @@ select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_WINBOND_W83627THG select PARALLEL_CPU_INIT - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 531ba4f..8028849 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -17,7 +17,6 @@ select HAVE_ROMSTAGE_CONSOLE_SPINLOCK select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index 5541c93..1436d8c 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -16,7 +16,6 @@ config SOUTHBRIDGE_AMD_AMD8111 bool select IOAPIC - select HAVE_HARD_RESET config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index f3ba8b6..aa323e4 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -52,7 +52,7 @@ enable_cf9_x(sbbusn, sbdn); } -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* reset */ diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index fea8891..41d9880 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -37,7 +37,7 @@ #include "../../../northbridge/amd/amdk8/reset_test.c" -void do_hard_reset(void) +void do_board_reset(void) { pci_devfn_t dev; unsigned bus; diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 353c2a4..6d62e67 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -22,7 +22,6 @@ def_bool y select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET select SMBUS_HAS_AUX_CHANNELS config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index 0878039..f5f7a2c 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -44,7 +44,7 @@ } } -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index f20fa82..d66469a 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -17,7 +17,6 @@ bool select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_SB800 diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index badc4a7..d73b75d 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -218,7 +218,7 @@ pmio_write(0x81, byte); } -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index e3f36f3..bd578b6 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -21,7 +21,7 @@ #include <northbridge/amd/amdk8/reset_test.c> -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig index d72afd8..1ec4f8f 100644 --- a/src/southbridge/broadcom/bcm5785/Kconfig +++ b/src/southbridge/broadcom/bcm5785/Kconfig @@ -1,6 +1,5 @@ config SOUTHBRIDGE_BROADCOM_BCM5785 bool - select HAVE_HARD_RESET config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 766aa1a..c2aa9bc 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -103,7 +103,7 @@ } -void do_hard_reset(void) +void do_board_reset(void) { bcm5785_enable_wdt_port_cf9(); diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 1041aae..ad3ea8f 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -21,7 +21,7 @@ #include "../../../northbridge/amd/amdk8/reset_test.c" -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index dbd24b7..338357e 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -1,6 +1,5 @@ config SOUTHBRIDGE_NVIDIA_CK804 bool - select HAVE_HARD_RESET select HAVE_USBDEBUG select IOAPIC diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index 673c44d..30b68ec 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -310,7 +310,7 @@ return set_ht_link_ck804(4); } -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 99e6ba7..fbc2719 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -355,7 +355,7 @@ return set_ht_link_ck804(4); } -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index bcb6dfc..f828c53 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -21,7 +21,7 @@ #include "../../../northbridge/amd/amdk8/reset_test.c" -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9. */ diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 89aa452..bb1b7df 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -2,7 +2,6 @@ bool select HAVE_USBDEBUG select IOAPIC - select HAVE_HARD_RESET if SOUTHBRIDGE_NVIDIA_MCP55 diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index e91abdf..66ceae2 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -29,7 +29,7 @@ outb(0x06, 0x0cf9); } -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 7be98d7..d6f7f6f 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -24,7 +24,7 @@ #include "../../../northbridge/amd/amdk8/reset_test.c" -void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ -- To view, visit https://review.coreboot.org/29058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c Gerrit-Change-Number: 29058 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: sb/amd/cimx/sb[89]00: Use CF9 reset
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29056 Change subject: sb/amd/cimx/sb[89]00: Use CF9 reset ...................................................................... sb/amd/cimx/sb[89]00: Use CF9 reset Change-Id: I2d277b0845b4e8977b68892c2e5e00d8918e063f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/amd/agesa/family14/state_machine.c M src/southbridge/amd/cimx/sb800/Kconfig M src/southbridge/amd/cimx/sb800/reset.c M src/southbridge/amd/cimx/sb900/Kconfig M src/southbridge/amd/cimx/sb900/reset.c 5 files changed, 10 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29056/1 diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index fd9e3d0..81ce57f 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -18,11 +18,11 @@ #include <arch/io.h> #include <cbmem.h> +#include <cf9_reset.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <halt.h> -#include <reset.h> #include <smp/node.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> @@ -46,7 +46,7 @@ u32 mct_cfg_lo = pci_read_config32(dev, 0x118); if (mct_cfg_lo & (1<<19)) { printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); - hard_reset(); + system_reset(); } } } diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 07232f1..aa5160b 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -19,7 +19,8 @@ select IOAPIC select HAVE_USBDEBUG_OPTIONS select AMD_SB_CIMX - select HAVE_HARD_RESET + select HAVE_CF9_RESET + select HAVE_CF9_RESET_PREPARE if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 40e861c..883ac3e 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -17,14 +17,14 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> -#include <reset.h> +#include <cf9_reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) #define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -static inline void set_bios_reset(void) +void cf9_reset_prepare(void) { u32 nodes; u32 htic; @@ -39,20 +39,3 @@ pci_write_config32(dev, HT_INIT_CONTROL, htic); } } - -void do_hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void do_soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 1fab6a7..be3b16d 100644 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -18,7 +18,8 @@ default n select IOAPIC select AMD_SB_CIMX - select HAVE_HARD_RESET + select HAVE_CF9_RESET + select HAVE_CF9_RESET_PREPARE if SOUTHBRIDGE_AMD_CIMX_SB900 config SATA_CONTROLLER_MODE diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 40e861c..883ac3e 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -17,14 +17,14 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> -#include <reset.h> +#include <cf9_reset.h> #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) #define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -static inline void set_bios_reset(void) +void cf9_reset_prepare(void) { u32 nodes; u32 htic; @@ -39,20 +39,3 @@ pci_write_config32(dev, HT_INIT_CONTROL, htic); } } - -void do_hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} - -//SbReset(); -void do_soft_reset(void) -{ - set_bios_reset(); - /* link reset */ - outb(0x06, 0x0cf9); -} -- To view, visit https://review.coreboot.org/29056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2d277b0845b4e8977b68892c2e5e00d8918e063f Gerrit-Change-Number: 29056 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: sb/amd/*/hudson: Use CF9 reset
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29057 Change subject: sb/amd/*/hudson: Use CF9 reset ...................................................................... sb/amd/*/hudson: Use CF9 reset Change-Id: I80801ba58b9d849ef5e14185510666bd312106c2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/reset.c M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/reset.c 4 files changed, 18 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29057/1 diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 91ebe03..4f769fb 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -15,24 +15,22 @@ config SOUTHBRIDGE_AMD_AGESA_BOLTON bool - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET config SOUTHBRIDGE_AMD_AGESA_HUDSON bool - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET config SOUTHBRIDGE_AMD_AGESA_YANGTZE bool - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE +config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_CF9_RESET + select HAVE_CF9_RESET_PREPARE + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/agesa/hudson/bootblock.c" diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index 315456d..7f61c83 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -17,26 +17,17 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> -#include <reset.h> +#include <cf9_reset.h> #define HT_INIT_CONTROL 0x6c #define HTIC_ColdR_Detect (1<<4) #define HTIC_BIOSR_Detect (1<<5) #define HTIC_INIT_Detect (1<<6) -static void set_bios_reset(void) +void cf9_reset_prepare(void) { u32 htic; htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); } - -void do_hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 5ac876f..9d803be 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -15,27 +15,25 @@ config SOUTHBRIDGE_AMD_PI_BOLTON bool - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET config SOUTHBRIDGE_AMD_PI_AVALON bool - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET config SOUTHBRIDGE_AMD_PI_KERN bool - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET config HUDSON_DISABLE_IMC bool if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN +config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_CF9_RESET + select HAVE_CF9_RESET_PREPARE + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/pi/hudson/bootblock.c" diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c index f80e2d4..7f61c83 100644 --- a/src/southbridge/amd/pi/hudson/reset.c +++ b/src/southbridge/amd/pi/hudson/reset.c @@ -17,27 +17,17 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> -#include <reset.h> +#include <cf9_reset.h> #define HT_INIT_CONTROL 0x6c #define HTIC_ColdR_Detect (1<<4) #define HTIC_BIOSR_Detect (1<<5) #define HTIC_INIT_Detect (1<<6) -static void set_bios_reset(void) +void cf9_reset_prepare(void) { u32 htic; htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); } - - -void do_hard_reset(void) -{ - set_bios_reset(); - /* Try rebooting through port 0xcf9 */ - /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ - outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} -- To view, visit https://review.coreboot.org/29057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I80801ba58b9d849ef5e14185510666bd312106c2 Gerrit-Change-Number: 29057 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: nb/via/vx900: Use CF9 reset
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29055 Change subject: nb/via/vx900: Use CF9 reset ...................................................................... nb/via/vx900: Use CF9 reset Change-Id: I2b68a23cdf244884104d4ed54e19d3ab347c3a3e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/via/vx900/Kconfig M src/northbridge/via/vx900/northbridge.c 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29055/1 diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index b666767..8d95942 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -20,7 +20,7 @@ select DRIVERS_GENERIC_IOAPIC select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS - select HAVE_HARD_RESET + select HAVE_CF9_RESET select NO_RELOCATABLE_RAMSTAGE if NORTHBRIDGE_VIA_VX900 diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 66b2def..5a2ddfb 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -24,7 +24,6 @@ #include <cpu/cpu.h> #include <cbmem.h> #include <lib.h> -#include <reset.h> #include <string.h> #define RAM_4GB (((u64)1) << 32) @@ -43,11 +42,6 @@ * remapping mechanism will overflow, the effects of which are unknown. */ -void do_hard_reset(void) -{ - outb((1 << 2) | (1 << 1), 0xcf9); -} - uint64_t get_uma_memory_base(void) { printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, -- To view, visit https://review.coreboot.org/29055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2b68a23cdf244884104d4ed54e19d3ab347c3a3e Gerrit-Change-Number: 29055 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: arch/x86: Implement common CF9 reset
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29054 Change subject: arch/x86: Implement common CF9 reset ...................................................................... arch/x86: Implement common CF9 reset It's very common across many x86 silicon vendors, so place it in `arch/x86/`. Use the "system reset" as board_reset(). Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc A src/arch/x86/cf9_reset.c A src/arch/x86/include/cf9_reset.h 4 files changed, 109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29054/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 46e0c2d..ff26a15 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -315,3 +315,10 @@ bool default n depends on ARCH_X86 + +config HAVE_CF9_RESET + bool + +config HAVE_CF9_RESET_PREPARE + bool + depends on HAVE_CF9_RESET diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7f85b6a..730bc83 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -43,6 +43,12 @@ pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)) pci$(stripped_vgabios_id).rom-type := optionrom +verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +ramstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c +postcar-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c + ############################################################################### # common support for early assembly includes ############################################################################### diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c new file mode 100644 index 0000000..6f903c9 --- /dev/null +++ b/src/arch/x86/cf9_reset.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/cache.h> +#include <cf9_reset.h> +#include <console/console.h> +#include <halt.h> +#include <reset.h> + +void do_system_reset(void) +{ + outb(SYS_RST, RST_CNT); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_full_reset(void) +{ + outb(FULL_RST | SYS_RST, RST_CNT); + outb(FULL_RST | RST_CPU | SYS_RST, RST_CNT); +} + +void system_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + cf9_reset_prepare(); + dcache_clean_all(); + do_system_reset(); + halt(); +} + +void full_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + cf9_reset_prepare(); + dcache_clean_all(); + do_full_reset(); + halt(); +} + +void do_board_reset(void) +{ + system_reset(); +} diff --git a/src/arch/x86/include/cf9_reset.h b/src/arch/x86/include/cf9_reset.h new file mode 100644 index 0000000..c0dcc92 --- /dev/null +++ b/src/arch/x86/include/cf9_reset.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef X86_CF9_RESET_H +#define X86_CF9_RESET_H + +/* Reset control port */ +#define RST_CNT 0xcf9 +#define FULL_RST (1 << 3) +#define RST_CPU (1 << 2) +#define SYS_RST (1 << 1) + +/* Implement the bare reset, i.e. write to cf9. */ +void do_system_reset(void); +void do_full_reset(void); + +/* Called by functions below before reset. */ +#if IS_ENABLED(CONFIG_HAVE_CF9_RESET_PREPARE) +void cf9_reset_prepare(void); +#else +static inline void cf9_reset_prepare(void) {} +#endif + +/* Prepare for reset, run do_*_reset(), halt. */ +__noreturn void system_reset(void); +__noreturn void full_reset(void); + +#endif /* X86_CF9_RESET_H */ -- To view, visit https://review.coreboot.org/29054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c Gerrit-Change-Number: 29054 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/amd: Implement common reset API
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29053 Change subject: soc/amd: Implement common reset API ...................................................................... soc/amd: Implement common reset API Add an `amdblocks` internal API and rename soft_reset() => warm_reset() hard_reset() => cold_reset() as these terms are commonly used in the surrounding code. On Stoney Ridge, make board_reset() call cold_reset() to keep current behaviour of common code calling hard_reset(). But add a TODO if this is intended. Note: Stoney Ridge is using CF9 for the actual reset but the configuration for a cold reset doesn't use the usual full reset bit but some other mechanism. Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- A src/soc/amd/common/block/include/amdblocks/reset.h M src/soc/amd/common/block/pi/def_callouts.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/reset.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 56 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29053/1 diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h new file mode 100644 index 0000000..4f149ea --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_RESET_H__ +#define __AMD_RESET_H__ + +#include <console/console.h> +#include <arch/cache.h> +#include <halt.h> + +void do_warm_reset(void); +void do_cold_reset(void); + +static inline __noreturn void warm_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + dcache_clean_all(); + do_warm_reset(); + halt(); +} + +static inline __noreturn void cold_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + dcache_clean_all(); + do_cold_reset(); + halt(); +} + +#endif /* __AMD_RESET_H__ */ diff --git a/src/soc/amd/common/block/pi/def_callouts.c b/src/soc/amd/common/block/pi/def_callouts.c index d136084..27d4b0b 100644 --- a/src/soc/amd/common/block/pi/def_callouts.c +++ b/src/soc/amd/common/block/pi/def_callouts.c @@ -21,7 +21,7 @@ #include <amdblocks/BiosCallOuts.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> -#include <reset.h> +#include <amdblocks/reset.h> #include <soc/southbridge.h> #if ENV_BOOTBLOCK @@ -127,12 +127,12 @@ switch (ResetType) { case WARM_RESET_WHENEVER: case WARM_RESET_IMMEDIATELY: - do_soft_reset(); + warm_reset(); break; case COLD_RESET_WHENEVER: case COLD_RESET_IMMEDIATELY: - do_hard_reset(); + cold_reset(); break; default: diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 1f2331a..4411984 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -39,7 +39,6 @@ select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET select HAVE_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select TSC_SYNC_LFENCE diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 738ec59..34aa576 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -20,6 +20,7 @@ #include <soc/pci_devs.h> #include <device/pci_ops.h> #include <soc/southbridge.h> +#include <amdblocks/reset.h> void set_warm_reset_flag(void) { @@ -45,7 +46,7 @@ pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic); } -void do_hard_reset(void) +void do_cold_reset(void) { clear_bios_reset(); @@ -55,7 +56,7 @@ outb(RST_CMD | SYS_RST, SYS_RESET); } -void do_soft_reset(void) +void do_warm_reset(void) { set_warm_reset_flag(); clear_bios_reset(); @@ -63,3 +64,9 @@ /* Assert reset signals only. */ outb(RST_CMD | SYS_RST, SYS_RESET); } + +void do_board_reset(void) +{ + /* TODO: Would a warm_reset() suffice? */ + do_cold_reset(); +} diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 763ddd7..5dff9fc 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -26,6 +26,7 @@ #include <elog.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/agesawrapper.h> +#include <amdblocks/reset.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> @@ -33,7 +34,6 @@ #include <soc/pci_devs.h> #include <agesa_headers.h> #include <soc/nvs.h> -#include <reset.h> /* * Table of devices that need their AOAC registers enabled and waited @@ -638,7 +638,7 @@ setup_misc(&reboot); if (reboot) - soft_reset(); + warm_reset(); sb_enable_legacy_io(); enable_aoac_devices(); -- To view, visit https://review.coreboot.org/29053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4 Gerrit-Change-Number: 29053 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/mediatek: Convert to `board_reset()`
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29051 Change subject: soc/mediatek: Convert to `board_reset()` ...................................................................... soc/mediatek: Convert to `board_reset()` Note, we select MISSING_BOARD_RESET for MT8183 because it didn't select HAVE_HARD_RESET before. Although, it is implemented? Change-Id: Ic850f2775ada5e6e543ffb92aaa033b9209596f5 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/mediatek/common/wdt.c M src/soc/mediatek/mt8173/Kconfig M src/soc/mediatek/mt8183/Kconfig 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29051/1 diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index c261753..2f70454 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -57,7 +57,10 @@ return wdt_sta; } -void do_hard_reset(void) +/* FIXME: Disabled for MT8183, probably by accident? */ +#if !IS_ENABLED(CONFIG_MISSING_BOARD_RESET) +void do_board_reset(void) { write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); } +#endif diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index de9b932..cf0c8d9 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -12,7 +12,6 @@ select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select GENERIC_GPIO_LIB - select HAVE_HARD_RESET select RTC if SOC_MEDIATEK_MT8173 diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index b58be7f..4832fbf 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -11,6 +11,7 @@ select HAVE_UART_SPECIAL select HAVE_MONOTONIC_TIMER select COMPRESS_BOOTBLOCK + select MISSING_BOARD_RESET if SOC_MEDIATEK_MT8183 -- To view, visit https://review.coreboot.org/29051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic850f2775ada5e6e543ffb92aaa033b9209596f5 Gerrit-Change-Number: 29051 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/samsung/exynos5250: Convert to `board_reset()`
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29052 Change subject: soc/samsung/exynos5250: Convert to `board_reset()` ...................................................................... soc/samsung/exynos5250: Convert to `board_reset()` Change-Id: I2f69d9f01ac5f7e28dd98e704f3280bf62b9ce58 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/samsung/exynos5250/Kconfig M src/soc/samsung/exynos5250/power.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29052/1 diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 40c8065..1c92c71 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -7,7 +7,6 @@ select GENERIC_UDELAY select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE - select HAVE_HARD_RESET bool default n diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index de99a82..8bd6304 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -39,7 +39,7 @@ setbits_le32(&exynos_power->sw_reset, 1); } -void do_hard_reset(void) +void do_board_reset(void) { power_reset(); } -- To view, visit https://review.coreboot.org/29052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2f69d9f01ac5f7e28dd98e704f3280bf62b9ce58 Gerrit-Change-Number: 29052 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/imgtech/pistachio: Convert to `board_reset()`
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29050 Change subject: soc/imgtech/pistachio: Convert to `board_reset()` ...................................................................... soc/imgtech/pistachio: Convert to `board_reset()` Change-Id: If8fc29c46e2cbc69f94ea8b6dc414a93d82ffb28 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/imgtec/pistachio/Kconfig M src/soc/imgtec/pistachio/reset.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29050/1 diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 1ce488c..333216d 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -23,7 +23,6 @@ select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select GENERIC_GPIO_LIB - select HAVE_HARD_RESET select UART_OVERRIDE_REFCLK bool diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c index c0e9105..d5d0a81 100644 --- a/src/soc/imgtec/pistachio/reset.c +++ b/src/soc/imgtec/pistachio/reset.c @@ -20,7 +20,7 @@ #define PISTACHIO_WD_ADDR 0xB8102100 #define PISTACHIO_WD_SW_RST_OFFSET 0x0000 -void do_hard_reset(void) +void do_board_reset(void) { /* Generate system reset */ write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1); -- To view, visit https://review.coreboot.org/29050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If8fc29c46e2cbc69f94ea8b6dc414a93d82ffb28 Gerrit-Change-Number: 29050 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/rockchip/rk3399: Convert to `board_reset()`
by Nico Huber (Code Review) 12 Oct '18

12 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29049 Change subject: soc/rockchip/rk3399: Convert to `board_reset()` ...................................................................... soc/rockchip/rk3399: Convert to `board_reset()` Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/gru/Kconfig M src/mainboard/google/gru/reset.c M src/soc/rockchip/rk3399/sdram.c 3 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29049/1 diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 11bf18c..fee2dd0 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -47,7 +47,6 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_RTC select EC_GOOGLE_CHROMEEC_SPI - select HAVE_HARD_RESET select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/mainboard/google/gru/reset.c b/src/mainboard/google/gru/reset.c index 0311d58..5bf7260 100644 --- a/src/mainboard/google/gru/reset.c +++ b/src/mainboard/google/gru/reset.c @@ -18,7 +18,7 @@ #include "board.h" -void do_hard_reset(void) +void do_board_reset(void) { gpio_output(GPIO_RESET, 1); } diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9734679..2b08413 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -990,7 +990,7 @@ if (stopwatch_expired(&sw)) { printk(BIOS_ERR, "index1 frequency change overtime, reset\n"); - hard_reset(); + board_reset(); } } @@ -1000,7 +1000,7 @@ if (stopwatch_expired(&sw)) { printk(BIOS_ERR, "index1 frequency done overtime, reset\n"); - hard_reset(); + board_reset(); } } @@ -1009,7 +1009,7 @@ clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { printk(BIOS_ERR, "index1 training failed, reset\n"); - hard_reset(); + board_reset(); } } } @@ -1042,7 +1042,7 @@ */ if (pctl_cfg(channel, sdram_params) != 0) { printk(BIOS_ERR, "pctl_cfg fail, reset\n"); - hard_reset(); + board_reset(); } /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ @@ -1052,7 +1052,7 @@ if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { printk(BIOS_ERR, "SDRAM initialization failed, reset\n"); - hard_reset(); + board_reset(); } set_ddrconfig(sdram_params, channel, -- To view, visit https://review.coreboot.org/29049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 Gerrit-Change-Number: 29049 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit October 2018