coreboot-gerrit October 2018

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Change in coreboot[master]: reset: Declare new single-function reset API
by Nico Huber (Code Review) 11 Oct '18

11 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29047 Change subject: reset: Declare new single-function reset API ...................................................................... reset: Declare new single-function reset API board_reset() replaces the existing common reset API. There is no common distinction between reset types across platforms, hence, common code could never decide which one to call. Currently only hard_reset() is used by common code. We'll replace these calls after moving all implementations to the new API. Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/reset.h M src/lib/Kconfig M src/lib/reset.c 3 files changed, 58 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29047/1 diff --git a/src/include/reset.h b/src/include/reset.h index cf9d574..47e71f0 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -1,7 +1,46 @@ #ifndef RESET_H #define RESET_H -/* Generic reset functions. Call from code that wants to trigger a reset. */ +/* + * Generic board reset function. Call from common code that + * wants to trigger a reset. + */ +__noreturn void board_reset(void); +/* + * SoC or board specific implementation of the board reset. + * + * Implementations should perform a warm reset if the following + * criteria can be met: + * + * o For vboot support, the TPM MUST be reset. + * + * o All SoC/chipset blocks SHOULD be reset except for those + * that are intentionally meant to survive reset (e.g. tomb- + * stone registers and that sort of stuff). + * + * o All external SoC pins MUST return to power-on reset values. + * + * o The CPU MUST resume execution from power-on reset vector + * (same as cold boot). + * + * o Other board components (e.g. PCI, SDIO and stuff) SHOULD + * be reset. + * + * o USB SHOULD be power-cycled. + * + * o Board components that are intended to be fully independent + * from SoC (e.g. EC and EC-attached devices, the Cr50 on + * Chromebooks) SHOULD NOT be reset. + * + * Otherwise a cold boot should be initiated. + * + * General recommendations: + * + * o DRAM SHOULD NOT lose power if possible. + * + * o Reset time SHOULD be minimized + */ +void do_board_reset(void); /* Super-hard reset specific to some Intel SoCs. */ __noreturn void global_reset(void); diff --git a/src/lib/Kconfig b/src/lib/Kconfig index eb4c16e..fcad921 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -1,3 +1,6 @@ +config MISSING_BOARD_RESET + bool + config NO_EDID_FILL_FB bool default y if !MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/lib/reset.c b/src/lib/reset.c index d828421..9c47adf 100644 --- a/src/lib/reset.c +++ b/src/lib/reset.c @@ -18,6 +18,21 @@ #include <halt.h> #include <reset.h> +__noreturn void board_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + dcache_clean_all(); + do_board_reset(); + halt(); +} + +#if IS_ENABLED(CONFIG_MISSING_BOARD_RESET) +void do_board_reset(void) +{ + printk(BIOS_CRIT, "No board_reset implementation, hanging...\n"); +} +#endif + __noreturn static void __hard_reset(void) { if (IS_ENABLED(CONFIG_HAVE_HARD_RESET)) do_hard_reset(); -- To view, visit https://review.coreboot.org/29047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128 Gerrit-Change-Number: 29047 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: reset: Convert individual boards to `board_reset()`
by Nico Huber (Code Review) 11 Oct '18

11 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29048 Change subject: reset: Convert individual boards to `board_reset()` ...................................................................... reset: Convert individual boards to `board_reset()` Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/foster/pmic.c M src/mainboard/google/foster/reset.c M src/mainboard/google/gale/Kconfig M src/mainboard/google/gale/reset.c M src/mainboard/google/nyan/pmic.c M src/mainboard/google/nyan/reset.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/pmic.c M src/mainboard/google/nyan_big/reset.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/pmic.c M src/mainboard/google/nyan_blaze/reset.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/purin/Kconfig M src/mainboard/google/purin/reset.c M src/mainboard/google/smaug/pmic.c M src/mainboard/google/smaug/reset.c M src/mainboard/google/storm/Kconfig M src/mainboard/google/storm/reset.c M src/mainboard/google/veyron/Kconfig M src/mainboard/google/veyron/reset.c M src/mainboard/google/veyron_mickey/Kconfig M src/mainboard/google/veyron_mickey/reset.c M src/mainboard/google/veyron_rialto/Kconfig M src/mainboard/google/veyron_rialto/reset.c M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra210/Kconfig 27 files changed, 19 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29048/1 diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index b73983b..8d4f855 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -44,7 +44,7 @@ printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); /* Reset the board on any PMIC write error */ - hard_reset(); + board_reset(); } else { if (delay) udelay(500); diff --git a/src/mainboard/google/foster/reset.c b/src/mainboard/google/foster/reset.c index 1b9e9e9..b30e1ac 100644 --- a/src/mainboard/google/foster/reset.c +++ b/src/mainboard/google/foster/reset.c @@ -18,7 +18,7 @@ #include <gpio.h> #include <reset.h> -void do_hard_reset(void) +void do_board_reset(void) { gpio_output(GPIO(I5), 0); } diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig index 883c9fe..f8def87 100644 --- a/src/mainboard/google/gale/Kconfig +++ b/src/mainboard/google/gale/Kconfig @@ -21,7 +21,6 @@ select BOARD_ROMSIZE_KB_8192 select COMMON_CBFS_SPI_WRAPPER select DRIVERS_I2C_WW_RING - select HAVE_HARD_RESET select MAINBOARD_HAS_CHROMEOS select SPI_FLASH select SPI_FLASH_GIGADEVICE diff --git a/src/mainboard/google/gale/reset.c b/src/mainboard/google/gale/reset.c index 23d83bf..d12fee0 100644 --- a/src/mainboard/google/gale/reset.c +++ b/src/mainboard/google/gale/reset.c @@ -19,7 +19,7 @@ #include <soc/iomap.h> #include <reset.h> -void do_hard_reset(void) +void do_board_reset(void) { /* * At boot time the boot loaders would have set a magic cookie diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c index f115586..d226459 100644 --- a/src/mainboard/google/nyan/pmic.c +++ b/src/mainboard/google/nyan/pmic.c @@ -61,7 +61,7 @@ printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); /* Reset the SoC on any PMIC write error */ - hard_reset(); + board_reset(); } else { if (do_delay) udelay(500); diff --git a/src/mainboard/google/nyan/reset.c b/src/mainboard/google/nyan/reset.c index ee36292..468b0c2 100644 --- a/src/mainboard/google/nyan/reset.c +++ b/src/mainboard/google/nyan/reset.c @@ -13,11 +13,10 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <gpio.h> #include <reset.h> -void do_hard_reset(void) +void do_board_reset(void) { gpio_output(GPIO(I5), 0); } diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 4ec0164..b96917e 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -76,7 +76,7 @@ */ if (power_reset_status() == POWER_RESET_WATCHDOG) { printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); - hard_reset(); + board_reset(); } /* FIXME: this may require coordination with moving timestamps */ diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index 77b6545..948d867 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -61,7 +61,7 @@ printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); /* Reset the SoC on any PMIC write error */ - hard_reset(); + board_reset(); } else { if (do_delay) udelay(500); diff --git a/src/mainboard/google/nyan_big/reset.c b/src/mainboard/google/nyan_big/reset.c index ee36292..468b0c2 100644 --- a/src/mainboard/google/nyan_big/reset.c +++ b/src/mainboard/google/nyan_big/reset.c @@ -13,11 +13,10 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <gpio.h> #include <reset.h> -void do_hard_reset(void) +void do_board_reset(void) { gpio_output(GPIO(I5), 0); } diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 4ec0164..b96917e 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -76,7 +76,7 @@ */ if (power_reset_status() == POWER_RESET_WATCHDOG) { printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); - hard_reset(); + board_reset(); } /* FIXME: this may require coordination with moving timestamps */ diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index 77b6545..948d867 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -61,7 +61,7 @@ printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); /* Reset the SoC on any PMIC write error */ - hard_reset(); + board_reset(); } else { if (do_delay) udelay(500); diff --git a/src/mainboard/google/nyan_blaze/reset.c b/src/mainboard/google/nyan_blaze/reset.c index ee36292..468b0c2 100644 --- a/src/mainboard/google/nyan_blaze/reset.c +++ b/src/mainboard/google/nyan_blaze/reset.c @@ -13,11 +13,10 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <gpio.h> #include <reset.h> -void do_hard_reset(void) +void do_board_reset(void) { gpio_output(GPIO(I5), 0); } diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index f094e34..cc8f90e 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -80,7 +80,7 @@ */ if (power_reset_status() == POWER_RESET_WATCHDOG) { printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n"); - hard_reset(); + board_reset(); } /* FIXME: this may require coordination with moving timestamps */ diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig index f48c33c..4666453 100644 --- a/src/mainboard/google/purin/Kconfig +++ b/src/mainboard/google/purin/Kconfig @@ -19,7 +19,6 @@ def_bool y select BOARD_ROMSIZE_KB_2048 select COMMON_CBFS_SPI_WRAPPER - select HAVE_HARD_RESET select MAINBOARD_HAS_CHROMEOS select SOC_BROADCOM_CYGNUS select SPI_FLASH diff --git a/src/mainboard/google/purin/reset.c b/src/mainboard/google/purin/reset.c index 3667bbf..51a2187 100644 --- a/src/mainboard/google/purin/reset.c +++ b/src/mainboard/google/purin/reset.c @@ -15,6 +15,6 @@ #include <reset.h> -void do_hard_reset(void) +void do_board_reset(void) { } diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 77de277..75075ad 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -47,7 +47,7 @@ printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", __func__, reg, val); /* Reset the board on any PMIC write error */ - hard_reset(); + board_reset(); } else { if (delay) udelay(500); diff --git a/src/mainboard/google/smaug/reset.c b/src/mainboard/google/smaug/reset.c index fc9a0b6..121cf64 100644 --- a/src/mainboard/google/smaug/reset.c +++ b/src/mainboard/google/smaug/reset.c @@ -18,7 +18,7 @@ #include "gpio.h" -void do_hard_reset(void) +void do_board_reset(void) { gpio_output(AP_SYS_RESET_L, 0); } diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index b8fc326..e624074 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -21,7 +21,6 @@ select BOARD_ROMSIZE_KB_8192 select COMMON_CBFS_SPI_WRAPPER select DRIVERS_I2C_WW_RING - select HAVE_HARD_RESET select MAINBOARD_HAS_CHROMEOS select SPI_FLASH select SPI_FLASH_SPANSION diff --git a/src/mainboard/google/storm/reset.c b/src/mainboard/google/storm/reset.c index d8f25274..f598de9 100644 --- a/src/mainboard/google/storm/reset.c +++ b/src/mainboard/google/storm/reset.c @@ -39,7 +39,7 @@ write32(APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE, 1); } -void do_hard_reset(void) +void do_board_reset(void) { wdog_reset(); } diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 6aef4ce..d57c143 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -36,7 +36,6 @@ select SOC_ROCKCHIP_RK3288 select MAINBOARD_HAS_CHROMEOS select BOARD_ROMSIZE_KB_4096 - select HAVE_HARD_RESET select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND diff --git a/src/mainboard/google/veyron/reset.c b/src/mainboard/google/veyron/reset.c index a937aff..512ea77 100644 --- a/src/mainboard/google/veyron/reset.c +++ b/src/mainboard/google/veyron/reset.c @@ -13,13 +13,12 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <gpio.h> #include <reset.h> #include "board.h" -void do_hard_reset(void) +void do_board_reset(void) { gpio_output(GPIO_RESET, 1); } diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index c283f0e..2d51962 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -19,7 +19,6 @@ def_bool y select BOARD_ROMSIZE_KB_4096 select COMMON_CBFS_SPI_WRAPPER - select HAVE_HARD_RESET select MAINBOARD_HAS_CHROMEOS select SOC_ROCKCHIP_RK3288 select SPI_FLASH diff --git a/src/mainboard/google/veyron_mickey/reset.c b/src/mainboard/google/veyron_mickey/reset.c index a937aff..512ea77 100644 --- a/src/mainboard/google/veyron_mickey/reset.c +++ b/src/mainboard/google/veyron_mickey/reset.c @@ -13,13 +13,12 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <gpio.h> #include <reset.h> #include "board.h" -void do_hard_reset(void) +void do_board_reset(void) { gpio_output(GPIO_RESET, 1); } diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index a8971d8..520d8c0 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -19,7 +19,6 @@ def_bool y select BOARD_ROMSIZE_KB_4096 select COMMON_CBFS_SPI_WRAPPER - select HAVE_HARD_RESET select MAINBOARD_HAS_CHROMEOS select SOC_ROCKCHIP_RK3288 select SPI_FLASH diff --git a/src/mainboard/google/veyron_rialto/reset.c b/src/mainboard/google/veyron_rialto/reset.c index a937aff..512ea77 100644 --- a/src/mainboard/google/veyron_rialto/reset.c +++ b/src/mainboard/google/veyron_rialto/reset.c @@ -13,13 +13,12 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <gpio.h> #include <reset.h> #include "board.h" -void do_hard_reset(void) +void do_board_reset(void) { gpio_output(GPIO_RESET, 1); } diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 79638d9..0e83774 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -7,7 +7,6 @@ select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL - select HAVE_HARD_RESET select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select BOOTBLOCK_CONSOLE diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index c7c1cf0..44e4719 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -10,7 +10,6 @@ select GIC select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY - select HAVE_HARD_RESET select HAVE_UART_SPECIAL select ARM64_USE_ARM_TRUSTED_FIRMWARE select GENERIC_GPIO_LIB -- To view, visit https://review.coreboot.org/29048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9 Gerrit-Change-Number: 29048 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/cavium/cn81xx: Drop dead do_soft_reset() implementation
by Nico Huber (Code Review) 11 Oct '18

11 Oct '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29046 Change subject: soc/cavium/cn81xx: Drop dead do_soft_reset() implementation ...................................................................... soc/cavium/cn81xx: Drop dead do_soft_reset() implementation Change-Id: I85f357739220f16497f65df1bb317d9d6eb54d9f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/cavium/cn81xx/Makefile.inc M src/soc/cavium/cn81xx/include/soc/addressmap.h D src/soc/cavium/cn81xx/reset.c 3 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/29046/1 diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc index d212715..ede7d73 100644 --- a/src/soc/cavium/cn81xx/Makefile.inc +++ b/src/soc/cavium/cn81xx/Makefile.inc @@ -25,7 +25,6 @@ bootblock-y += spi.c bootblock-y += uart.c bootblock-y += cpu.c -bootblock-y += reset.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif @@ -40,7 +39,6 @@ verstage-y += spi.c verstage-$(CONFIG_DRIVERS_UART) += uart.c verstage-y += cbmem.c -verstage-y += reset.c ################################################################################ # romstage @@ -53,7 +51,6 @@ romstage-y += uart.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbmem.c -romstage-y += reset.c romstage-y += sdram.c romstage-y += mmu.c @@ -74,7 +71,6 @@ ramstage-y += cpu_secondary.S ramstage-y += ecam0.c ramstage-y += cbmem.c -ramstage-y += reset.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h index f188961..f698306 100644 --- a/src/soc/cavium/cn81xx/include/soc/addressmap.h +++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h @@ -62,7 +62,6 @@ /* RST */ #define RST_PF_BAR0 (0x87E006000000ULL + 0x1600) -#define RST_SOFT_RESET (RST_PF_BAR0 + 0x80ULL) #define RST_PP_AVAILABLE (RST_PF_BAR0 + 0x138ULL) #define RST_PP_RESET (RST_PF_BAR0 + 0x140ULL) #define RST_PP_PENDING (RST_PF_BAR0 + 0x148ULL) diff --git a/src/soc/cavium/cn81xx/reset.c b/src/soc/cavium/cn81xx/reset.c deleted file mode 100644 index d3be7c9..0000000 --- a/src/soc/cavium/cn81xx/reset.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018-present Facebook, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/addressmap.h> -#include <reset.h> - -void do_soft_reset(void) -{ - write64((void *)RST_SOFT_RESET, 1); -} -- To view, visit https://review.coreboot.org/29046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I85f357739220f16497f65df1bb317d9d6eb54d9f Gerrit-Change-Number: 29046 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: mainboard/google/kahlee: Set PSPP setting to BalanceLow
by Martin Roth (Code Review) 11 Oct '18

11 Oct '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/29028 ) Change subject: mainboard/google/kahlee: Set PSPP setting to BalanceLow ...................................................................... mainboard/google/kahlee: Set PSPP setting to BalanceLow With correct stapm values audio issue is not observed with PsPPBalanceLow (Gen1 speed). BUG=b:117569918 TEST=audio playback multiple times Change-Id: Iaeae52b262b12622a6753432e3fc40bf5f0fd8e0 Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> Reviewed-on: https://review.coreboot.org/29028 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Martin Roth: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index f5cab08..e9cf5c8 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -149,7 +149,7 @@ VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; - InitEarly->GnbConfig.PsppPolicy = PsppBalanceHigh; + InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow; InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4)) -- To view, visit https://review.coreboot.org/29028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iaeae52b262b12622a6753432e3fc40bf5f0fd8e0 Gerrit-Change-Number: 29028 Gerrit-PatchSet: 2 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/kahlee: Set PSPP setting to BalanceLow
by Raul Rangel (Code Review) 11 Oct '18

11 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/29028 ) Change subject: mainboard/google/kahlee: Set PSPP setting to BalanceLow ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaeae52b262b12622a6753432e3fc40bf5f0fd8e0 Gerrit-Change-Number: 29028 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 11 Oct 2018 21:01:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: This patch fixes Klockwork issues due to the possibility of a NULL po...
by Francois Toguo Fotso (Code Review) 11 Oct '18

11 Oct '18

Francois Toguo Fotso has uploaded a new patch set (#2). ( https://review.coreboot.org/29045 ) Change subject: This patch fixes Klockwork issues due to the possibility of a NULL pointer being dereferenced ...................................................................... This patch fixes Klockwork issues due to the possibility of a NULL pointer being dereferenced Found-by: klockwork BUG=None TEST=Boot to OS Change-Id: Ife366fcb9f8932b39f4a227082c1724e25aa83d1 Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M src/arch/x86/acpigen.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29045/2 -- To view, visit https://review.coreboot.org/29045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ife366fcb9f8932b39f4a227082c1724e25aa83d1 Gerrit-Change-Number: 29045 Gerrit-PatchSet: 2 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com>

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Change in coreboot[master]: This patch fixes Klockwork issues due to the possibility of a NULL po...
by Francois Toguo Fotso (Code Review) 11 Oct '18

11 Oct '18

Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/29045 Change subject: This patch fixes Klockwork issues due to the possibility of a NULL pointer being dereferenced ...................................................................... This patch fixes Klockwork issues due to the possibility of a NULL pointer being dereferenced Change-Id: Ife366fcb9f8932b39f4a227082c1724e25aa83d1 Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M src/arch/x86/acpigen.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29045/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index de3d39e..3945670 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -286,6 +286,13 @@ int dotcount = 0, i; int dotpos = 0; + /* If we have an incoming NULL namepath Then we need to put a null + name (0x00). */ + if (namepath == NULL) { + acpigen_emit_byte(ZERO_OP); + return; + } + /* We can start with a '\'. */ if (namepath[0] == '\\') { acpigen_emit_byte('\\'); -- To view, visit https://review.coreboot.org/29045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife366fcb9f8932b39f4a227082c1724e25aa83d1 Gerrit-Change-Number: 29045 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: Tune DPTF settings for CPU
by Sumeet R Pawnikar (Code Review) 11 Oct '18

11 Oct '18

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/29044 Change subject: mb/google/poppy/variants/nocturne: Tune DPTF settings for CPU ...................................................................... mb/google/poppy/variants/nocturne: Tune DPTF settings for CPU Update CPU passive temperature thershold value from 70C to 80C, to avoid early throttling for spiky workloads. Also, change CPU throttling interval from 1 sec to 5 sec for CPU temperature. Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29044/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl index 61e5d3b..059c7f0 100644 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 70 +#define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_CRITICAL 100 #define DPTF_TSR0_SENSOR_ID 1 @@ -50,7 +50,7 @@ Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR0) */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, -- To view, visit https://review.coreboot.org/29044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686 Gerrit-Change-Number: 29044 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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Change in coreboot[master]: [Lenovo] Remove some unused includes
by Patrick Rudolph (Code Review) 11 Oct '18

11 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29033 ) Change subject: [Lenovo] Remove some unused includes ...................................................................... Patch Set 2: Code-Review+1 Prefix: mb/lenovo -- To view, visit https://review.coreboot.org/29033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I385cac1a75cee13453b831bd75b3ecc7a6d229fa Gerrit-Change-Number: 29033 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 11 Oct 2018 16:45:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [lenovo t430] Set USB always on when calling SMI sleep
by Patrick Rudolph (Code Review) 11 Oct '18

11 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29031 ) Change subject: [lenovo t430] Set USB always on when calling SMI sleep ...................................................................... Patch Set 1: Code-Review+1 Please use the correct prefix mb/lenovo/t430 -- To view, visit https://review.coreboot.org/29031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic4851022267caca267b667b4e3c327838e0a0b66 Gerrit-Change-Number: 29031 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 11 Oct 2018 16:44:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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