Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29047
Change subject: reset: Declare new single-function reset API
......................................................................
reset: Declare new single-function reset API
board_reset() replaces the existing common reset API. There is no common
distinction between reset types across platforms, hence, common code
could never decide which one to call.
Currently only hard_reset() is used by common code. We'll replace these
calls after moving all implementations to the new API.
Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/include/reset.h
M src/lib/Kconfig
M src/lib/reset.c
3 files changed, 58 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29047/1
diff --git a/src/include/reset.h b/src/include/reset.h
index cf9d574..47e71f0 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -1,7 +1,46 @@
#ifndef RESET_H
#define RESET_H
-/* Generic reset functions. Call from code that wants to trigger a reset. */
+/*
+ * Generic board reset function. Call from common code that
+ * wants to trigger a reset.
+ */
+__noreturn void board_reset(void);
+/*
+ * SoC or board specific implementation of the board reset.
+ *
+ * Implementations should perform a warm reset if the following
+ * criteria can be met:
+ *
+ * o For vboot support, the TPM MUST be reset.
+ *
+ * o All SoC/chipset blocks SHOULD be reset except for those
+ * that are intentionally meant to survive reset (e.g. tomb-
+ * stone registers and that sort of stuff).
+ *
+ * o All external SoC pins MUST return to power-on reset values.
+ *
+ * o The CPU MUST resume execution from power-on reset vector
+ * (same as cold boot).
+ *
+ * o Other board components (e.g. PCI, SDIO and stuff) SHOULD
+ * be reset.
+ *
+ * o USB SHOULD be power-cycled.
+ *
+ * o Board components that are intended to be fully independent
+ * from SoC (e.g. EC and EC-attached devices, the Cr50 on
+ * Chromebooks) SHOULD NOT be reset.
+ *
+ * Otherwise a cold boot should be initiated.
+ *
+ * General recommendations:
+ *
+ * o DRAM SHOULD NOT lose power if possible.
+ *
+ * o Reset time SHOULD be minimized
+ */
+void do_board_reset(void);
/* Super-hard reset specific to some Intel SoCs. */
__noreturn void global_reset(void);
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index eb4c16e..fcad921 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -1,3 +1,6 @@
+config MISSING_BOARD_RESET
+ bool
+
config NO_EDID_FILL_FB
bool
default y if !MAINBOARD_DO_NATIVE_VGA_INIT
diff --git a/src/lib/reset.c b/src/lib/reset.c
index d828421..9c47adf 100644
--- a/src/lib/reset.c
+++ b/src/lib/reset.c
@@ -18,6 +18,21 @@
#include <halt.h>
#include <reset.h>
+__noreturn void board_reset(void)
+{
+ printk(BIOS_INFO, "%s() called!\n", __func__);
+ dcache_clean_all();
+ do_board_reset();
+ halt();
+}
+
+#if IS_ENABLED(CONFIG_MISSING_BOARD_RESET)
+void do_board_reset(void)
+{
+ printk(BIOS_CRIT, "No board_reset implementation, hanging...\n");
+}
+#endif
+
__noreturn static void __hard_reset(void) {
if (IS_ENABLED(CONFIG_HAVE_HARD_RESET))
do_hard_reset();
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128
Gerrit-Change-Number: 29047
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29046
Change subject: soc/cavium/cn81xx: Drop dead do_soft_reset() implementation
......................................................................
soc/cavium/cn81xx: Drop dead do_soft_reset() implementation
Change-Id: I85f357739220f16497f65df1bb317d9d6eb54d9f
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/soc/cavium/cn81xx/Makefile.inc
M src/soc/cavium/cn81xx/include/soc/addressmap.h
D src/soc/cavium/cn81xx/reset.c
3 files changed, 0 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/29046/1
diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.inc
index d212715..ede7d73 100644
--- a/src/soc/cavium/cn81xx/Makefile.inc
+++ b/src/soc/cavium/cn81xx/Makefile.inc
@@ -25,7 +25,6 @@
bootblock-y += spi.c
bootblock-y += uart.c
bootblock-y += cpu.c
-bootblock-y += reset.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
@@ -40,7 +39,6 @@
verstage-y += spi.c
verstage-$(CONFIG_DRIVERS_UART) += uart.c
verstage-y += cbmem.c
-verstage-y += reset.c
################################################################################
# romstage
@@ -53,7 +51,6 @@
romstage-y += uart.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += cbmem.c
-romstage-y += reset.c
romstage-y += sdram.c
romstage-y += mmu.c
@@ -74,7 +71,6 @@
ramstage-y += cpu_secondary.S
ramstage-y += ecam0.c
ramstage-y += cbmem.c
-ramstage-y += reset.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c
diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h
index f188961..f698306 100644
--- a/src/soc/cavium/cn81xx/include/soc/addressmap.h
+++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h
@@ -62,7 +62,6 @@
/* RST */
#define RST_PF_BAR0 (0x87E006000000ULL + 0x1600)
-#define RST_SOFT_RESET (RST_PF_BAR0 + 0x80ULL)
#define RST_PP_AVAILABLE (RST_PF_BAR0 + 0x138ULL)
#define RST_PP_RESET (RST_PF_BAR0 + 0x140ULL)
#define RST_PP_PENDING (RST_PF_BAR0 + 0x148ULL)
diff --git a/src/soc/cavium/cn81xx/reset.c b/src/soc/cavium/cn81xx/reset.c
deleted file mode 100644
index d3be7c9..0000000
--- a/src/soc/cavium/cn81xx/reset.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2018-present Facebook, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <soc/addressmap.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
- write64((void *)RST_SOFT_RESET, 1);
-}
--
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Gerrit-Change-Id: I85f357739220f16497f65df1bb317d9d6eb54d9f
Gerrit-Change-Number: 29046
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Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Francois Toguo Fotso has uploaded a new patch set (#2). ( https://review.coreboot.org/29045 )
Change subject: This patch fixes Klockwork issues due to the possibility of a NULL pointer being dereferenced
......................................................................
This patch fixes Klockwork issues due to the possibility of a NULL pointer being dereferenced
Found-by: klockwork
BUG=None
TEST=Boot to OS
Change-Id: Ife366fcb9f8932b39f4a227082c1724e25aa83d1
Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com>
---
M src/arch/x86/acpigen.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29045/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ife366fcb9f8932b39f4a227082c1724e25aa83d1
Gerrit-Change-Number: 29045
Gerrit-PatchSet: 2
Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com>
Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/29045
Change subject: This patch fixes Klockwork issues due to the possibility of a NULL pointer being dereferenced
......................................................................
This patch fixes Klockwork issues due to the possibility of a NULL pointer being dereferenced
Change-Id: Ife366fcb9f8932b39f4a227082c1724e25aa83d1
Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com>
---
M src/arch/x86/acpigen.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29045/1
diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
index de3d39e..3945670 100644
--- a/src/arch/x86/acpigen.c
+++ b/src/arch/x86/acpigen.c
@@ -286,6 +286,13 @@
int dotcount = 0, i;
int dotpos = 0;
+ /* If we have an incoming NULL namepath Then we need to put a null
+ name (0x00). */
+ if (namepath == NULL) {
+ acpigen_emit_byte(ZERO_OP);
+ return;
+ }
+
/* We can start with a '\'. */
if (namepath[0] == '\\') {
acpigen_emit_byte('\\');
--
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Gerrit-Change-Id: Ife366fcb9f8932b39f4a227082c1724e25aa83d1
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Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com>
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/29044
Change subject: mb/google/poppy/variants/nocturne: Tune DPTF settings for CPU
......................................................................
mb/google/poppy/variants/nocturne: Tune DPTF settings for CPU
Update CPU passive temperature thershold value from 70C to 80C,
to avoid early throttling for spiky workloads. Also, change CPU
throttling interval from 1 sec to 5 sec for CPU temperature.
Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29044/1
diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
index 61e5d3b..059c7f0 100644
--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/dptf.asl
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-#define DPTF_CPU_PASSIVE 70
+#define DPTF_CPU_PASSIVE 80
#define DPTF_CPU_CRITICAL 100
#define DPTF_TSR0_SENSOR_ID 1
@@ -50,7 +50,7 @@
Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
- Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR0) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
--
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29033 )
Change subject: [Lenovo] Remove some unused includes
......................................................................
Patch Set 2: Code-Review+1
Prefix: mb/lenovo
--
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Gerrit-Change-Id: I385cac1a75cee13453b831bd75b3ecc7a6d229fa
Gerrit-Change-Number: 29033
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Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 11 Oct 2018 16:45:17 +0000
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29031 )
Change subject: [lenovo t430] Set USB always on when calling SMI sleep
......................................................................
Patch Set 1: Code-Review+1
Please use the correct prefix mb/lenovo/t430
--
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