coreboot-gerrit October 2018

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: Hook up IntelFSP repo"
by Ren Kuo (Code Review) 23 Oct '18

23 Oct '18

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/29237 Change subject: Revert "drivers/intel/fsp2_0: Hook up IntelFSP repo" ...................................................................... Revert "drivers/intel/fsp2_0: Hook up IntelFSP repo" This reverts commit 6539e10c4f209ea4273a78528b26c1f9ff4a3047. Change-Id: Iadde396e5f75fa2f045026be3a0927c1e17f5f7f --- M 3rdparty/blobs M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc A src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h A src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h 23 files changed, 14,262 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/29237/1 -- To view, visit https://review.coreboot.org/29237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iadde396e5f75fa2f045026be3a0927c1e17f5f7f Gerrit-Change-Number: 29237 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: src: Variable name annotation shouldn't contain asterisks
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29235 ) Change subject: src: Variable name annotation shouldn't contain asterisks ...................................................................... Patch Set 5: (19 comments) https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h File src/northbridge/amd/amdht/h3finit.h: https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 229: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 230: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 231: * @param[in,out] u32 FreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 232: * @param[in,out] u32 FeatureCap = modify to change the link's feature capability line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 269: * @param[in,out] u8 ABLinkWidthLimit = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 270: * @param[in,out] u8 BALinkWidthLimit = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 271: * @param[in,out] u32 PCBFreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 302: * @param[in,out] u8 DownstreamLinkWidthLimit = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 303: * @param[in,out] u8 UpstreamLinkWidthLimit = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 304: * @param[in,out] u32 PCBFreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 403: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 404: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 405: * @param[in,out] u16 LinkFrequency = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 434: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 435: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 436: * @param[in,out] u16 LinkFrequency = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3finit.h… PS5, Line 462: * @param[in] u8 pEventData0 = useful data associated with the event. line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3ncmn.c File src/northbridge/amd/amdht/h3ncmn.c: https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3ncmn.c@… PS5, Line 1201: * @param[in] targetNode = The node that shall be the recipient of the traffic line over 80 characters https://review.coreboot.org/#/c/29235/5/src/northbridge/amd/amdht/h3ncmn.c@… PS5, Line 1202: * @param[in] targetLink = The link that shall be the recipient of the traffic line over 80 characters -- To view, visit https://review.coreboot.org/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 5 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 23 Oct 2018 11:53:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src: Variable name annotation shouldn't contain asterisks
by Peter Lemenkov (Code Review) 23 Oct '18

23 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29235 to look at the new patch set (#5). Change subject: src: Variable name annotation shouldn't contain asterisks ...................................................................... src: Variable name annotation shouldn't contain asterisks Whatever code formatting/documenting/analysis tool was used here, these annotations of a variable are wrong. One or two asterisks belongs to the type of the variable, not to the name of the variable. Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/device/pci_device.c M src/drivers/intel/i210/i210.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/mainboard/amd/bettong/OemCustomize.c M src/mainboard/amd/db-ft3b-lc/OemCustomize.c M src/mainboard/amd/gardenia/bootblock/OemCustomize.c M src/mainboard/amd/lamar/OemCustomize.c M src/mainboard/amd/olivehillplus/OemCustomize.c M src/mainboard/bap/ode_e21XX/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c M src/mainboard/pcengines/apu2/OemCustomize.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c M src/mainboard/siemens/mc_tcu3/ptn3460.c M src/northbridge/amd/amdht/h3finit.h M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c M src/soc/intel/fsp_baytrail/i2c.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/lynxpoint/hda_verb.c 19 files changed, 138 insertions(+), 141 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29235/5 -- To view, visit https://review.coreboot.org/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 5 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Variable name annotation shouldn't contain asterisks
by Peter Lemenkov (Code Review) 23 Oct '18

23 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29235 to look at the new patch set (#4). Change subject: src: Variable name annotation shouldn't contain asterisks ...................................................................... src: Variable name annotation shouldn't contain asterisks Whatever code formatting/documenting/analysis tool was used here, these annotations of a variable are wrong. One or two asterisks belongs to the type of the variable, not to the name of the variable. Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/device/pci_device.c M src/drivers/intel/i210/i210.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/mainboard/amd/bettong/OemCustomize.c M src/mainboard/amd/db-ft3b-lc/OemCustomize.c M src/mainboard/amd/gardenia/bootblock/OemCustomize.c M src/mainboard/amd/lamar/OemCustomize.c M src/mainboard/amd/olivehillplus/OemCustomize.c M src/mainboard/bap/ode_e21XX/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c M src/mainboard/pcengines/apu2/OemCustomize.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c M src/mainboard/siemens/mc_tcu3/ptn3460.c M src/northbridge/amd/amdht/h3finit.h M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c M src/soc/intel/fsp_baytrail/i2c.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/lynxpoint/hda_verb.c 19 files changed, 139 insertions(+), 141 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29235/4 -- To view, visit https://review.coreboot.org/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 4 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Variable name annotation shouldn't contain asterisks
by Peter Lemenkov (Code Review) 23 Oct '18

23 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29235 to look at the new patch set (#3). Change subject: src: Variable name annotation shouldn't contain asterisks ...................................................................... src: Variable name annotation shouldn't contain asterisks Whatever code formatting/documenting/analysis tool was used here, this annotation of a variable is wrong. One or two asterisks belongs to the type of the variable, not to the name of the variable. Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/device/pci_device.c M src/drivers/intel/i210/i210.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/mainboard/amd/bettong/OemCustomize.c M src/mainboard/amd/db-ft3b-lc/OemCustomize.c M src/mainboard/amd/gardenia/bootblock/OemCustomize.c M src/mainboard/amd/lamar/OemCustomize.c M src/mainboard/amd/olivehillplus/OemCustomize.c M src/mainboard/bap/ode_e21XX/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c M src/mainboard/pcengines/apu2/OemCustomize.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c M src/mainboard/siemens/mc_tcu3/ptn3460.c M src/northbridge/amd/amdht/h3finit.h M src/northbridge/amd/amdht/h3ncmn.c M src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c M src/soc/intel/fsp_baytrail/i2c.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/lynxpoint/hda_verb.c 19 files changed, 139 insertions(+), 141 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29235/3 -- To view, visit https://review.coreboot.org/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel: Use common RCBA MACROs
by Elyes HAOUAS (Code Review) 23 Oct '18

23 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/29236 ) Change subject: sb/intel: Use common RCBA MACROs ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/29236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Gerrit-Change-Number: 29236 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 23 Oct 2018 10:55:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel: Use common RCBA MACROs
by Peter Lemenkov (Code Review) 23 Oct '18

23 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29236 to look at the new patch set (#2). Change subject: sb/intel: Use common RCBA MACROs ...................................................................... sb/intel: Use common RCBA MACROs This commit is a followup to commit 2e464cf3 with Change-Id I61fb3b01ff15ba2da2ee938addfa630c282c9870. Also it adds RCBA64 macro. Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/rcba.h M src/southbridge/intel/fsp_bd82x6x/pch.h M src/southbridge/intel/fsp_i89xx/pch.h M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 12 files changed, 13 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29236/2 -- To view, visit https://review.coreboot.org/29236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Gerrit-Change-Number: 29236 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel: Use common RCBA MACROs
by Peter Lemenkov (Code Review) 23 Oct '18

23 Oct '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29236 Change subject: sb/intel: Use common RCBA MACROs ...................................................................... sb/intel: Use common RCBA MACROs This commit is a followup to commit 2e464cf3 with Change-Id I61fb3b01ff15ba2da2ee938addfa630c282c9870. Also it adds RCBA64 macro. Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/rcba.h M src/southbridge/intel/fsp_bd82x6x/pch.h M src/southbridge/intel/fsp_i89xx/pch.h M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 12 files changed, 11 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29236/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index e234ca0..112c0b2 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -265,9 +265,6 @@ #define PMBASE 0x40 -/* Root Complex Register Block */ -#define RCBA 0xf0 - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index b6cba8e..ef5e489 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -25,9 +25,14 @@ #ifndef __ACPI__ +/* Root Complex Register Block */ +#define RCBA 0xf0 +#define RCBA_ENABLE 0x01 + #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x))) #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x))) #define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + x))) +#define RCBA64(x) (*((volatile u64 *)(DEFAULT_RCBA + x))) #define RCBA_AND_OR(bits, x, and, or) \ (RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))) diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 1f1c18a..20a4318 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -19,6 +19,7 @@ #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H #include <arch/acpi.h> +#include <southbridge/intel/common/rcba.h> /* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ @@ -47,12 +48,6 @@ #define DEFAULT_PMBASE 0x0400 #ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -#ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 #if defined(__SMM__) && !defined(__ASSEMBLER__) @@ -263,20 +258,6 @@ #define PMBASE 0x40 -/* Root Complex Register Block */ -#define RCBA 0xf0 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h index 3382cbd..2757f7d 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.h +++ b/src/southbridge/intel/fsp_i89xx/pch.h @@ -19,6 +19,7 @@ #define SOUTHBRIDGE_INTEL_I89XX_PCH_H #include <arch/acpi.h> +#include <southbridge/intel/common/rcba.h> /* PCH types */ #define PCH_TYPE_CC 0x23 /* CaveCreek */ @@ -46,12 +47,6 @@ #define DEFAULT_PMBASE 0x0400 #ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -#ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 #if defined(__SMM__) && !defined(__ASSEMBLER__) @@ -180,20 +175,6 @@ #define PMBASE 0x40 -/* Root Complex Register Block */ -#define RCBA 0xf0 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - #define V0CTL 0x0014 /* 32bit */ #define V0STS 0x001a /* 16bit */ diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 0917201..cad5d57 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -19,6 +19,7 @@ #define SOUTHBRIDGE_INTEL_RANGELEY_SOC_H #include <arch/acpi.h> +#include <southbridge/intel/common/rcba.h> /* SOC types */ #define SOC_TYPE_RANGELEY 0x1F @@ -41,11 +42,6 @@ /* Southbridge internal device MEM BARs (Set to match FSP settings) */ #define DEFAULT_IBASE 0xfed08000 #define DEFAULT_PBASE 0xfed03000 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 @@ -176,21 +172,6 @@ #define SMB_SMI_EN (1 << 1) #define HST_EN (1 << 0) -/* Root Complex Register Block */ -#define RCBA 0xf0 -#define RCBA_ENABLE 0x01 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - /* Root Port configuration space hide */ #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d14a809..c0b6637 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -187,9 +187,6 @@ #define PMBASE 0x40 -/* Root Complex Register Block */ -#define RCBA 0xf0 - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 7c4dafa..96c34c1 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -33,7 +33,7 @@ const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); /* Set up RCBA. */ - pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1); /* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index aed1999..456ac8a 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -116,7 +116,6 @@ #define D31F0_CxSTATE_CNF 0xa9 #define D31F0_C4TIMING_CNT 0xaa #define D31F0_GPIO_ROUT 0xb8 -#define D31F0_RCBA 0xf0 /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 115555c..6380e4f 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -48,6 +48,6 @@ enable_spi_prefetch(); /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA, + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); } diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 3c09746..8d98db1 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -119,7 +119,6 @@ #define D31F0_CxSTATE_CNF 0xa9 #define D31F0_C4TIMING_CNT 0xaa #define D31F0_GPIO_ROUT 0xb8 -#define D31F0_RCBA 0xf0 /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 55478b9..216955a 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -235,9 +235,6 @@ #define PMBASE 0x40 -/* Root Complex Register Block */ -#define RCBA 0xf0 - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 489b565..0b673fa 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -18,6 +18,7 @@ #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #include <arch/acpi.h> +#include <southbridge/intel/common/rcba.h> #define CROS_GPIO_DEVICE_NAME "LynxPoint" @@ -83,11 +84,6 @@ #endif #define HPET_ADDR 0xfed00000 -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif #ifndef __ACPI__ @@ -484,20 +480,6 @@ #define PMBASE 0x40 -/* Root Complex Register Block */ -#define RCBA 0xf0 - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) -#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) -#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) -#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) -#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ -- To view, visit https://review.coreboot.org/29236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Gerrit-Change-Number: 29236 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: sb/intel/lynxpoint/hda_verb: Variable name annotation shouldn't conta...
by Peter Lemenkov (Code Review) 23 Oct '18

23 Oct '18

Peter Lemenkov has uploaded a new patch set (#2). ( https://review.coreboot.org/29235 ) Change subject: sb/intel/lynxpoint/hda_verb: Variable name annotation shouldn't contain asterisks ...................................................................... sb/intel/lynxpoint/hda_verb: Variable name annotation shouldn't contain asterisks Whatever code formatting/documenting/analysis tool was used here, this annotation of a variable is wrong. Two asterisks belongs to the type of the variable, not to the name of the variable. Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/southbridge/intel/lynxpoint/hda_verb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29235/2 -- To view, visit https://review.coreboot.org/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

1 0

Change in coreboot[master]: sb/intel/lynxpoint/hda_verb: Variable name here shouldn't contain ast...
by Peter Lemenkov (Code Review) 23 Oct '18

23 Oct '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29235 Change subject: sb/intel/lynxpoint/hda_verb: Variable name here shouldn't contain asterisks ...................................................................... sb/intel/lynxpoint/hda_verb: Variable name here shouldn't contain asterisks Whatever code formatting/documenting/analysis tool was used here, this annotation of a variable is wrong. Two asterisks belongs to the type of the variable, not to the name of the variable. Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/southbridge/intel/lynxpoint/hda_verb.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29235/1 diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index a8a139c..8859628 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -139,7 +139,7 @@ * @param verb_table_bytes: verb table size in bytes * @param verb_table_data: verb table data * @param viddid: vendor/device to search for - * @param **verb: pointer to entry within table + * @param verb: pointer to entry within table * * Returns size of the entry within the verb table, * Returns 0 if the entry is not found -- To view, visit https://review.coreboot.org/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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coreboot-gerrit October 2018