coreboot-gerrit October 2018

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Change in coreboot[master]: {cpu, drivers, sb}/amd: Replace MTRR addresses with macros
by Elyes HAOUAS (Code Review) 23 Oct '18

23 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/29243 ) Change subject: {cpu,drivers,sb}/amd: Replace MTRR addresses with macros ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29243/1/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29243/1/src/southbridge/amd/rs780/gfx.c@770 PS1, Line 770: TOP_MEM > TOP_MEM2 Oops. Thank you -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 23 Oct 2018 17:29:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/common/pi: Correct top of DRAM reporting by AGESA
by Martin Roth (Code Review) 23 Oct '18

23 Oct '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/29229 ) Change subject: soc/amd/common/pi: Correct top of DRAM reporting by AGESA ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd Gerrit-Change-Number: 29229 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 23 Oct 2018 16:27:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/common: Fix function formating
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29230 ) Change subject: soc/amd/common: Fix function formating ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29230/2/src/soc/amd/common/block/pi/heapman… File src/soc/amd/common/block/pi/heapmanager.c: https://review.coreboot.org/#/c/29230/2/src/soc/amd/common/block/pi/heapman… PS2, Line 144: AGESA_STATUS agesa_AllocateBuffer(UINT32 Func, UINTN Data, VOID *ConfigPtr) need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/29230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2120d9d5f663453b6201d1872f29c6dc4abd6191 Gerrit-Change-Number: 29230 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 23 Oct 2018 16:13:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/common: Remove unused variables of write_pci_cfg_irqs()
by Richard Spiegel (Code Review) 23 Oct '18

23 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29244 Change subject: soc/amd/common: Remove unused variables of write_pci_cfg_irqs() ...................................................................... soc/amd/common: Remove unused variables of write_pci_cfg_irqs() Function write_pci_cfg_irqs() has "no function" variables. One variable is set and never used, the other is only used to control a print. Remove them. BUG=b:117950052 TEST=Build grunt. Change-Id: Icd98db3e794e609b112f15979a3a00a2977a0fdb Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/pci/amd_pci_util.c 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29244/1 diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c index 2c48ae7..ecf03d6 100644 --- a/src/soc/amd/common/block/pci/amd_pci_util.c +++ b/src/soc/amd/common/block/pci/amd_pci_util.c @@ -105,9 +105,7 @@ u16 target_pin = 0; u16 int_line = 0; u16 pci_intr_idx = 0; /* Index into PCI_INTR table, 0xC00/0xC01 */ - u8 bus = 0; /* TODO: no longer used, remove it */ u16 devfn = 0; - u8 bridged_device = 0; /* TODO: Remove this */ u32 i = 0; size_t limit; const struct irq_idx_name *idx_name; @@ -142,7 +140,6 @@ if (int_pin < 1 || int_pin > 4) continue; /* Device has invalid INT_PIN - skip */ - bus = target_dev->bus->secondary; devfn = target_dev->path.pci.devfn; /* @@ -218,10 +215,6 @@ */ printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n", int_pin, pin_to_str(int_pin)); - if (bridged_device) - printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", - target_pin, pin_to_str(target_pin)); - printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n" "\tINT_LINE\t: 0x%X (IRQ %d)\n", pci_intr_idx, idx_name[i].name, -- To view, visit https://review.coreboot.org/29244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icd98db3e794e609b112f15979a3a00a2977a0fdb Gerrit-Change-Number: 29244 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: {cpu, drivers, sb}/amd: Replace MTRR addresses with macros
by Martin Roth (Code Review) 23 Oct '18

23 Oct '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/29243 ) Change subject: {cpu,drivers,sb}/amd: Replace MTRR addresses with macros ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29243/1/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29243/1/src/southbridge/amd/rs780/gfx.c@770 PS1, Line 770: TOP_MEM TOP_MEM2 -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 23 Oct 2018 15:42:21 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: {cpu, drivers, sb}/amd: Replace MTRR addresses with macros
by Elyes HAOUAS (Code Review) 23 Oct '18

23 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29243 Change subject: {cpu,drivers,sb}/amd: Replace MTRR addresses with macros ...................................................................... {cpu,drivers,sb}/amd: Replace MTRR addresses with macros Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/s3_mtrr.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/sr5650/sr5650.c 10 files changed, 21 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29243/1 diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index e97a819..9df43e5 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -15,6 +15,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <AGESA.h> #include "amdlib.h" @@ -40,7 +41,7 @@ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00DFFF00; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32) MsrReg; diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 978c25f..a49cefb 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -15,6 +15,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <AGESA.h> #include "amdlib.h" @@ -51,7 +52,7 @@ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; // last address before non-posted range LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32) MsrReg; diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index 7e493f9..a0ae193 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -15,6 +15,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <AGESA.h> #include "amdlib.h" @@ -47,7 +48,7 @@ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index c761d6d..2d74c7b 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -15,6 +15,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <AGESA.h> #include "amdlib.h" @@ -47,7 +48,7 @@ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 11cab62..ae2a2df 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -15,6 +15,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <Porting.h> #include <AGESA.h> @@ -52,7 +53,7 @@ /* last address before non-posted range */ PciData = 0x00FECF00; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index ee8728d..e028b6f 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -15,6 +15,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <Porting.h> #include <AGESA.h> @@ -51,7 +52,7 @@ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 4350572..163066b 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -15,6 +15,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/msr.h> +#include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <Porting.h> #include <AGESA.h> @@ -51,7 +52,7 @@ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index 531ad45..4df7b05 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -61,9 +61,9 @@ /* SYSCFG_MSR */ write_mtrr(&nvram_pos, SYSCFG_MSR); /* TOM */ - write_mtrr(&nvram_pos, 0xC001001A); + write_mtrr(&nvram_pos, TOP_MEM); /* TOM2 */ - write_mtrr(&nvram_pos, 0xC001001D); + write_mtrr(&nvram_pos, TOP_MEM2); *mtrr_store_size = nvram_pos - (u8*) mtrr_store; } diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 43bfb02..d71d646 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -34,6 +34,7 @@ #include <device/pci_ops.h> #include <delay.h> #include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> #include "rs780.h" /* Trust the original resource allocation. Don't do it again. */ @@ -762,11 +763,11 @@ printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); /* The system top memory in 780. */ - sysmem = rdmsr(0xc001001a); + sysmem = rdmsr(TOP_MEM); printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); pci_write_config32(nb_dev, 0x90, sysmem.lo); - sysmem = rdmsr(0xc001001D); + sysmem = rdmsr(TOP_MEM); printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); htiu_write_index(nb_dev, 0x31, sysmem.hi); htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 1e85c48..0f8b265 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -304,11 +304,11 @@ msr_t sysmem; /* The system top memory in SR56X0. */ - sysmem = rdmsr(0xc001001A); + sysmem = rdmsr(TOP_MEM); printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); pci_write_config32(nb_dev, 0x90, sysmem.lo); - sysmem = rdmsr(0xc001001D); + sysmem = rdmsr(TOP_MEM2); printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); htiu_write_index(nb_dev, 0x31, sysmem.hi); htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/amd/stoneyridge: Replace public magic numbers
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29198 ) Change subject: soc/amd/stoneyridge: Replace public magic numbers ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29198/5/src/soc/amd/stoneyridge/northbridge… File src/soc/amd/stoneyridge/northbridge.c: https://review.coreboot.org/#/c/29198/5/src/soc/amd/stoneyridge/northbridge… PS5, Line 405: if (base & (MMIO_WE) | MMIO_RE)) { trailing statements should be on next line -- To view, visit https://review.coreboot.org/29198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I96ac59fd92c4a5e27c3836f77bf6633e9b0c4990 Gerrit-Change-Number: 29198 Gerrit-PatchSet: 5 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 23 Oct 2018 15:10:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/fizz: Enable use of override devicetree
by Furquan Shaikh (Code Review) 23 Oct '18

23 Oct '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29242 Change subject: mb/google/fizz: Enable use of override devicetree ...................................................................... mb/google/fizz: Enable use of override devicetree This change enables override device tree for Fizz to allow variants to provide their own overrides and also moves I2C5 realtek node to fizz/overridetree.cb since it doesn't apply to some variants being added for Fizz. Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/variants/baseboard/devicetree.cb A src/mainboard/google/fizz/variants/fizz/overridetree.cb 3 files changed, 21 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/29242/1 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 6ab94c9..c82f809 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -29,6 +29,10 @@ string default "variants/baseboard/devicetree.cb" +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_EC_EFS diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 281d65c..ff0db37 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -418,15 +418,7 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA device pci 19.0 on end # UART #2 - device pci 19.1 on - chip drivers/i2c/generic - register "hid" = ""10EC5663"" - register "name" = ""RT53"" - register "desc" = ""Realtek RT5663"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" - device i2c 13 on end - end - end # I2C #5 + device pci 19.1 on end # I2C #5 device pci 19.2 off end # I2C #4 device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 diff --git a/src/mainboard/google/fizz/variants/fizz/overridetree.cb b/src/mainboard/google/fizz/variants/fizz/overridetree.cb new file mode 100644 index 0000000..0d3c4fc --- /dev/null +++ b/src/mainboard/google/fizz/variants/fizz/overridetree.cb @@ -0,0 +1,16 @@ +chip soc/intel/skylake + + device domain 0 on + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""10EC5663"" + register "name" = ""RT53"" + register "desc" = ""Realtek RT5663"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" + device i2c 13 on end + end + end # I2C #5 + + end + +end -- To view, visit https://review.coreboot.org/29242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f Gerrit-Change-Number: 29242 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/octopus: Use DIMM_INFO_PART_NUMBER_SIZE for part_num_store
by Furquan Shaikh (Code Review) 23 Oct '18

23 Oct '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29241 Change subject: mb/google/octopus: Use DIMM_INFO_PART_NUMBER_SIZE for part_num_store ...................................................................... mb/google/octopus: Use DIMM_INFO_PART_NUMBER_SIZE for part_num_store This change uses DIMM_INFO_PART_NUMBER_SIZE to decide the size of part_num_store that holds the number of the DRAM part. It ensures that host advertises the supported size to read part number from the EC. BUG=b:115697578 Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/romstage.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29241/1 diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index 9e5734b..43349a0 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -17,6 +17,7 @@ #include <boardid.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> +#include <memory_info.h> #include <soc/meminit.h> #include <soc/romstage.h> @@ -33,7 +34,7 @@ void mainboard_save_dimm_info(void) { - char part_num_store[32]; + char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; const char *part_num = NULL; if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI)) { -- To view, visit https://review.coreboot.org/29241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef Gerrit-Change-Number: 29241 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: Hook up IntelFSP repo"
by Ren Kuo (Code Review) 23 Oct '18

23 Oct '18

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/29237 ) Change subject: Revert "drivers/intel/fsp2_0: Hook up IntelFSP repo" ...................................................................... Patch Set 2: > Patch Set 2: > > uhm, why? We got problem to run cros_workon-nami start coreboot emerge-nami coreboot error !!! Need to revert the CL to let the emerge-nami coreboot pass ! -- To view, visit https://review.coreboot.org/29237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iadde396e5f75fa2f045026be3a0927c1e17f5f7f Gerrit-Change-Number: 29237 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 23 Oct 2018 12:38:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit October 2018