coreboot-gerrit October 2018

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Change in coreboot[master]: amd: Fix non-local header treated as local
by Elyes HAOUAS (Code Review) 24 Oct '18

24 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29103 to look at the new patch set (#3). Change subject: amd: Fix non-local header treated as local ...................................................................... amd: Fix non-local header treated as local Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/drivers/amd/agesa/acpi_tables.c M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/heapmanager.c M src/drivers/amd/agesa/state_machine.c M src/mainboard/amd/bettong/BiosCallOuts.c M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c M src/mainboard/amd/inagua/BiosCallOuts.c M src/mainboard/amd/inagua/buildOpts.c M src/mainboard/amd/lamar/BiosCallOuts.c M src/mainboard/amd/olivehill/BiosCallOuts.c M src/mainboard/amd/olivehill/OemCustomize.c M src/mainboard/amd/olivehill/buildOpts.c M src/mainboard/amd/olivehillplus/BiosCallOuts.c M src/mainboard/amd/parmer/BiosCallOuts.c M src/mainboard/amd/parmer/OemCustomize.c M src/mainboard/amd/parmer/buildOpts.c M src/mainboard/amd/persimmon/BiosCallOuts.c M src/mainboard/amd/persimmon/buildOpts.c M src/mainboard/amd/south_station/BiosCallOuts.c M src/mainboard/amd/south_station/buildOpts.c M src/mainboard/amd/thatcher/BiosCallOuts.c M src/mainboard/amd/thatcher/OemCustomize.c M src/mainboard/amd/thatcher/buildOpts.c M src/mainboard/amd/torpedo/BiosCallOuts.c M src/mainboard/amd/torpedo/buildOpts.c M src/mainboard/amd/union_station/BiosCallOuts.c M src/mainboard/amd/union_station/OemCustomize.c M src/mainboard/amd/union_station/buildOpts.c M src/mainboard/asrock/e350m1/BiosCallOuts.c M src/mainboard/asrock/e350m1/OemCustomize.c M src/mainboard/asrock/e350m1/buildOpts.c M src/mainboard/asrock/imb-a180/BiosCallOuts.c M src/mainboard/asrock/imb-a180/OemCustomize.c M src/mainboard/asrock/imb-a180/buildOpts.c M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/asus/am1i-a/OemCustomize.c M src/mainboard/asus/am1i-a/buildOpts.c M src/mainboard/asus/f2a85-m/BiosCallOuts.c M src/mainboard/asus/f2a85-m/OemCustomize.c M src/mainboard/bap/ode_e20XX/BiosCallOuts.c M src/mainboard/bap/ode_e20XX/OemCustomize.c M src/mainboard/bap/ode_e20XX/buildOpts.c M src/mainboard/bap/ode_e21XX/BiosCallOuts.c M src/mainboard/biostar/a68n_5200/BiosCallOuts.c M src/mainboard/biostar/a68n_5200/OemCustomize.c M src/mainboard/biostar/a68n_5200/buildOpts.c M src/mainboard/biostar/am1ml/BiosCallOuts.c M src/mainboard/biostar/am1ml/OemCustomize.c M src/mainboard/biostar/am1ml/buildOpts.c M src/mainboard/elmex/pcm205400/BiosCallOuts.c M src/mainboard/elmex/pcm205400/buildOpts.c M src/mainboard/gizmosphere/gizmo/BiosCallOuts.c M src/mainboard/gizmosphere/gizmo/OemCustomize.c M src/mainboard/gizmosphere/gizmo/buildOpts.c M src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c M src/mainboard/gizmosphere/gizmo2/OemCustomize.c M src/mainboard/gizmosphere/gizmo2/buildOpts.c M src/mainboard/hp/abm/BiosCallOuts.c M src/mainboard/hp/abm/OemCustomize.c M src/mainboard/hp/abm/buildOpts.c M src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c M src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c M src/mainboard/lenovo/g505s/BiosCallOuts.c M src/mainboard/lenovo/g505s/OemCustomize.c M src/mainboard/lippert/frontrunner-af/BiosCallOuts.c M src/mainboard/lippert/frontrunner-af/OemCustomize.c M src/mainboard/lippert/frontrunner-af/buildOpts.c M src/mainboard/lippert/frontrunner-af/sema.c M src/mainboard/lippert/toucan-af/BiosCallOuts.c M src/mainboard/lippert/toucan-af/OemCustomize.c M src/mainboard/lippert/toucan-af/buildOpts.c M src/mainboard/msi/ms7721/BiosCallOuts.c M src/mainboard/msi/ms7721/OemCustomize.c M src/mainboard/pcengines/apu1/BiosCallOuts.c M src/mainboard/pcengines/apu1/buildOpts.c M src/mainboard/pcengines/apu1/romstage.c M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/mainboard/pcengines/apu2/gpio_ftns.c M src/northbridge/amd/agesa/BiosCallOuts.h M src/northbridge/amd/agesa/family12/dimmSpd.c M src/northbridge/amd/agesa/family12/state_machine.c M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family15tn/state_machine.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/northbridge/amd/agesa/family16kb/state_machine.c M src/northbridge/amd/lx/northbridge.c M src/northbridge/amd/pi/00630F01/dimmSpd.c M src/northbridge/amd/pi/00660F01/dimmSpd.c M src/northbridge/amd/pi/00730F01/dimmSpd.c M src/northbridge/amd/pi/agesawrapper.h M src/northbridge/amd/pi/agesawrapper_call.h M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/resume.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/SBPLATFORM.h M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb800/smbus_spd.c M src/southbridge/amd/cimx/sb900/SbPlatform.h M src/southbridge/amd/cimx/sb900/smbus_spd.c M src/southbridge/amd/pi/hudson/fchec.h M src/southbridge/amd/pi/hudson/smbus_spd.c 109 files changed, 203 insertions(+), 204 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29103/3 -- To view, visit https://review.coreboot.org/29103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Gerrit-Change-Number: 29103 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mediatek/mt8183: Refine structure definitions of DDR driver
by Tristan Hsieh (Code Review) 24 Oct '18

24 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/29251 Change subject: mediatek/mt8183: Refine structure definitions of DDR driver ...................................................................... mediatek/mt8183: Refine structure definitions of DDR driver Remove unused members in emi_mpu_regs and sdram_params. Refine mpu_ctrl_d as an array and fix the misuse. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_register.h M src/soc/mediatek/mt8183/include/soc/emi.h 3 files changed, 10 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29251/1 diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 78e0b28..286c872 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -54,7 +54,7 @@ row_bit = ((((emi_cona >> (24 - chn * 20 + rank)) & 0x01) << 2) + ((emi_cona >> (12 + chn * 16 + rank * 2)) & 0x03)) + 13; - /* data width (bytes) * 8 banks */ + /* Data width (bytes) * 8 banks */ return ((u64)(1 << (row_bit + col_bit))) * ((u64)(4 >> shift_for_16bit) * 8); } @@ -80,7 +80,7 @@ else ch_rank0_size = (ch0_rank0_size * 256 << 20); - /* dual rank enable */ + /* Dual rank enable */ if ((emi_cona & (1 << 17)) != 0) { if (ch0_rank1_size == 0) ch_rank1_size = get_ch_rank_size(CHANNEL_A, RANK_1); @@ -115,7 +115,7 @@ for (int i = 0; i < RANK_MAX; i++) { dram_size += rank_size[i]; - dramc_show("rank%d size:0x%llx\n", i, rank_size[i]); + dramc_show("Rank%d size:0x%llx\n", i, rank_size[i]); } return dram_size; @@ -126,7 +126,7 @@ u8 u4value = 0; /* CONA 17th bit 0: Disable dual rank mode - * 1: Enable dual rank mode */ + 1: Enable dual rank mode */ u4value = ((params->emi_cona_val & (0x1 << 17)) >> 17) ? 0 : 1; clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 12, u4value << 12); } @@ -249,8 +249,8 @@ { emi_esl_setting2(); - setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 1, 0x1 << 4); - setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 7, 0x1 << 4); + setbits_le32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); + setbits_le32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); write32(&emi_regs->bwct0, 0x0a000705); write32(&emi_regs->bwct0_3rd, 0x0); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index ac76e51..c88eaa0 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -936,25 +936,12 @@ struct emi_mpu_regs { uint32_t mpu_ctrl; - uint32_t mpu_dbg; - uint32_t rsvd_2[62]; - uint32_t mpu_sa0; - uint32_t rsvd_3[63]; - uint32_t mpu_ea0; - uint32_t rsvd_4[63]; - uint32_t mpu_apc0; - uint32_t rsvd_5[319]; - uint32_t mpu_ctrl_d0; - uint32_t rsvd_6[63]; - uint32_t rg_mask_d0; + uint32_t rsvd[511]; + uint32_t mpu_ctrl_d[16]; }; -check_member(emi_mpu_regs, mpu_dbg, 0x0004); -check_member(emi_mpu_regs, mpu_sa0, 0x0100); -check_member(emi_mpu_regs, mpu_ea0, 0x0200); -check_member(emi_mpu_regs, mpu_apc0, 0x0300); -check_member(emi_mpu_regs, mpu_ctrl_d0, 0x0800); -check_member(emi_mpu_regs, rg_mask_d0, 0x0900); +check_member(emi_mpu_regs, mpu_ctrl, 0x0000); +check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800); enum { TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT = 12, diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index c3c8e81..22331ae 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -25,8 +25,6 @@ u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; u8 cbt_cs[CHANNEL_MAX][RANK_MAX]; u8 cbt_mr12[CHANNEL_MAX][RANK_MAX]; - s8 clk_delay; - s8 dqs_delay[CHANNEL_MAX]; u32 emi_cona_val; u32 emi_conh_val; u32 emi_conf_val; -- To view, visit https://review.coreboot.org/29251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I95c002058dc5e1cba868334fecf8f42bd3e497e6 Gerrit-Change-Number: 29251 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: amd: Fix non-local header treated as local
by Elyes HAOUAS (Code Review) 24 Oct '18

24 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29103 to look at the new patch set (#2). Change subject: amd: Fix non-local header treated as local ...................................................................... amd: Fix non-local header treated as local Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/drivers/amd/agesa/acpi_tables.c M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/heapmanager.c M src/drivers/amd/agesa/state_machine.c M src/mainboard/amd/bettong/BiosCallOuts.c M src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c M src/mainboard/amd/inagua/BiosCallOuts.c M src/mainboard/amd/inagua/buildOpts.c M src/mainboard/amd/lamar/BiosCallOuts.c M src/mainboard/amd/olivehill/BiosCallOuts.c M src/mainboard/amd/olivehill/OemCustomize.c M src/mainboard/amd/olivehill/buildOpts.c M src/mainboard/amd/olivehillplus/BiosCallOuts.c M src/mainboard/amd/parmer/BiosCallOuts.c M src/mainboard/amd/parmer/OemCustomize.c M src/mainboard/amd/parmer/buildOpts.c M src/mainboard/amd/persimmon/BiosCallOuts.c M src/mainboard/amd/persimmon/buildOpts.c M src/mainboard/amd/south_station/BiosCallOuts.c M src/mainboard/amd/south_station/buildOpts.c M src/mainboard/amd/thatcher/BiosCallOuts.c M src/mainboard/amd/thatcher/OemCustomize.c M src/mainboard/amd/thatcher/buildOpts.c M src/mainboard/amd/torpedo/BiosCallOuts.c M src/mainboard/amd/torpedo/buildOpts.c M src/mainboard/amd/union_station/BiosCallOuts.c M src/mainboard/amd/union_station/OemCustomize.c M src/mainboard/amd/union_station/buildOpts.c M src/mainboard/asrock/e350m1/BiosCallOuts.c M src/mainboard/asrock/e350m1/OemCustomize.c M src/mainboard/asrock/e350m1/buildOpts.c M src/mainboard/asrock/imb-a180/BiosCallOuts.c M src/mainboard/asrock/imb-a180/OemCustomize.c M src/mainboard/asrock/imb-a180/buildOpts.c M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/asus/am1i-a/OemCustomize.c M src/mainboard/asus/am1i-a/buildOpts.c M src/mainboard/asus/f2a85-m/BiosCallOuts.c M src/mainboard/asus/f2a85-m/OemCustomize.c M src/mainboard/bap/ode_e20XX/BiosCallOuts.c M src/mainboard/bap/ode_e20XX/OemCustomize.c M src/mainboard/bap/ode_e20XX/buildOpts.c M src/mainboard/bap/ode_e21XX/BiosCallOuts.c M src/mainboard/biostar/a68n_5200/BiosCallOuts.c M src/mainboard/biostar/a68n_5200/OemCustomize.c M src/mainboard/biostar/a68n_5200/buildOpts.c M src/mainboard/biostar/am1ml/BiosCallOuts.c M src/mainboard/biostar/am1ml/OemCustomize.c M src/mainboard/biostar/am1ml/buildOpts.c M src/mainboard/elmex/pcm205400/BiosCallOuts.c M src/mainboard/elmex/pcm205400/buildOpts.c M src/mainboard/gizmosphere/gizmo/BiosCallOuts.c M src/mainboard/gizmosphere/gizmo/OemCustomize.c M src/mainboard/gizmosphere/gizmo/buildOpts.c M src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c M src/mainboard/gizmosphere/gizmo2/OemCustomize.c M src/mainboard/gizmosphere/gizmo2/buildOpts.c M src/mainboard/hp/abm/BiosCallOuts.c M src/mainboard/hp/abm/OemCustomize.c M src/mainboard/hp/abm/buildOpts.c M src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c M src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c M src/mainboard/lenovo/g505s/BiosCallOuts.c M src/mainboard/lenovo/g505s/OemCustomize.c M src/mainboard/lippert/frontrunner-af/BiosCallOuts.c M src/mainboard/lippert/frontrunner-af/OemCustomize.c M src/mainboard/lippert/frontrunner-af/buildOpts.c M src/mainboard/lippert/frontrunner-af/sema.c M src/mainboard/lippert/toucan-af/BiosCallOuts.c M src/mainboard/lippert/toucan-af/OemCustomize.c M src/mainboard/lippert/toucan-af/buildOpts.c M src/mainboard/msi/ms7721/BiosCallOuts.c M src/mainboard/msi/ms7721/OemCustomize.c M src/mainboard/pcengines/apu1/BiosCallOuts.c M src/mainboard/pcengines/apu1/buildOpts.c M src/mainboard/pcengines/apu1/romstage.c M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/mainboard/pcengines/apu2/gpio_ftns.c M src/northbridge/amd/agesa/BiosCallOuts.h M src/northbridge/amd/agesa/family12/dimmSpd.c M src/northbridge/amd/agesa/family12/state_machine.c M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family15tn/state_machine.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/northbridge/amd/agesa/family16kb/state_machine.c M src/northbridge/amd/lx/northbridge.c M src/northbridge/amd/pi/00630F01/dimmSpd.c M src/northbridge/amd/pi/00660F01/dimmSpd.c M src/northbridge/amd/pi/00730F01/dimmSpd.c M src/northbridge/amd/pi/agesawrapper.h M src/northbridge/amd/pi/agesawrapper_call.h M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/resume.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/SBPLATFORM.h M src/southbridge/amd/cimx/sb800/smbus_spd.c M src/southbridge/amd/cimx/sb900/SbPlatform.h M src/southbridge/amd/cimx/sb900/smbus_spd.c M src/southbridge/amd/pi/hudson/fchec.h M src/southbridge/amd/pi/hudson/smbus_spd.c 108 files changed, 192 insertions(+), 193 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29103/2 -- To view, visit https://review.coreboot.org/29103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Gerrit-Change-Number: 29103 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: {cpu, drivers, nb, sb}/amd: Replace {MSR, MTRR} addresses with macros
by build bot (Jenkins) (Code Review) 24 Oct '18

24 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29243 ) Change subject: {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/#/c/29243/7/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/29243/7/src/northbridge/amd/amdmct/mct_ddr3… PS7, Line 364: data->msr0000020[i] = rdmsr_uint64_t(MTRR_PHYS_BASE(0) | i); line over 80 characters https://review.coreboot.org/#/c/29243/7/src/northbridge/amd/amdmct/mct_ddr3… PS7, Line 703: wrmsr_uint64_t(MTRR_PHYS_BASE(0) | i, data->msr0000020[i]); line over 80 characters -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 24 Oct 2018 09:23:38 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: {cpu, drivers, nb, sb}/amd: Replace {MSR, MTRR} addresses with macros
by Elyes HAOUAS (Code Review) 24 Oct '18

24 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29243 to look at the new patch set (#7). Change subject: {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros ...................................................................... {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/s3_mtrr.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/sr5650/sr5650.c 15 files changed, 47 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29243/7 -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: {cpu, drivers, nb, sb}/amd: Replace {MSR, MTRR} addresses with macros
by build bot (Jenkins) (Code Review) 24 Oct '18

24 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29243 ) Change subject: {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/#/c/29243/6/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/29243/6/src/northbridge/amd/amdmct/mct_ddr3… PS6, Line 364: data->msr0000020[i] = rdmsr_uint64_t(MTRR_PHYS_BASE(0) | i); line over 80 characters https://review.coreboot.org/#/c/29243/6/src/northbridge/amd/amdmct/mct_ddr3… PS6, Line 703: wrmsr_uint64_t(MTRR_PHYS_BASE(0) | i, data->msr0000020[i]); line over 80 characters -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 24 Oct 2018 09:21:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: {cpu, drivers, nb, sb}/amd: Replace {MSR, MTRR} addresses with macros
by Elyes HAOUAS (Code Review) 24 Oct '18

24 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29243 to look at the new patch set (#6). Change subject: {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros ...................................................................... {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/s3_mtrr.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/sr5650/sr5650.c 15 files changed, 47 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29243/6 -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: arch/x86/acpi: Add TPM2 table support
by build bot (Jenkins) (Code Review) 24 Oct '18

24 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29181 ) Change subject: arch/x86/acpi: Add TPM2 table support ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/#/c/29181/7/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/#/c/29181/7/src/arch/x86/acpi.c@326 PS7, Line 326: tpm2->platform_class = 0; // Hard to detect for coreboot. Just set it to 0 line over 80 characters https://review.coreboot.org/#/c/29181/7/src/arch/x86/acpi.c@328 PS7, Line 328: tpm2->start_method = 6; // coreboot only supports the TIS interface driver line over 80 characters -- To view, visit https://review.coreboot.org/29181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5 Gerrit-Change-Number: 29181 Gerrit-PatchSet: 7 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph (1001864) Gerrit-Comment-Date: Wed, 24 Oct 2018 09:12:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic
by Philipp Deppenwiese (Code Review) 24 Oct '18

24 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29060 ) Change subject: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic ...................................................................... vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic - should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag - implement vboot_platform_is_resuming on platforms missing it - add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges [ originally https://review.coreboot.org/c/coreboot/+/28750 ] BUG=b:114018226 TEST=compile coreboot Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Signed-off-by: Joel Kitching <kitching(a)google.com> Reviewed-on: https://review.coreboot.org/29060 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/security/vboot/vboot_logic.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/broadwell/pmutil.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/i82371eb/Kconfig M src/southbridge/intel/i82801jx/Kconfig 9 files changed, 53 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Philipp Deppenwiese: Looks good to me, approved diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index f3a6b41..1b24160 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -309,7 +309,6 @@ * does verification of memory init and thus must ensure it resumes with * the same slot that it booted from. */ if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && - IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && vboot_platform_is_resuming()) ctx.flags |= VB2_CONTEXT_S3_RESUME; diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 51c3ea0..06751f1 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -14,6 +14,7 @@ */ #include <stdint.h> +#include <arch/acpi.h> #include <arch/io.h> #include <cbmem.h> #include <console/console.h> @@ -23,6 +24,7 @@ #include <soc/pci_devs.h> #include <soc/pmc.h> #include <security/vboot/vbnv.h> +#include <security/vboot/vboot_common.h> #if defined(__SIMPLE_DEVICE__) @@ -384,3 +386,11 @@ { return rtc_failure(); } + +int vboot_platform_is_resuming(void) +{ + if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + return 0; + + return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; +} diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 00284d1..85384a61 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <arch/io.h> #include <cbmem.h> #include <console/console.h> @@ -24,6 +25,7 @@ #include <soc/pm.h> #include <stdint.h> #include <security/vboot/vbnv.h> +#include <security/vboot/vboot_common.h> #if defined(__SIMPLE_DEVICE__) @@ -380,3 +382,11 @@ { return rtc_failure(); } + +int vboot_platform_is_resuming(void) +{ + if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + return 0; + + return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; +} diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 3899130..e19025b 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -18,6 +18,7 @@ * and the differences between PCH variants. */ +#include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -29,6 +30,7 @@ #include <soc/pm.h> #include <soc/gpio.h> #include <security/vboot/vbnv.h> +#include <security/vboot/vboot_common.h> /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -473,3 +475,11 @@ { return rtc_failure(); } + +int vboot_platform_is_resuming(void) +{ + if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + return 0; + + return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; +} diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index f8d985e..fb5962e 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -39,6 +39,7 @@ #include <version.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <security/vboot/vboot_common.h> /* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ uint32_t chipset_prev_sleep_state(uint32_t clear) @@ -271,3 +272,8 @@ { return 0; } + +int vboot_platform_is_resuming(void) +{ + return !!romstage_handoff_is_resume(); +} diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 360b63d..2de57d6 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -14,13 +14,16 @@ */ #include <stdint.h> +#include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> #include <arch/early_variables.h> #include <assert.h> +#include <security/vboot/vboot_common.h> #include "pmbase.h" +#include "pmutil.h" /* LPC PM Base Address Register */ #define PMBASE 0x40 @@ -91,3 +94,13 @@ return inb(lpc_get_pmbase() + addr); } + +int vboot_platform_is_resuming(void) +{ + u16 reg16 = read_pmbase16(PM1_STS); + + if (!(reg16 & WAK_STS)) + return 0; + + return acpi_sleep_from_pm1(reg16) == ACPI_S3; +} diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 273e0f8..26134d9 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -17,6 +17,8 @@ #ifndef INTEL_COMMON_PMUTIL_H #define INTEL_COMMON_PMUTIL_H +#include <cpu/x86/smm.h> + #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_3 0xa4 #define D31F0_GPIO_ROUT 0xb8 diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index f22c6e9..6552099 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -1,4 +1,5 @@ config SOUTHBRIDGE_INTEL_I82371EB + select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS bool diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index e56d692..4308e29 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -28,6 +28,7 @@ select SOUTHBRIDGE_INTEL_COMMON_GPIO select INTEL_DESCRIPTOR_MODE_CAPABLE select COMMON_FADT + select ACPI_INTEL_HARDWARE_SLEEP_VALUES if SOUTHBRIDGE_INTEL_I82801JX -- To view, visit https://review.coreboot.org/29060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Gerrit-Change-Number: 29060 Gerrit-PatchSet: 8 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic
by Philipp Deppenwiese (Code Review) 24 Oct '18

24 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29060 ) Change subject: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic ...................................................................... Patch Set 7: Nice work Joel! Thanks for the patience. :) -- To view, visit https://review.coreboot.org/29060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Gerrit-Change-Number: 29060 Gerrit-PatchSet: 7 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 24 Oct 2018 09:07:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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