coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic
by Philipp Deppenwiese (Code Review) 24 Oct '18

24 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29060 ) Change subject: vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/29060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9 Gerrit-Change-Number: 29060 Gerrit-PatchSet: 7 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 24 Oct 2018 09:06:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: tpm2/tlcl_send_startup: should pass on TPM_E_INVALID_POSTINIT
by Philipp Deppenwiese (Code Review) 24 Oct '18

24 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29063 ) Change subject: tpm2/tlcl_send_startup: should pass on TPM_E_INVALID_POSTINIT ...................................................................... tpm2/tlcl_send_startup: should pass on TPM_E_INVALID_POSTINIT Change TSS layer tlcl_send_startup() to expose TPM_RC_INITIALIZE, which gets mapped to TPM_E_INVALID_POSTINIT. The return value is exposed to TSPI layer tpm_setup(), and dealt with as follows: - Regular startup: TPM_E_INVALID_POSTINIT should count as failure. - S3 resume: TPM_E_INVALID_POSTINIT can be assumed to mean that TPM maintains power during S3, and is already initialized. Also, correct an error where |response| could be erroneously accessed when it is set to NULL. BUG=b:114018226 TEST=compile coreboot Change-Id: Ib0c3750386ae04279401c1dc318c5019d39f5ecf Signed-off-by: Joel Kitching <kitching(a)google.com> Reviewed-on: https://review.coreboot.org/29063 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/security/tpm/tss/tcg-2.0/tss.c 1 file changed, 15 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Philipp Deppenwiese: Looks good to me, approved Julius Werner: Looks good to me, approved diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e6ec57c..c67fdfa 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -61,12 +61,24 @@ startup.startup_type = type; response = tpm_process_command(TPM2_Startup, &startup); - if (response && (response->hdr.tpm_code == 0 || - response->hdr.tpm_code == TPM_RC_INITIALIZE)) { - return TPM_SUCCESS; + /* IO error, tpm2_response pointer is empty. */ + if (response == NULL) { + printk(BIOS_ERR, "%s: TPM communication error\n", __func__); + return TPM_E_IOERROR; } + printk(BIOS_INFO, "%s: Startup return code is %x\n", __func__, response->hdr.tpm_code); + + switch (response->hdr.tpm_code) { + case TPM_RC_INITIALIZE: + /* TPM already initialized. */ + return TPM_E_INVALID_POSTINIT; + case TPM2_RC_SUCCESS: + return TPM_SUCCESS; + } + + /* Collapse any other errors into TPM_E_IOERROR. */ return TPM_E_IOERROR; } -- To view, visit https://review.coreboot.org/29063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib0c3750386ae04279401c1dc318c5019d39f5ecf Gerrit-Change-Number: 29063 Gerrit-PatchSet: 6 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: tpm2/tlcl_send_startup: should pass on TPM_E_INVALID_POSTINIT
by Philipp Deppenwiese (Code Review) 24 Oct '18

24 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29063 ) Change subject: tpm2/tlcl_send_startup: should pass on TPM_E_INVALID_POSTINIT ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/29063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib0c3750386ae04279401c1dc318c5019d39f5ecf Gerrit-Change-Number: 29063 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 24 Oct 2018 09:05:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: {cpu, drivers, nb, sb}/amd: Replace {MSR, MTRR} addresses with macros
by build bot (Jenkins) (Code Review) 24 Oct '18

24 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29243 ) Change subject: {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/29243/5/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/29243/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 364: data->msr0000020[i] = rdmsr_uint64_t(MTRR_PHYS_BASE(0) | i); line over 80 characters https://review.coreboot.org/#/c/29243/5/src/northbridge/amd/amdmct/mct_ddr3… PS5, Line 703: wrmsr_uint64_t(MTRR_PHYS_BASE(0) | i, data->msr0000020[i]); line over 80 characters -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 24 Oct 2018 08:33:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: {cpu, drivers, nb, sb}/amd: Replace {MSR, MTRR} addresses with macros
by Elyes HAOUAS (Code Review) 24 Oct '18

24 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29243 to look at the new patch set (#5). Change subject: {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros ...................................................................... {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/s3_mtrr.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/sr5650/sr5650.c 16 files changed, 54 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29243/5 -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/intel/icelake: Do initial SoC commit
by build bot (Jenkins) (Code Review) 24 Oct '18

24 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29162 ) Change subject: soc/intel/icelake: Do initial SoC commit ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/29162/6/src/soc/intel/icelake/include/soc/r… File src/soc/intel/icelake/include/soc/romstage.h: https://review.coreboot.org/#/c/29162/6/src/soc/intel/icelake/include/soc/r… PS6, Line 22: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/29162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5 Gerrit-Change-Number: 29162 Gerrit-PatchSet: 6 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Wed, 24 Oct 2018 08:26:40 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: {cpu, drivers, nb, sb}/amd: Replace {MSR, MTRR} addresses with macros
by Elyes HAOUAS (Code Review) 24 Oct '18

24 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29243 to look at the new patch set (#4). Change subject: {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros ...................................................................... {cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/s3_mtrr.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/sr5650/sr5650.c 15 files changed, 51 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29243/4 -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: {cpu, drivers, sb}/amd: Replace {MSR, MTRR} addresses with macros
by build bot (Jenkins) (Code Review) 24 Oct '18

24 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29243 ) Change subject: {cpu,drivers,sb}/amd: Replace {MSR,MTRR} addresses with macros ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/29243/3/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/29243/3/src/northbridge/amd/amdmct/mct_ddr3… PS3, Line 364: data->msr0000020[i] = rdmsr_uint64_t(MTRR_PHYS_BASE(0) | i); line over 80 characters https://review.coreboot.org/#/c/29243/3/src/northbridge/amd/amdmct/mct_ddr3… PS3, Line 703: wrmsr_uint64_t(MTRR_PHYS_BASE(0) | i, data->msr0000020[i]); line over 80 characters -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 24 Oct 2018 07:43:48 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: {cpu, drivers, sb}/amd: Replace {MSR, MTRR} addresses with macros
by Elyes HAOUAS (Code Review) 24 Oct '18

24 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29243 to look at the new patch set (#3). Change subject: {cpu,drivers,sb}/amd: Replace {MSR,MTRR} addresses with macros ...................................................................... {cpu,drivers,sb}/amd: Replace {MSR,MTRR} addresses with macros Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/drivers/amd/agesa/s3_mtrr.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/sr5650/sr5650.c 15 files changed, 51 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29243/3 -- To view, visit https://review.coreboot.org/29243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b Gerrit-Change-Number: 29243 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: ec/google/chromeec: Add 2 strings to chromeos_log information
by Nicolas Boichat (Code Review) 24 Oct '18

24 Oct '18

Nicolas Boichat has uploaded this change for review. ( https://review.coreboot.org/29250 Change subject: ec/google/chromeec: Add 2 strings to chromeos_log information ...................................................................... ec/google/chromeec: Add 2 strings to chromeos_log information EC added 1 reset flag, and 1 reset cause. BUG=b:109900671 Change-Id: I0db5d0f996ecc8813cab670826b852e8545b6389 Signed-off-by: Nicolas Boichat <drinkcat(a)chromium.org> --- M src/ec/google/chromeec/ec.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29250/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 75d9da1..29f9d38 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -954,6 +954,7 @@ "reset: debug warm reboot", "reset: at AP's request", "reset: during EC initialization", + "reset: AP watchdog", }; static const size_t shutdown_cause_begin = 1 << 15; @@ -1007,7 +1008,8 @@ "usb-resume", "rdd", "rbox", - "security" + "security", + "ap-watchdog", }; struct ec_response_uptime_info cmd_resp; int i, flag, flag_count; -- To view, visit https://review.coreboot.org/29250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0db5d0f996ecc8813cab670826b852e8545b6389 Gerrit-Change-Number: 29250 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolas Boichat <drinkcat(a)chromium.org>

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coreboot-gerrit October 2018