coreboot-gerrit October 2018

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Change in coreboot[master]: soc/amd/stoneyridge: Remove dev_find_slot where possible
by Richard Spiegel (Code Review) 23 Oct '18

23 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29227 Change subject: soc/amd/stoneyridge: Remove dev_find_slot where possible ...................................................................... soc/amd/stoneyridge: Remove dev_find_slot where possible The procedure dev_find_slot has 3 main uses. To find configuration (devicetree), to verify if a particular device is enabled at build \ time, and to get the address for PCI access while in bootblock/romstage. The third use can be hidden by using macros defined in pci_devs.h, making it very clear what PCI device is being accessed. replace the temporary pointers to device used with PCI access with SOC_XXX_DEV where XXX is the device being accessed, and remove the setting of the temporary pointers. BUG=b:117917136 TEST=Build grunt. Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 25 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/29227/1 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 92b2950..3741703 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -55,8 +55,8 @@ static int get_cpu_count(void) { - struct device *nb = dev_find_slot(0, HT_DEVFN); - return (pci_read_config16(nb, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1; + return (pci_read_config16(SOC_NB_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + + 1; } static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 27e1f70..78bed2a 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -98,6 +98,7 @@ /* D18F5 */ #define nb_capabilities2 0x84 #define cmp_cap_mask 0xff + enum { /* SMM handler area. */ SMM_SUBREGION_HANDLER, diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 6833db6..317574b 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -38,32 +38,30 @@ { u8 byte; u32 dword; - struct device *sm_dev; /* * Enable the LPC Controller * SMBus register 0x64 is not defined in public datasheet. */ - sm_dev = dev_find_slot(0, SMBUS_DEVFN); - dword = pci_read_config32(sm_dev, 0x64); + dword = pci_read_config32(SOC_SMBUS_DEV, 0x64); dword |= 1 << 20; - pci_write_config32(sm_dev, 0x64, dword); + pci_write_config32(SOC_SMBUS_DEV, 0x64, dword); /* Initialize isa dma */ isa_dma_init(); /* Enable DMA transaction on the LPC bus */ - byte = pci_read_config8(dev, LPC_PCI_CONTROL); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL); byte |= LEGACY_DMA_EN; - pci_write_config8(dev, LPC_PCI_CONTROL, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte); /* Disable the timeout mechanism on LPC */ - byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; - pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte); /* Disable LPC MSI Capability */ - byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS); /* BIT 1 is not defined in public datasheet. */ byte &= ~(1 << 1); @@ -73,15 +71,15 @@ * interrupt and visit LPC. */ byte &= ~LPC_NOHOG; - pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte); /* * Enable hand-instance of the pulse generator and SPI * controller prefetch of flash. */ - byte = pci_read_config8(dev, LPC_HOST_CONTROL); + byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL); byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; - pci_write_config8(dev, LPC_HOST_CONTROL, byte); + pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte); cmos_check_update_date(); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 4e844af..d17d855 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -47,27 +47,25 @@ u32 io_min, u32 io_max) { u32 tempreg; - struct device *addr_map = dev_find_slot(0, ADDR_DEVFN); /* io range allocation. Limit */ tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0) << (12 - 4)); - pci_write_config32(addr_map, reg + 4, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ - pci_write_config32(addr_map, reg, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg, tempreg); } static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max) { u32 tempreg; - struct device *addr_map = dev_find_slot(0, ADDR_DEVFN); /* io range allocation. Limit */ tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(addr_map, reg + 4, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(addr_map, reg, tempreg); + pci_write_config32(SOC_ADDR_DEV, reg, tempreg); } static void read_resources(struct device *dev) @@ -153,8 +151,7 @@ printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ - pci_write_config32(dev_find_slot(0, ADDR_DEVFN), - D18F1_VGAEN, VGA_ADDR_ENABLE); + pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); } static void set_resources(struct device *dev) @@ -379,17 +376,16 @@ void fam15_finalize(void *chip_info) { - struct device *dev; u32 value; - dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, NB_IOAPIC_INDEX, 0); - pci_write_config32(dev, NB_IOAPIC_DATA, 5); /* TODO: move to dsdt.asl */ + + /* TODO: move IOAPIC code to dsdt.asl */ + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0); + pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5); /* disable No Snoop */ - dev = dev_find_slot(0, HDA0_DEVFN); - value = pci_read_config32(dev, HDA_DEV_CTRL_STATUS); + value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); value &= ~HDA_NO_SNOOP_EN; - pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value); + pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); } static void reserve_domain_res(unsigned int start, unsigned int end) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b188b76..6a94b4c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -892,7 +892,7 @@ uintptr_t xhci_fw; uintptr_t fwaddr; size_t fwsize; - const struct device *sd, *sata, *ehci; + const struct device *sd, *sata; struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs == NULL) @@ -925,7 +925,6 @@ gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE; gnvs->fw03 = fwsize << 16; - ehci = dev_find_slot(0, EHCI1_DEVFN); gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0) & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } -- To view, visit https://review.coreboot.org/29227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11 Gerrit-Change-Number: 29227 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 17: (98 comments) https://review.coreboot.org/#/c/29161/17/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/powernow_acpi.c: https://review.coreboot.org/#/c/29161/17/src/cpu/amd/family_10h-family_15h/… PS17, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters https://review.coreboot.org/#/c/29161/17/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/17/src/cpu/via/nano/nano_init.c@125 PS17, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/db-ft3b-lc/BiosC… File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/db-ft3b-lc/BiosC… PS17, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/lamar/BiosCallOu… File src/mainboard/amd/lamar/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/lamar/BiosCallOu… PS17, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/olivehill/BiosCa… File src/mainboard/amd/olivehill/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/olivehill/BiosCa… PS17, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/olivehillplus/Bi… File src/mainboard/amd/olivehillplus/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/olivehillplus/Bi… PS17, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/parmer/BiosCallO… File src/mainboard/amd/parmer/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/parmer/BiosCallO… PS17, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… PS17, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… PS17, Line 110: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… PS17, Line 116: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… PS17, Line 122: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… PS17, Line 128: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… PS17, Line 150: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… PS17, Line 150: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… PS17, Line 163: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/serengeti_cheeta… PS17, Line 163: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/thatcher/BiosCal… File src/mainboard/amd/thatcher/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/thatcher/BiosCal… PS17, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/amd/torpedo/gpio.c@94 PS17, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/mainboard/bap/ode_e20XX/BiosCa… File src/mainboard/bap/ode_e20XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/bap/ode_e20XX/BiosCa… PS17, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/bap/ode_e21XX/BiosCa… File src/mainboard/bap/ode_e21XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/bap/ode_e21XX/BiosCa… PS17, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/biostar/a68n_5200/Bi… File src/mainboard/biostar/a68n_5200/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/biostar/a68n_5200/Bi… PS17, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/gizmosphere/gizmo/Oe… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/gizmosphere/gizmo/Oe… PS17, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/gizmosphere/gizmo2/B… File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/gizmosphere/gizmo2/B… PS17, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/hp/pavilion_m6_1035d… File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/hp/pavilion_m6_1035d… PS17, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/lenovo/g505s/BiosCal… File src/mainboard/lenovo/g505s/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/lenovo/g505s/BiosCal… PS17, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/lenovo/t60/smihandle… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/lenovo/t60/smihandle… PS17, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/lenovo/z61t/smihandl… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/lenovo/z61t/smihandl… PS17, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/frontrunner-… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/frontrunner-… PS17, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/frontrunner-… PS17, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/frontrunner-… PS17, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/frontrunner-… PS17, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/frontrunner-… PS17, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/frontrunner-… PS17, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/frontrunner-… PS17, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/toucan-af/ma… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/toucan-af/ma… PS17, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/toucan-af/ma… PS17, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/toucan-af/ma… PS17, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/toucan-af/ma… PS17, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/17/src/mainboard/lippert/toucan-af/ma… PS17, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/17/src/mainboard/msi/ms9652_fam10/get… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/msi/ms9652_fam10/get… PS17, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/msi/ms9652_fam10/get… PS17, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/pcengines/apu1/OemCu… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/pcengines/apu1/OemCu… PS17, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/pcengines/apu2/mainb… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/pcengines/apu2/mainb… PS17, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/supermicro/h8dmr_fam… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/supermicro/h8dmr_fam… PS17, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/supermicro/h8dmr_fam… PS17, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/supermicro/h8qme_fam… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/supermicro/h8qme_fam… PS17, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/supermicro/h8qme_fam… PS17, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/tyan/s2912_fam10/get… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/17/src/mainboard/tyan/s2912_fam10/get… PS17, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/mainboard/tyan/s2912_fam10/get… PS17, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/northbridge/amd/agesa/family12… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/17/src/northbridge/amd/agesa/family12… PS17, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/17/src/northbridge/intel/fsp_rangeley… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/17/src/northbridge/intel/fsp_rangeley… PS17, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 73: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 75: (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 78: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 83: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 85: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 87: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 91: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 93: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 96: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 98: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 100: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 104: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 106: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 113: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 118: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 131: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 137: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 143: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 149: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 156: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 167: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 473: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 485: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/ddr_init.c… PS17, Line 1403: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/phy_reg_ac… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/phy_reg_ac… PS17, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/broadcom/cygnus/phy_reg_ac… PS17, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/17/src/soc/intel/baytrail/perf_power.… PS17, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/17/src/soc/intel/fsp_baytrail/fsp/chi… File src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: https://review.coreboot.org/#/c/29161/17/src/soc/intel/fsp_baytrail/fsp/chi… PS17, Line 325: printk(BIOS_WARNING, "Rebooting..\n" ); space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/29161/17/src/soc/intel/fsp_baytrail/northcl… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/17/src/soc/intel/fsp_baytrail/northcl… PS17, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/cimx/sb800/fan… File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/cimx/sb800/fan… PS17, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/cimx/sb800/fan… PS17, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/cimx/sb800/fan… PS17, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/cimx/sb800/fan… PS17, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/cimx/sb800/fan… PS17, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/cimx/sb800/fan… PS17, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/cimx/sb800/fan… PS17, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/cimx/sb800/fan… PS17, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/rs780/gfx.c@250 PS17, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/rs780/gfx.c@250 PS17, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/sb700/sata.c@4… PS17, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/17/src/southbridge/amd/sr5650/pcie.c@… PS17, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/17/src/southbridge/intel/bd82x6x/earl… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29161/17/src/southbridge/intel/bd82x6x/earl… PS17, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/intel/fsp_bd82x6x/… File src/southbridge/intel/fsp_bd82x6x/early_init.c: https://review.coreboot.org/#/c/29161/17/src/southbridge/intel/fsp_bd82x6x/… PS17, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/intel/fsp_i89xx/ea… File src/southbridge/intel/fsp_i89xx/early_init.c: https://review.coreboot.org/#/c/29161/17/src/southbridge/intel/fsp_i89xx/ea… PS17, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/17/src/southbridge/nvidia/ck804/early… File src/southbridge/nvidia/ck804/early_setup.c: https://review.coreboot.org/#/c/29161/17/src/southbridge/nvidia/ck804/early… PS17, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 17 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Oct 2018 20:31:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 16: (99 comments) https://review.coreboot.org/#/c/29161/16/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/powernow_acpi.c: https://review.coreboot.org/#/c/29161/16/src/cpu/amd/family_10h-family_15h/… PS16, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters https://review.coreboot.org/#/c/29161/16/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/16/src/cpu/via/nano/nano_init.c@125 PS16, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/db-ft3b-lc/BiosC… File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/db-ft3b-lc/BiosC… PS16, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/lamar/BiosCallOu… File src/mainboard/amd/lamar/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/lamar/BiosCallOu… PS16, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/olivehill/BiosCa… File src/mainboard/amd/olivehill/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/olivehill/BiosCa… PS16, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/olivehillplus/Bi… File src/mainboard/amd/olivehillplus/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/olivehillplus/Bi… PS16, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/parmer/BiosCallO… File src/mainboard/amd/parmer/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/parmer/BiosCallO… PS16, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… PS16, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… PS16, Line 110: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… PS16, Line 116: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… PS16, Line 122: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… PS16, Line 128: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… PS16, Line 150: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… PS16, Line 150: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… PS16, Line 163: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/serengeti_cheeta… PS16, Line 163: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/thatcher/BiosCal… File src/mainboard/amd/thatcher/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/thatcher/BiosCal… PS16, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/amd/torpedo/gpio.c@94 PS16, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/mainboard/bap/ode_e20XX/BiosCa… File src/mainboard/bap/ode_e20XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/bap/ode_e20XX/BiosCa… PS16, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/bap/ode_e21XX/BiosCa… File src/mainboard/bap/ode_e21XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/bap/ode_e21XX/BiosCa… PS16, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/biostar/a68n_5200/Bi… File src/mainboard/biostar/a68n_5200/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/biostar/a68n_5200/Bi… PS16, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/gizmosphere/gizmo/Oe… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/gizmosphere/gizmo/Oe… PS16, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/gizmosphere/gizmo2/B… File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/gizmosphere/gizmo2/B… PS16, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/hp/pavilion_m6_1035d… File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/hp/pavilion_m6_1035d… PS16, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/lenovo/g505s/BiosCal… File src/mainboard/lenovo/g505s/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/lenovo/g505s/BiosCal… PS16, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/lenovo/t60/smihandle… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/lenovo/t60/smihandle… PS16, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/lenovo/z61t/smihandl… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/lenovo/z61t/smihandl… PS16, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/frontrunner-… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/frontrunner-… PS16, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/frontrunner-… PS16, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/frontrunner-… PS16, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/frontrunner-… PS16, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/frontrunner-… PS16, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/frontrunner-… PS16, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/frontrunner-… PS16, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/toucan-af/ma… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/toucan-af/ma… PS16, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/toucan-af/ma… PS16, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/toucan-af/ma… PS16, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/toucan-af/ma… PS16, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/16/src/mainboard/lippert/toucan-af/ma… PS16, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/16/src/mainboard/msi/ms9652_fam10/get… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/msi/ms9652_fam10/get… PS16, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/msi/ms9652_fam10/get… PS16, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/pcengines/apu1/OemCu… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/pcengines/apu1/OemCu… PS16, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/pcengines/apu2/mainb… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/pcengines/apu2/mainb… PS16, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/supermicro/h8dmr_fam… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/supermicro/h8dmr_fam… PS16, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/supermicro/h8dmr_fam… PS16, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/supermicro/h8qme_fam… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/supermicro/h8qme_fam… PS16, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/supermicro/h8qme_fam… PS16, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/tyan/s2912_fam10/get… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/16/src/mainboard/tyan/s2912_fam10/get… PS16, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/mainboard/tyan/s2912_fam10/get… PS16, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/northbridge/amd/agesa/family12… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/16/src/northbridge/amd/agesa/family12… PS16, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/16/src/northbridge/intel/fsp_rangeley… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/16/src/northbridge/intel/fsp_rangeley… PS16, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 73: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 75: (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 78: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 83: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 85: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 87: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 91: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 93: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 96: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 98: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 100: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 104: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 106: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 113: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 118: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 131: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 137: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 143: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 149: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 156: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 167: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 473: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 485: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 1000: reg32_write(reg,val); space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/ddr_init.c… PS16, Line 1403: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/phy_reg_ac… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/phy_reg_ac… PS16, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/broadcom/cygnus/phy_reg_ac… PS16, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/16/src/soc/intel/baytrail/perf_power.… PS16, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/16/src/soc/intel/fsp_baytrail/fsp/chi… File src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: https://review.coreboot.org/#/c/29161/16/src/soc/intel/fsp_baytrail/fsp/chi… PS16, Line 325: printk(BIOS_WARNING, "Rebooting..\n" ); space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/29161/16/src/soc/intel/fsp_baytrail/northcl… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/16/src/soc/intel/fsp_baytrail/northcl… PS16, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/cimx/sb800/fan… File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/cimx/sb800/fan… PS16, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/cimx/sb800/fan… PS16, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/cimx/sb800/fan… PS16, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/cimx/sb800/fan… PS16, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/cimx/sb800/fan… PS16, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/cimx/sb800/fan… PS16, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/cimx/sb800/fan… PS16, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/cimx/sb800/fan… PS16, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/rs780/gfx.c@250 PS16, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/rs780/gfx.c@250 PS16, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/sb700/sata.c@4… PS16, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/16/src/southbridge/amd/sr5650/pcie.c@… PS16, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/16/src/southbridge/intel/bd82x6x/earl… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29161/16/src/southbridge/intel/bd82x6x/earl… PS16, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/intel/fsp_bd82x6x/… File src/southbridge/intel/fsp_bd82x6x/early_init.c: https://review.coreboot.org/#/c/29161/16/src/southbridge/intel/fsp_bd82x6x/… PS16, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/intel/fsp_i89xx/ea… File src/southbridge/intel/fsp_i89xx/early_init.c: https://review.coreboot.org/#/c/29161/16/src/southbridge/intel/fsp_i89xx/ea… PS16, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/16/src/southbridge/nvidia/ck804/early… File src/southbridge/nvidia/ck804/early_setup.c: https://review.coreboot.org/#/c/29161/16/src/southbridge/nvidia/ck804/early… PS16, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 16 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Oct 2018 20:20:16 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 15: (98 comments) https://review.coreboot.org/#/c/29161/15/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/powernow_acpi.c: https://review.coreboot.org/#/c/29161/15/src/cpu/amd/family_10h-family_15h/… PS15, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters https://review.coreboot.org/#/c/29161/15/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/15/src/cpu/via/nano/nano_init.c@125 PS15, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/db-ft3b-lc/BiosC… File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/db-ft3b-lc/BiosC… PS15, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/lamar/BiosCallOu… File src/mainboard/amd/lamar/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/lamar/BiosCallOu… PS15, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/olivehill/BiosCa… File src/mainboard/amd/olivehill/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/olivehill/BiosCa… PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/olivehillplus/Bi… File src/mainboard/amd/olivehillplus/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/olivehillplus/Bi… PS15, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/parmer/BiosCallO… File src/mainboard/amd/parmer/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/parmer/BiosCallO… PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… PS15, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… PS15, Line 110: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… PS15, Line 116: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… PS15, Line 122: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… PS15, Line 128: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… PS15, Line 150: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… PS15, Line 150: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… PS15, Line 163: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/serengeti_cheeta… PS15, Line 163: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/thatcher/BiosCal… File src/mainboard/amd/thatcher/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/thatcher/BiosCal… PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/amd/torpedo/gpio.c@94 PS15, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/mainboard/bap/ode_e20XX/BiosCa… File src/mainboard/bap/ode_e20XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/bap/ode_e20XX/BiosCa… PS15, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/bap/ode_e21XX/BiosCa… File src/mainboard/bap/ode_e21XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/bap/ode_e21XX/BiosCa… PS15, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/biostar/a68n_5200/Bi… File src/mainboard/biostar/a68n_5200/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/biostar/a68n_5200/Bi… PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/gizmosphere/gizmo/Oe… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/gizmosphere/gizmo/Oe… PS15, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/gizmosphere/gizmo2/B… File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/gizmosphere/gizmo2/B… PS15, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/hp/pavilion_m6_1035d… File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/hp/pavilion_m6_1035d… PS15, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/g505s/BiosCal… File src/mainboard/lenovo/g505s/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/g505s/BiosCal… PS15, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/t60/smihandle… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/t60/smihandle… PS15, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/z61t/smihandl… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/lenovo/z61t/smihandl… PS15, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-… PS15, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-… PS15, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-… PS15, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-… PS15, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-… PS15, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-… PS15, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/frontrunner-… PS15, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/ma… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/ma… PS15, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/ma… PS15, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/ma… PS15, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/ma… PS15, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/15/src/mainboard/lippert/toucan-af/ma… PS15, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/15/src/mainboard/msi/ms9652_fam10/get… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/msi/ms9652_fam10/get… PS15, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/msi/ms9652_fam10/get… PS15, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/pcengines/apu1/OemCu… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/pcengines/apu1/OemCu… PS15, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/pcengines/apu2/mainb… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/pcengines/apu2/mainb… PS15, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8dmr_fam… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8dmr_fam… PS15, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8dmr_fam… PS15, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8qme_fam… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8qme_fam… PS15, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/supermicro/h8qme_fam… PS15, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/tyan/s2912_fam10/get… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/15/src/mainboard/tyan/s2912_fam10/get… PS15, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/mainboard/tyan/s2912_fam10/get… PS15, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/northbridge/amd/agesa/family12… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/15/src/northbridge/amd/agesa/family12… PS15, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/15/src/northbridge/intel/fsp_rangeley… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/15/src/northbridge/intel/fsp_rangeley… PS15, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 73: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 75: (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 78: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 83: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 85: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 87: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 91: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 93: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 96: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 98: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 100: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 104: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 106: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 113: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 118: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 131: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 137: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 143: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 149: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 156: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 167: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 473: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 485: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 1000: reg32_write(reg,val); space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/ddr_init.c… PS15, Line 1403: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/phy_reg_ac… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/phy_reg_ac… PS15, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/broadcom/cygnus/phy_reg_ac… PS15, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/15/src/soc/intel/baytrail/perf_power.… PS15, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/15/src/soc/intel/fsp_baytrail/northcl… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/15/src/soc/intel/fsp_baytrail/northcl… PS15, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan… File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan… PS15, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan… PS15, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan… PS15, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan… PS15, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan… PS15, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan… PS15, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan… PS15, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/cimx/sb800/fan… PS15, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/rs780/gfx.c@250 PS15, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/rs780/gfx.c@250 PS15, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/sb700/sata.c@4… PS15, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/15/src/southbridge/amd/sr5650/pcie.c@… PS15, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/bd82x6x/earl… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/bd82x6x/earl… PS15, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/fsp_bd82x6x/… File src/southbridge/intel/fsp_bd82x6x/early_init.c: https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/fsp_bd82x6x/… PS15, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/fsp_i89xx/ea… File src/southbridge/intel/fsp_i89xx/early_init.c: https://review.coreboot.org/#/c/29161/15/src/southbridge/intel/fsp_i89xx/ea… PS15, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/15/src/southbridge/nvidia/ck804/early… File src/southbridge/nvidia/ck804/early_setup.c: https://review.coreboot.org/#/c/29161/15/src/southbridge/nvidia/ck804/early… PS15, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 15 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Oct 2018 20:17:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 13: (98 comments) https://review.coreboot.org/#/c/29161/13/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/powernow_acpi.c: https://review.coreboot.org/#/c/29161/13/src/cpu/amd/family_10h-family_15h/… PS13, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters https://review.coreboot.org/#/c/29161/13/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/13/src/cpu/via/nano/nano_init.c@125 PS13, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/db-ft3b-lc/BiosC… File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/db-ft3b-lc/BiosC… PS13, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/lamar/BiosCallOu… File src/mainboard/amd/lamar/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/lamar/BiosCallOu… PS13, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/olivehill/BiosCa… File src/mainboard/amd/olivehill/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/olivehill/BiosCa… PS13, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/olivehillplus/Bi… File src/mainboard/amd/olivehillplus/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/olivehillplus/Bi… PS13, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/parmer/BiosCallO… File src/mainboard/amd/parmer/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/parmer/BiosCallO… PS13, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… PS13, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… PS13, Line 110: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… PS13, Line 116: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… PS13, Line 122: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… PS13, Line 128: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… PS13, Line 150: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… PS13, Line 150: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… PS13, Line 163: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/serengeti_cheeta… PS13, Line 163: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/thatcher/BiosCal… File src/mainboard/amd/thatcher/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/thatcher/BiosCal… PS13, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/amd/torpedo/gpio.c@94 PS13, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/mainboard/bap/ode_e20XX/BiosCa… File src/mainboard/bap/ode_e20XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/bap/ode_e20XX/BiosCa… PS13, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/bap/ode_e21XX/BiosCa… File src/mainboard/bap/ode_e21XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/bap/ode_e21XX/BiosCa… PS13, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/biostar/a68n_5200/Bi… File src/mainboard/biostar/a68n_5200/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/biostar/a68n_5200/Bi… PS13, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/gizmosphere/gizmo/Oe… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/gizmosphere/gizmo/Oe… PS13, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/gizmosphere/gizmo2/B… File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/gizmosphere/gizmo2/B… PS13, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/hp/pavilion_m6_1035d… File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/hp/pavilion_m6_1035d… PS13, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/lenovo/g505s/BiosCal… File src/mainboard/lenovo/g505s/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/lenovo/g505s/BiosCal… PS13, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/lenovo/t60/smihandle… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/lenovo/t60/smihandle… PS13, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/lenovo/z61t/smihandl… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/lenovo/z61t/smihandl… PS13, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/frontrunner-… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/frontrunner-… PS13, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/frontrunner-… PS13, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/frontrunner-… PS13, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/frontrunner-… PS13, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/frontrunner-… PS13, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/frontrunner-… PS13, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/frontrunner-… PS13, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/toucan-af/ma… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/toucan-af/ma… PS13, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/toucan-af/ma… PS13, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/toucan-af/ma… PS13, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/toucan-af/ma… PS13, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/13/src/mainboard/lippert/toucan-af/ma… PS13, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/13/src/mainboard/msi/ms9652_fam10/get… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/msi/ms9652_fam10/get… PS13, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/msi/ms9652_fam10/get… PS13, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/pcengines/apu1/OemCu… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/pcengines/apu1/OemCu… PS13, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/pcengines/apu2/mainb… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/pcengines/apu2/mainb… PS13, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/supermicro/h8dmr_fam… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/supermicro/h8dmr_fam… PS13, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/supermicro/h8dmr_fam… PS13, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/supermicro/h8qme_fam… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/supermicro/h8qme_fam… PS13, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/supermicro/h8qme_fam… PS13, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/tyan/s2912_fam10/get… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/13/src/mainboard/tyan/s2912_fam10/get… PS13, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/mainboard/tyan/s2912_fam10/get… PS13, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/northbridge/amd/agesa/family12… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/13/src/northbridge/amd/agesa/family12… PS13, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/13/src/northbridge/intel/fsp_rangeley… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/13/src/northbridge/intel/fsp_rangeley… PS13, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 73: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 75: (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 78: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 83: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 85: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 87: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 91: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 93: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 96: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 98: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 100: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 104: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 106: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 113: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 118: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 131: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 137: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 143: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 149: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 156: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 167: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 473: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 485: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 1000: reg32_write(reg,val); space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/ddr_init.c… PS13, Line 1403: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/phy_reg_ac… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/phy_reg_ac… PS13, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/broadcom/cygnus/phy_reg_ac… PS13, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/13/src/soc/intel/baytrail/perf_power.… PS13, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/13/src/soc/intel/fsp_baytrail/northcl… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/13/src/soc/intel/fsp_baytrail/northcl… PS13, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/cimx/sb800/fan… File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/cimx/sb800/fan… PS13, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/cimx/sb800/fan… PS13, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/cimx/sb800/fan… PS13, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/cimx/sb800/fan… PS13, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/cimx/sb800/fan… PS13, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/cimx/sb800/fan… PS13, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/cimx/sb800/fan… PS13, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/cimx/sb800/fan… PS13, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/rs780/gfx.c@250 PS13, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/rs780/gfx.c@250 PS13, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/sb700/sata.c@4… PS13, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/13/src/southbridge/amd/sr5650/pcie.c@… PS13, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/13/src/southbridge/intel/bd82x6x/earl… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29161/13/src/southbridge/intel/bd82x6x/earl… PS13, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/intel/fsp_bd82x6x/… File src/southbridge/intel/fsp_bd82x6x/early_init.c: https://review.coreboot.org/#/c/29161/13/src/southbridge/intel/fsp_bd82x6x/… PS13, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/intel/fsp_i89xx/ea… File src/southbridge/intel/fsp_i89xx/early_init.c: https://review.coreboot.org/#/c/29161/13/src/southbridge/intel/fsp_i89xx/ea… PS13, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/13/src/southbridge/nvidia/ck804/early… File src/southbridge/nvidia/ck804/early_setup.c: https://review.coreboot.org/#/c/29161/13/src/southbridge/nvidia/ck804/early… PS13, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Oct 2018 20:13:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: intel/fsp: Fix license header for MeminfoHob.h
by Ian Kelling (Code Review) 23 Oct '18

23 Oct '18

Ian Kelling has posted comments on this change. ( https://review.coreboot.org/29224 ) Change subject: intel/fsp: Fix license header for MeminfoHob.h ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/29224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I129c8a465e702d3885d994f4fab352b34d46f177 Gerrit-Change-Number: 29224 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Ian Kelling <ian(a)iankelling.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Oct 2018 18:57:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/fsp: Fix license header for MeminfoHob.h
by Lijian Zhao (Code Review) 23 Oct '18

23 Oct '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29224 Change subject: intel/fsp: Fix license header for MeminfoHob.h ...................................................................... intel/fsp: Fix license header for MeminfoHob.h Current header file included a proprietary license, fix that by using same license shared on public fsp release on fsp. BUG=https://ticket.coreboot.org/issues/177 TEST=N/A Change-Id: I129c8a465e702d3885d994f4fab352b34d46f177 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h 1 file changed, 8 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29224/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h index 99dd815..e605e92 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h @@ -3,34 +3,15 @@ Memory S3 Save data, Memory Info data and Memory Platform data hobs. -@copyright - INTEL CONFIDENTIAL - Copyright 1999 - 2018 Intel Corporation. + @copyright + Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. - - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. - - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. - - This file contains an 'Intel Peripheral Driver' and is uniquely identified as - "Intel Reference Module" and is licensed for Intel CPUs and chipsets under - the terms of your license agreement with Intel or your vendor. This file may - be modified by the user, subject to additional terms of the license agreement. + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. @par Specification Reference: **/ -- To view, visit https://review.coreboot.org/29224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I129c8a465e702d3885d994f4fab352b34d46f177 Gerrit-Change-Number: 29224 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mb/google/octopus: Use a single GPIO for trackpad wake and IRQ
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29189 ) Change subject: mb/google/octopus: Use a single GPIO for trackpad wake and IRQ ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29189/5/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/29189/5/src/mainboard/google/octopus/varian… PS5, Line 199: PAD_CFG_GPI_IRQ_WAKE(GPIO_135, NONE, DEEP, LEVEL, INVERT),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */ line over 80 characters -- To view, visit https://review.coreboot.org/29189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2b704f1be493141629c647b79723b0025b0f7dd6 Gerrit-Change-Number: 29189 Gerrit-PatchSet: 5 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Oct 2018 16:47:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/apollolake: postcar stage potentially needs the reset code, ...
by Patrick Georgi (Code Review) 22 Oct '18

22 Oct '18

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/29223 Change subject: soc/intel/apollolake: postcar stage potentially needs the reset code, too ...................................................................... soc/intel/apollolake: postcar stage potentially needs the reset code, too Also add a test case for that, a config taken from chromiumos with some references to binaries dropped that aren't in our blobs repo (eg audio firmware). Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- A configs/config.google_reef_cros M src/soc/intel/apollolake/Makefile.inc 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29223/1 diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros new file mode 100644 index 0000000..82b9b52 --- /dev/null +++ b/configs/config.google_reef_cros @@ -0,0 +1,15 @@ +CONFIG_USE_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_REEF=y +CONFIG_CHROMEOS=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y +CONFIG_ELOG_GSMI=y +CONFIG_ELOG_BOOT_COUNT=y +CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 +CONFIG_SPI_FLASH_SMM=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_CMOS_POST=y +CONFIG_CMOS_POST_OFFSET=0x70 +CONFIG_CMOS_POST_EXTRA=y +CONFIG_PAYLOAD_NONE=y diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 632cb99..ede565a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -72,6 +72,8 @@ postcar-y += mmap_boot.c postcar-y += spi.c postcar-y += i2c.c +postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c +postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c postcar-$(CONFIG_UART_DEBUG) += uart.c postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S -- To view, visit https://review.coreboot.org/29223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Gerrit-Change-Number: 29223 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: soc/intel: Consolidate FSP CAR setup and teardown code
by PraveenX Hodagatta Pranesh (Code Review) 22 Oct '18

22 Oct '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/29209 Change subject: soc/intel: Consolidate FSP CAR setup and teardown code ...................................................................... soc/intel: Consolidate FSP CAR setup and teardown code This patch adds following changes, - APL, CFL, DENVERTON soc's using same implementation to setup and teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is cosolidated into one file and moved to common code CPU car folder. - exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file and moved to common CPU car. - Tempraminit parameters are passed from soc bootblock.c. - Coffee lake Soc uses FSPT to support Intel Security features like BootGuard verify boot and Measured boot. Add FSP CAR support for CFL by programming tempraminit parameters and add FSP_T_XIP default if FSP_CAR is selected. BUG= None TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup. Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR without errors. Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/bootblock/bootblock.c D src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/bootblock/bootblock.c M src/soc/intel/common/block/cpu/Makefile.inc R src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S R src/soc/intel/common/block/cpu/car/exit_car_fsp.S M src/soc/intel/denverton_ns/Makefile.inc D src/soc/intel/denverton_ns/exit_car_fsp.S 10 files changed, 61 insertions(+), 196 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29209/1 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 632cb99..d2a9a1f 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -18,7 +18,6 @@ bootblock-y += pmutil.c bootblock-y += spi.c bootblock-$(CONFIG_UART_DEBUG) += uart.c -bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c @@ -74,8 +73,6 @@ postcar-y += i2c.c postcar-$(CONFIG_UART_DEBUG) += uart.c -postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S - verstage-y += car.c verstage-y += i2c.c verstage-y += gspi.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index bc5c170..0ec80a0 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2018 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -34,6 +34,25 @@ #include <soc/pm.h> #include <spi-generic.h> #include <timestamp.h> +#include <FsptUpd.h> + +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = 0x545F4450554C5041ULL, /* 'APLUPD_T' */ + .Revision = 1, + .Reserved = {0}, + }, + .FsptCommonUpd = { + .Revision = 0, + .Reserved = {0}, + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, + .CodeRegionBase = + (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, + .Reserved1 = {0}, + }, +}; static const struct pad_config tpm_spi_configs[] = { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S deleted file mode 100644 index 4c4fa71..0000000 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_def.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/cr.h> -#include <cpu/x86/post_code.h> - -#include <../../../arch/x86/walkcbfs.S> - -#define FSP_HDR_OFFSET 0x94 - -.global bootblock_pre_c_entry -bootblock_pre_c_entry: - -.global cache_as_ram -cache_as_ram: - post_code(0x21) - - /* find fsp in cbfs */ - lea fsp_name, %esi - mov $1f, %esp - jmp walkcbfs_asm -1: - cmp $0, %eax - jz .halt_forever - mov CBFS_FILE_OFFSET(%eax), %ebx - bswap %ebx - add %eax, %ebx - add FSP_HDR_OFFSET, %ebx - - /* - * ebx = FSP INFO HEADER - * Calculate entry into FSP - */ - mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */ - add 0x1c(%ebx), %eax /* add the FSP ImageBase */ - - /* - * Pass early init variables on a fake stack (no memory yet) - * as well as the return location - */ - lea CAR_init_stack, %esp - - /* call FSP binary to setup temporary stack */ - jmp *%eax - -/* - * If the TempRamInit API is successful, then when returning, the ECX and - * EDX registers will point to the temporary but writeable memory range - * available to the bootloader where ECX is the start and EDX is the end of - * the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more - * information. - * - * Return Values: - * EAX | Return Status - * ECX | Temporary Memory Start - * EDX | Temporary Memory End - * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call - */ - -CAR_init_done: - - /* Setup bootblock stack */ - mov %edx, %esp - - /* clear CAR_GLOBAL area as it is not shared */ - cld - xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi - sub %edi, %ecx - rep stosl - - /* We can call into C functions now */ - call bootblock_c_entry - - /* Never reached */ - -.halt_forever: - post_code(POST_DEAD_CODE) - hlt - jmp .halt_forever - -CAR_init_params: - .long 0 /* Microcode Location */ - .long 0 /* Microcode Length */ - .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ - .long CONFIG_ROM_SIZE /* Total Firmware Length */ - -CAR_init_stack: - .long CAR_init_done - .long CAR_init_params - -fsp_name: - .ascii "blobs/fspt.bin\x00" diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index abe029a..161db33 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -75,6 +75,7 @@ select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO + select FSP_T_XIP if FSP_CAR config UART_DEBUG bool "Enable UART debug port." diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 0aac186..805ae0e 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation.. + * Copyright (C) 2017-2018 Intel Corporation.. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,6 +19,24 @@ #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/pch.h> +#include <FsptUpd.h> + +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = 0x545F4450554C4643ULL, /* 'CFLUPD_T' */ + .Revision = 1, + .Reserved = {0}, + }, + .FsptCoreUpd = { + .MicrocodeRegionBase = + (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, + .MicrocodeRegionSize = + (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, + .CodeRegionBase = + (UINT32)(0x100000000ULL - CONFIG_ROM_SIZE), + .CodeRegionSize = (UINT32)CONFIG_ROM_SIZE, + }, +}; asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index aa61ffc..5207227 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -1,10 +1,12 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S +bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S +postcar-$(CONFIG_FSP_CAR) += car/exit_car_fsp.S ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) += mp_init.c diff --git a/src/soc/intel/denverton_ns/bootblock/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S similarity index 82% rename from src/soc/intel/denverton_ns/bootblock/cache_as_ram_fsp.S rename to src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index b998c21..5bab9cd 100644 --- a/src/soc/intel/denverton_ns/bootblock/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2017 Intel Corp. + * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,10 +19,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> +#include <../../../../../arch/x86/walkcbfs.S> -#include <../../../arch/x86/walkcbfs.S> - -#define FSP_HDR_OFFSET 0x94 .extern temp_ram_init_params @@ -31,7 +29,7 @@ .global cache_as_ram cache_as_ram: - post_code(0x2f) + post_code(0x21) /* find fsp in cbfs */ lea fsp_name, %esi @@ -43,8 +41,7 @@ mov CBFS_FILE_OFFSET(%eax), %ebx bswap %ebx add %eax, %ebx - - addl $FSP_HDR_OFFSET, %ebx + add $0x94, %ebx /* * save mm2 into ebp, because TempRamInit API doesn't preserve @@ -72,8 +69,7 @@ * If the TempRamInit API is successful, then when returning, the ECX and * EDX registers will point to the temporary but writeable memory range * available to the bootloader where ECX is the start and EDX is the end of - * the range i.e. [ECX,EDX). See Denverton_ns FSP Integration Guide for more - * information. + * the range i.e. [ECX,EDX). See FSP Integration Guide for more information. * * Return Values: * EAX | Return Status @@ -86,22 +82,22 @@ cmp $0, %eax jnz .halt_forever + /* Setup bootblock stack */ + mov %edx, %esp + /* clear CAR_GLOBAL area as it is not shared */ cld - xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi - sub %edi, %ecx + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx shrl $2, %ecx - rep stosl - - /* Setup bootblock stack */ - movl $(_car_stack_end), %esp + rep stosl /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ push %ebp - movd %mm1, %eax - push %eax + movd %mm1, %eax + push %eax /* We can call into C functions now */ call bootblock_c_entry @@ -113,10 +109,9 @@ hlt jmp .halt_forever - .align 4 CAR_init_stack: .long CAR_init_done .long temp_ram_init_params fsp_name: - .ascii "fspt.bin\x00" + .string "fspt.bin\x00" diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S similarity index 68% rename from src/soc/intel/apollolake/exit_car_fsp.S rename to src/soc/intel/common/block/cpu/car/exit_car_fsp.S index fbf2d31..4ac580c 100644 --- a/src/soc/intel/apollolake/exit_car_fsp.S +++ b/src/soc/intel/common/block/cpu/car/exit_car_fsp.S @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2018 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -23,16 +23,8 @@ * the rest of arch/x86/exit_car.S and calls main() itself instead of * returning to _start. In main(), the TempRamExit FSP API is called * to tear down the CAR and set up caching which can be overwritten - * after the API call. More info can be found in the Apollo Lake FSP - * Integration Guide included with the FSP binary. The below - * caching settings are based on an 8MiB Flash Size given as a - * parameter to TempRamInit. - * - * TempRamExit MTRR Settings: - * 0x00000000 - 0x0009FFFF | Write Back - * 0x000C0000 - Top of Low Memory | Write Back - * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect - * 0x100000000 - Top of High Memory | Write Back + * after the API call. More info can be found in the FSP Integration + * Guide included with the FSP binary. */ .text diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 3f6333d..c024c3a 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -23,7 +23,6 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache -bootblock-$(CONFIG_FSP_CAR)+= bootblock/cache_as_ram_fsp.S bootblock-y += bootblock/bootblock.c bootblock-y += spi.c bootblock-y += tsc_freq.c @@ -31,7 +30,6 @@ bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c postcar-y += memmap.c -postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S postcar-y += spi.c postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c diff --git a/src/soc/intel/denverton_ns/exit_car_fsp.S b/src/soc/intel/denverton_ns/exit_car_fsp.S deleted file mode 100644 index 83d5a33..0000000 --- a/src/soc/intel/denverton_ns/exit_car_fsp.S +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016-2017 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cr.h> -//#include <soc/cpu.h> - -/* - * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed. - * This version of chipset_teardown_car sets up the stack, then bypasses - * the rest of arch/x86/exit_car.S and calls main() itself instead of - * returning to _start. In main(), the TempRamExit FSP API is called - * to tear down the CAR and set up caching which can be overwritten - * after the API call. More info can be found in the Denverton-NS FSP - * Integration Guide included with the FSP binary. The below - * caching settings are based on an 8MiB Flash Size given as a - * parameter to TempRamInit. - * - * TempRamExit MTRR Settings: - * 0x00000000 - 0x0009FFFF | Write Back - * 0x000C0000 - Top of Low Memory | Write Back - * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect - * 0x100000000 - Top of High Memory | Write Back - */ - -.text -.global chipset_teardown_car -chipset_teardown_car: - - /* Set up new stack. */ - mov post_car_stack_top, %esp - - /* Call C code */ - call main -- To view, visit https://review.coreboot.org/29209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9 Gerrit-Change-Number: 29209 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com>

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coreboot-gerrit October 2018