coreboot-gerrit October 2018

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Change in coreboot[master]: mb/google/poppy: add the smi_events back
by Furquan Shaikh (Code Review) 23 Oct '18

23 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29191 ) Change subject: mb/google/poppy: add the smi_events back ...................................................................... Patch Set 1: Thanks for fixing this Zhuohao! -- To view, visit https://review.coreboot.org/29191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id82311a8ccd109f9c26516f59a45bdf34da98529 Gerrit-Change-Number: 29191 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 23 Oct 2018 00:46:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: sdm845: Port I2C driver
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29104 ) Change subject: sdm845: Port I2C driver ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/#/c/29104/3/src/soc/qualcomm/sdm845/i2c.c File src/soc/qualcomm/sdm845/i2c.c: https://review.coreboot.org/#/c/29104/3/src/soc/qualcomm/sdm845/i2c.c@279 PS3, Line 279: void i2c_init(unsigned qup_i2c_instance) Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29104/3/src/soc/qualcomm/sdm845/i2c.c@440 PS3, Line 440: int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29104/3/src/soc/qualcomm/sdm845/include/soc… File src/soc/qualcomm/sdm845/include/soc/i2c.h: https://review.coreboot.org/#/c/29104/3/src/soc/qualcomm/sdm845/include/soc… PS3, Line 31: unsigned initialized; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/29104/3/src/soc/qualcomm/sdm845/include/soc… PS3, Line 38: void i2c_init(unsigned qup_i2c_instance); Prefer 'unsigned int' to bare use of 'unsigned' -- To view, visit https://review.coreboot.org/29104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Gerrit-Change-Number: 29104 Gerrit-PatchSet: 3 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Oct 2018 22:19:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: HACK: Julius' changes for v17
by Julius Werner (Code Review) 23 Oct '18

23 Oct '18

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/29232 Change subject: HACK: Julius' changes for v17 ...................................................................... HACK: Julius' changes for v17 Change-Id: I0cd7f0deadb001b2492deadb001811713c547649 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/qualcomm/sdm845/Kconfig M src/soc/qualcomm/sdm845/Makefile.inc 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29232/1 diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index ff4b140..249961f 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -6,6 +6,7 @@ select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select GENERIC_GPIO_LIB select GENERIC_UDELAY diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index f4f8e68..5beeda0 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -67,6 +67,8 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include +BL31_MAKEARGS += PLAT=sdm845 + SDM845_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/sdm845 ################################################################################ -- To view, visit https://review.coreboot.org/29232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0cd7f0deadb001b2492deadb001811713c547649 Gerrit-Change-Number: 29232 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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Change in coreboot[master]: mb/google/poppy/var/nocturne: Use CRFP as device name for FP device
by Furquan Shaikh (Code Review) 23 Oct '18

23 Oct '18

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/29231 ) Change subject: mb/google/poppy/var/nocturne: Use CRFP as device name for FP device ...................................................................... mb/google/poppy/var/nocturne: Use CRFP as device name for FP device This change uses CRFP ACPI name for FP device since user space utilities expect this name for triggering different actions. BRANCH=nocturne Change-Id: I63309227c916b43917e529c223cf738fc3baa209 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/29231/2 -- To view, visit https://review.coreboot.org/29231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I63309227c916b43917e529c223cf738fc3baa209 Gerrit-Change-Number: 29231 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/poppy/var/nocturne: Use CRFP as device name for FP device
by Furquan Shaikh (Code Review) 23 Oct '18

23 Oct '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29231 Change subject: mb/google/poppy/var/nocturne: Use CRFP as device name for FP device ...................................................................... mb/google/poppy/var/nocturne: Use CRFP as device name for FP device This change uses CRFP ACPI name for FP device since user space utilities expect this name for triggering different actions. Change-Id: I63309227c916b43917e529c223cf738fc3baa209 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/29231/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 919a073..c798db5 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -420,6 +420,7 @@ end # GSPI #0 device pci 1e.3 on chip drivers/spi/acpi + register "name" = ""CRFP"" register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" -- To view, visit https://review.coreboot.org/29231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I63309227c916b43917e529c223cf738fc3baa209 Gerrit-Change-Number: 29231 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/amd/common: Fix function formating
by build bot (Jenkins) (Code Review) 23 Oct '18

23 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29230 ) Change subject: soc/amd/common: Fix function formating ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29230/1/src/soc/amd/common/block/pi/heapman… File src/soc/amd/common/block/pi/heapmanager.c: https://review.coreboot.org/#/c/29230/1/src/soc/amd/common/block/pi/heapman… PS1, Line 144: AGESA_STATUS agesa_AllocateBuffer(UINT32 Func, UINTN Data, VOID *ConfigPtr) need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/29230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2120d9d5f663453b6201d1872f29c6dc4abd6191 Gerrit-Change-Number: 29230 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Oct 2018 22:04:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/common: Fix function formating
by Richard Spiegel (Code Review) 23 Oct '18

23 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29230 Change subject: soc/amd/common: Fix function formating ...................................................................... soc/amd/common: Fix function formating There are functions within heapmanager.c that have a space between the function name and open parenthesis. Remove these spaces. BUG=b:117950051 TEST=build grunt. Change-Id: I2120d9d5f663453b6201d1872f29c6dc4abd6191 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/pi/heapmanager.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/29230/1 diff --git a/src/soc/amd/common/block/pi/heapmanager.c b/src/soc/amd/common/block/pi/heapmanager.c index e6a0c46..6fd0069 100644 --- a/src/soc/amd/common/block/pi/heapmanager.c +++ b/src/soc/amd/common/block/pi/heapmanager.c @@ -141,7 +141,7 @@ ROMSTAGE_CBMEM_INIT_HOOK(EmptyHeap) -AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_AllocateBuffer(UINT32 Func, UINTN Data, VOID *ConfigPtr) { /* * Size variables explanation: @@ -316,7 +316,7 @@ return AGESA_SUCCESS; } -AGESA_STATUS agesa_DeallocateBuffer (UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_DeallocateBuffer(UINT32 Func, UINTN Data, VOID *ConfigPtr) { UINT8 *BiosHeapBaseAddr; @@ -429,7 +429,7 @@ return AGESA_SUCCESS; } -AGESA_STATUS agesa_LocateBuffer (UINT32 Func, UINTN Data, VOID *ConfigPtr) +AGESA_STATUS agesa_LocateBuffer(UINT32 Func, UINTN Data, VOID *ConfigPtr) { BIOS_BUFFER_NODE *AllocNodePtr; AGESA_BUFFER_PARAMS *AllocParams; -- To view, visit https://review.coreboot.org/29230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2120d9d5f663453b6201d1872f29c6dc4abd6191 Gerrit-Change-Number: 29230 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/common/pi: Correct top of DRAM reporting by AGESA
by Marshall Dawson (Code Review) 23 Oct '18

23 Oct '18

Marshall Dawson has uploaded a new patch set (#2). ( https://review.coreboot.org/29229 ) Change subject: soc/amd/common/pi: Correct top of DRAM reporting by AGESA ...................................................................... soc/amd/common/pi: Correct top of DRAM reporting by AGESA Accurately reflect the intention of the syslimit value returned from AmdInitPost(). Assume FFs for the non-present bits. BUG=b:118178425 TEST=Boot Grunt and verify reported value = TOM2-1. Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/29229/2 -- To view, visit https://review.coreboot.org/29229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd Gerrit-Change-Number: 29229 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Correct top of DRAM reporting by AGESA
by Marshall Dawson (Code Review) 23 Oct '18

23 Oct '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29229 Change subject: soc/amd/stoneyridge: Correct top of DRAM reporting by AGESA ...................................................................... soc/amd/stoneyridge: Correct top of DRAM reporting by AGESA Accurately reflect the intention of the syslimit value returned from AmdInitPost(). Assume FFs for the non-present bits. BUG=b:118178425 TEST=Boot Grunt and verify reported value = TOM2-1. Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/29229/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 49a2c4c..87e0b69 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -164,7 +164,7 @@ break; } - syslimit = (u64)parms->MemConfig.SysLimit * 64 * KiB; + syslimit = (u64)(parms->MemConfig.SysLimit + 1) * 64 * KiB - 1; bottomio = (u64)parms->MemConfig.BottomIo * 64 * KiB; uma_size = (u64)parms->MemConfig.UmaSize * 64 * KiB; -- To view, visit https://review.coreboot.org/29229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie8ea4fcbfd52c46ad441890f0decaf0f55816cfd Gerrit-Change-Number: 29229 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Fix 80+ characters lines
by Richard Spiegel (Code Review) 23 Oct '18

23 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29228 Change subject: soc/amd/stoneyridge: Fix 80+ characters lines ...................................................................... soc/amd/stoneyridge: Fix 80+ characters lines There some files that do have at least 1 line over the 80 characters limit. Find and fix them. BUG=b:117950052 TEST=Build grunt. Change-Id: I1083a7559919e05a3e3a2dac99f571c161bb4c27 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/pci/amd_pci_util.c M src/soc/amd/stoneyridge/include/soc/nvs.h M src/soc/amd/stoneyridge/northbridge.c 3 files changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29228/1 diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c index 8127601..e0b3c3d 100644 --- a/src/soc/amd/common/block/pci/amd_pci_util.c +++ b/src/soc/amd/common/block/pci/amd_pci_util.c @@ -98,7 +98,9 @@ void write_pci_cfg_irqs(void) { struct device *dev = NULL; /* Our current device to route IRQs */ - struct device *target_dev = NULL; /* to bridge a device may be connected to */ + struct device *target_dev = NULL; /* the bridge a device may be + *connected to + */ u16 int_pin = 0; /* Value of the INT_PIN register 0x3D */ u16 target_pin = 0; /* Pin we will search our tables for */ u16 int_line = 0; /* IRQ # read from PCI_INTR tbl and write to 3C */ diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 3e6ef30..7578f9d 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -43,7 +43,9 @@ uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ - uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */ + uint8_t scdo; /* 0x2A - GPIO pad offset relative + * to the community + */ uint8_t tmps; /* 0x2B - Temperature Sensor ID */ uint8_t tlvl; /* 0x2C - Throttle Level Limit */ uint8_t flvl; /* 0x2D - Current FAN Level */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d17d855..88a74b0 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -86,7 +86,9 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device *dev, + struct resource *resource, + u32 nodeid) { resource_t rbase, rend; unsigned int reg, link_num; -- To view, visit https://review.coreboot.org/29228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1083a7559919e05a3e3a2dac99f571c161bb4c27 Gerrit-Change-Number: 29228 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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coreboot-gerrit October 2018