coreboot-gerrit September 2017

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Change in coreboot[master]: amd/stoneyridge: Put S5-S0 AGESA heap into cbmem
by Marshall Dawson (Code Review) 19 Sep '17

19 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21594 Change subject: amd/stoneyridge: Put S5-S0 AGESA heap into cbmem ...................................................................... amd/stoneyridge: Put S5-S0 AGESA heap into cbmem Now that soc/amd supports EARLY_CBMEM_INIT, put the HEAP into cbmem, allowing better control of its cacheability in subsequent patches. This relocates the heap initialization from the common directory into stoneyridge (i.e. now expected to be non-generic), and places it later than cbmem initialization. The conversion relies on cbmem_add() first searching cbmem for the ID before adding a new entry. Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/agesawrapper.c M src/soc/amd/common/heapmanager.c M src/soc/amd/stoneyridge/romstage.c 3 files changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/21594/1 diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index 3ad4871..eea0ddc 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -174,8 +174,6 @@ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); return status; } diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/heapmanager.c index 902fb15..58b072b 100644 --- a/src/soc/amd/common/heapmanager.c +++ b/src/soc/amd/common/heapmanager.c @@ -22,12 +22,7 @@ void *GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) { - void *heap = (void *)BIOS_HEAP_START_ADDRESS; - - if (acpi_is_wakeup_s3()) - heap = cbmem_find(CBMEM_ID_RESUME_SCRATCH); - - return heap; + return cbmem_add(CBMEM_ID_RESUME_SCRATCH, BIOS_HEAP_SIZE); } void EmptyHeap(void) diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index da1d4b9..5ed02bb 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -24,6 +24,7 @@ #include <soc/northbridge.h> #include <soc/southbridge.h> #include <amdblocks/psp.h> +#include <BiosCallOuts.h> asmlinkage void car_stage_entry(void) { @@ -70,6 +71,9 @@ post_code(0x43); cbmem_initialize_empty(); + /* Establish AGESA's heap. */ + EmptyHeap(); + /* * This writes contents to DRAM backing before teardown. * todo: move CAR teardown to postcar implementation and -- To view, visit https://review.coreboot.org/21594 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848 Gerrit-Change-Number: 21594 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Convert GetHeapBase to void pointer
by Marshall Dawson (Code Review) 19 Sep '17

19 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21593 Change subject: soc/amd/common: Convert GetHeapBase to void pointer ...................................................................... soc/amd/common: Convert GetHeapBase to void pointer Change the type of value returned by GetHeapBase(). This should be innocuous, and will allow a subsequent patch to be simpler. Change-Id: Id4a024d000a514ea9a44f9dfc2caffae9ff01789 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/BiosCallOuts.h M src/soc/amd/common/heapmanager.c 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/21593/1 diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/BiosCallOuts.h index 4456466..00ce745 100644 --- a/src/soc/amd/common/BiosCallOuts.h +++ b/src/soc/amd/common/BiosCallOuts.h @@ -35,7 +35,7 @@ UINT32 NextNodeOffset; } BIOS_BUFFER_NODE; -UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); +void *GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); void EmptyHeap(void); AGESA_STATUS agesa_AllocateBuffer(UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/heapmanager.c index 6c240eb..902fb15 100644 --- a/src/soc/amd/common/heapmanager.c +++ b/src/soc/amd/common/heapmanager.c @@ -20,19 +20,19 @@ #include <heapManager.h> #include <string.h> -UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) +void *GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) { - UINT32 heap = BIOS_HEAP_START_ADDRESS; + void *heap = (void *)BIOS_HEAP_START_ADDRESS; if (acpi_is_wakeup_s3()) - heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH); + heap = cbmem_find(CBMEM_ID_RESUME_SCRATCH); return heap; } void EmptyHeap(void) { - void *BiosManagerPtr = (void *)GetHeapBase(NULL); + void *BiosManagerPtr = GetHeapBase(NULL); memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); } @@ -58,7 +58,7 @@ AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof(BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *)GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *)BiosHeapBaseAddr; if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { @@ -215,7 +215,7 @@ AllocParams = (AGESA_BUFFER_PARAMS *)ConfigPtr; - BiosHeapBaseAddr = (UINT8 *)GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *)BiosHeapBaseAddr; /* Find target node to deallocate in list of allocated nodes. @@ -338,7 +338,7 @@ AllocParams = (AGESA_BUFFER_PARAMS *)ConfigPtr; - BiosHeapBaseAddr = (UINT8 *)GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBaseAddr = GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *)BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; -- To view, visit https://review.coreboot.org/21593 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id4a024d000a514ea9a44f9dfc2caffae9ff01789 Gerrit-Change-Number: 21593 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT table
by build bot (Jenkins) (Code Review) 19 Sep '17

19 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21531 ) Change subject: mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT table ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60690/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15892/ : SUCCESS -- To view, visit https://review.coreboot.org/21531 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id0b2b9e9ae2755ed89cee337a1a085fc4e95b073 Gerrit-Change-Number: 21531 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Wei-nan Liu <wei-nan.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 01:00:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add PCIE IRQs
by build bot (Jenkins) (Code Review) 19 Sep '17

19 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21530 ) Change subject: soc/intel/cannonlake: Add PCIE IRQs ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60689/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15891/ : SUCCESS -- To view, visit https://review.coreboot.org/21530 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e Gerrit-Change-Number: 21530 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Wei-nan Liu <wei-nan.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 00:53:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8: Add support for bluetooth on wifi
by Jonathan Neuschäfer (Code Review) 19 Sep '17

19 Sep '17

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/21578 ) Change subject: ec/lenovo/h8: Add support for bluetooth on wifi ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/21578 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I23f14c937252a296dc543db49ec9e093e7e24604 Gerrit-Change-Number: 21578 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 00:09:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection
by Jonathan Neuschäfer (Code Review) 19 Sep '17

19 Sep '17

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/21587 ) Change subject: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/21587 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c Gerrit-Change-Number: 21587 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Sep 2017 00:08:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/purism/librem13v2: Remove redundant MAINBOARD_VENDOR setting
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21591 ) Change subject: mb/purism/librem13v2: Remove redundant MAINBOARD_VENDOR setting ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60688/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15890/ : SUCCESS -- To view, visit https://review.coreboot.org/21591 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If0b33df01ff3327272d089b7efb8e64fa1233fdf Gerrit-Change-Number: 21591 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 20:04:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Adding the PSP SMM implementation (WIP)
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21564 ) Change subject: soc/amd/stoneyridge: Adding the PSP SMM implementation (WIP) ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60684/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15886/ : SUCCESS -- To view, visit https://review.coreboot.org/21564 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I88d45b73263369917b67a2e586f44e331bb7028b Gerrit-Change-Number: 21564 Gerrit-PatchSet: 4 Gerrit-Owner: frank vibrans <frank.vibrans(a)scarletltd.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: frank vibrans <frank.vibrans(a)scarletltd.com> Gerrit-Comment-Date: Mon, 18 Sep 2017 20:02:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: timer: Add helper function stopwatch_wait_until_expired
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21589 ) Change subject: timer: Add helper function stopwatch_wait_until_expired ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60687/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15889/ : SUCCESS -- To view, visit https://review.coreboot.org/21589 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia888907028d687e3d17e5a088657086a3c839ad3 Gerrit-Change-Number: 21589 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 20:01:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Use stopwatch_wait_until_expired where applicable
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21590 ) Change subject: Use stopwatch_wait_until_expired where applicable ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60685/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15887/ : SUCCESS -- To view, visit https://review.coreboot.org/21590 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4d6c6810b91294a7e401a4a1a446218c04c98e55 Gerrit-Change-Number: 21590 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 19:52:44 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017