coreboot-gerrit September 2017

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Change in coreboot[master]: soc/intel/skylake: Refactor memory layout calculation
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21537 ) Change subject: soc/intel/skylake: Refactor memory layout calculation ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60679/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15881/ : SUCCESS -- To view, visit https://review.coreboot.org/21537 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f Gerrit-Change-Number: 21537 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 19:16:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add PCIE IRQs
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21530 ) Change subject: soc/intel/cannonlake: Add PCIE IRQs ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60676/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15878/ : SUCCESS -- To view, visit https://review.coreboot.org/21530 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e Gerrit-Change-Number: 21530 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Wei-nan Liu <wei-nan.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 19:02:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT table
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21531 ) Change subject: mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT table ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60677/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15879/ : SUCCESS -- To view, visit https://review.coreboot.org/21531 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id0b2b9e9ae2755ed89cee337a1a085fc4e95b073 Gerrit-Change-Number: 21531 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Wei-nan Liu <wei-nan.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 19:01:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: Improve error returning and debug output
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21480 ) Change subject: device/dram/ddr2.c: Improve error returning and debug output ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60674/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15876/ : SUCCESS -- To view, visit https://review.coreboot.org/21480 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Gerrit-Change-Number: 21480 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 18:20:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [NEEDSTEST] soc/intel/skylake: Generate ACPI DMAR table
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21588 ) Change subject: [NEEDSTEST] soc/intel/skylake: Generate ACPI DMAR table ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60675/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15877/ : SUCCESS -- To view, visit https://review.coreboot.org/21588 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Gerrit-Change-Number: 21588 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 18:19:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [NEEDSTEST] soc/intel/skylake: Generate ACPI DMAR table
by Nico Huber (Code Review) 18 Sep '17

18 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21588 Change subject: [NEEDSTEST] soc/intel/skylake: Generate ACPI DMAR table ...................................................................... [NEEDSTEST] soc/intel/skylake: Generate ACPI DMAR table Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/include/soc/acpi.h M src/soc/intel/skylake/include/soc/p2sb.h 4 files changed, 76 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/21588/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index cfb98cd..9ebf5fa 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -31,12 +31,14 @@ #include <cpu/intel/turbo.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> +#include <intelblocks/systemagent.h> #include <soc/intel/common/acpi.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/msr.h> +#include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/ramstage.h> @@ -534,6 +536,73 @@ } } +static unsigned long acpi_fill_dmar(unsigned long current) +{ + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); + const u32 gfx_vtbar = MCHBAR32(0x5400) & ~0xfff; + + /* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */ + if (igfx_dev && igfx_dev->enabled && gfx_vtbar && !MCHBAR32(0x5404)) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); + current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0); + current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 1); + + acpi_dmar_drhd_fixup(tmp, current); + } + + struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); + const u32 vtvc0bar = MCHBAR32(0x5410) & ~0xfff; + + /* General VTBAR has to be set and in 32-bit space. */ + if (p2sb_dev && vtvc0bar && !MCHBAR32(0x5414)) { + const unsigned long tmp = current; + + /* P2SB may already be hidden. There's no clear rule, when. */ + const u8 p2sb_hidden = + pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1); + pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0); + + const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); + const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + + pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden); + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_drhd_ds_ioapic(current, + 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); + current += acpi_create_dmar_drhd_ds_msi_hpet(current, + 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + + acpi_dmar_drhd_fixup(tmp, current); + } + + return current; +} + +unsigned long northcluster_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT); + + /* Create DMAR table only if we have VT-d capability. */ + if (!root_dev || pci_read_config32(root_dev, 0xe4) & 1 << 23) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + current = acpi_align_current(current); + + return current; +} + unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci = acpi_sci_irq(); diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7014c24..a52c9aa 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -49,7 +49,8 @@ .scan_bus = &pci_domain_scan_bus, .ops_pci_bus = &pci_bus_default_ops, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - .acpi_name = &soc_acpi_name, + .write_acpi_tables = &northcluster_write_acpi_tables, + .acpi_name = &soc_acpi_name, #endif }; diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h index 94c7c2f..e3da126 100644 --- a/src/soc/intel/skylake/include/soc/acpi.h +++ b/src/soc/intel/skylake/include/soc/acpi.h @@ -32,5 +32,7 @@ void southcluster_inject_dsdt(device_t device); unsigned long southcluster_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); +unsigned long northcluster_write_acpi_tables(struct device *, + unsigned long current, struct acpi_rsdp *); #endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h index d846dfc..09e73fc 100644 --- a/src/soc/intel/skylake/include/soc/p2sb.h +++ b/src/soc/intel/skylake/include/soc/p2sb.h @@ -19,6 +19,9 @@ #define HPTC_OFFSET 0x60 #define HPTC_ADDR_ENABLE_BIT (1 << 7) +#define PCH_P2SB_IBDF 0x6c +#define PCH_P2SB_HBDF 0x70 + #define PCH_P2SB_EPMASK0 0xB0 #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) -- To view, visit https://review.coreboot.org/21588 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Gerrit-Change-Number: 21588 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21587 ) Change subject: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60673/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15875/ : SUCCESS -- To view, visit https://review.coreboot.org/21587 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c Gerrit-Change-Number: 21587 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 16:40:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection
by Patrick Rudolph (Code Review) 18 Sep '17

18 Sep '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/21587 Change subject: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection ...................................................................... mb/lenovo/x2?0/devicetree: Fix regression of BDC detection The x220 and x230 do have BDC detection, but it's broken. Disable BDC detection on those two boards, and add a comment why it doesn't work. The issue has been reported and tested on Lenovo X220. Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/21587/1 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 1332cd8..2aa2431 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -165,7 +165,9 @@ register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" - register "has_bdc_detection" = "1" + # BDC detection is broken on this board as pin14 of + # the BDC's connector is left floating. + register "has_bdc_detection" = "0" register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" end diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index d7f5647..b2527c4 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -167,7 +167,9 @@ register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" - register "has_bdc_detection" = "1" + # BDC detection is broken on this board as pin14 of + # the BDC's connector is left floating. + register "has_bdc_detection" = "0" register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" end -- To view, visit https://review.coreboot.org/21587 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c Gerrit-Change-Number: 21587 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: siemens/mc_apl1: Move SCI to IRQ 10
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21586 ) Change subject: siemens/mc_apl1: Move SCI to IRQ 10 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60672/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15874/ : SUCCESS -- To view, visit https://review.coreboot.org/21586 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3 Gerrit-Change-Number: 21586 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 15:54:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Makefile: Don't rebuild when generating tags or file list
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21585 ) Change subject: Makefile: Don't rebuild when generating tags or file list ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60671/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15873/ : SUCCESS -- To view, visit https://review.coreboot.org/21585 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9cc12ef3d1990c3422625630451b2a7b8d77829c Gerrit-Change-Number: 21585 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 15:45:34 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017