coreboot-gerrit September 2017

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Change in coreboot[master]: soc/intel/apollolake: Make SCI configurable
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21584 ) Change subject: soc/intel/apollolake: Make SCI configurable ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60670/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15872/ : SUCCESS -- To view, visit https://review.coreboot.org/21584 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1 Gerrit-Change-Number: 21584 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 15:37:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: siemens/mc_apl1: Move SCI to IRQ 10
by Mario Scheithauer (Code Review) 18 Sep '17

18 Sep '17

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/21586 Change subject: siemens/mc_apl1: Move SCI to IRQ 10 ...................................................................... siemens/mc_apl1: Move SCI to IRQ 10 IRQ 9 is used for different purpose on this mainboard so move SCI away to IRQ 10. Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/21586/1 diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb index 7f4983e..04b3ae5 100644 --- a/src/mainboard/siemens/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -4,6 +4,8 @@ device lapic 0 on end end + register "sci_irq" = "SCIS_IRQ10" + # Disable unused clkreq of PCIe root ports register "pcie_rp0_clkreq_pin" = "3" # PCIe-PCI-Bridge register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" -- To view, visit https://review.coreboot.org/21586 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3 Gerrit-Change-Number: 21586 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: Makefile: Don't rebuild when generating tags or file list
by Martin Roth (Code Review) 18 Sep '17

18 Sep '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21585 Change subject: Makefile: Don't rebuild when generating tags or file list ...................................................................... Makefile: Don't rebuild when generating tags or file list Generating a project file list used to do a rebuild of the project. Instead, just make sure there's a coreboot.rom file present and if it is, generate the list. Change-Id: I9cc12ef3d1990c3422625630451b2a7b8d77829c Signed-off-by: Martin Roth <martinroth(a)google.com> --- M Makefile 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/21585/1 diff --git a/Makefile b/Makefile index 383d583..4ad0177 100644 --- a/Makefile +++ b/Makefile @@ -369,13 +369,16 @@ $(shell mkdir -p $(KCONFIG_SPLITCONFIG) $(objk)/lxdialog $(additional-dirs) $(alldirs)) endif -$(obj)/project_filelist.txt: all +$(obj)/project_filelist.txt: + if [ -z "$(wildcard $(obj)/coreboot.rom)" ]; then \ + echo "*** Error: Project must be built before generating file list ***"; \ + exit 1; \ + fi find $(obj) -name "*.d" -exec cat {} \; | \ sed 's/[:\\]/ /g' | sed 's/ /\n/g' | sort | uniq | \ grep -v '\.o$$' > $(obj)/project_filelist.txt -filelist: clean - $(MAKE) $(obj)/project_filelist.txt +filelist: $(obj)/project_filelist.txt printf "\nFiles used in build:\n" cat $(obj)/project_filelist.txt -- To view, visit https://review.coreboot.org/21585 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9cc12ef3d1990c3422625630451b2a7b8d77829c Gerrit-Change-Number: 21585 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/intel/apollolake: Make SCI configurable
by Mario Scheithauer (Code Review) 18 Sep '17

18 Sep '17

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/21584 Change subject: soc/intel/apollolake: Make SCI configurable ...................................................................... soc/intel/apollolake: Make SCI configurable The System Control Interrupt is routed per default to IRQ 9. Some mainboards use IRQ 9 for different purpose. Therefore it is necessary to make the SCI configurable on Apollo Lake. Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h M src/soc/intel/common/block/include/intelblocks/acpi.h 4 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/21584/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index e4846e4..df4e630 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. + * Copyright 2017 Siemens AG. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -69,6 +70,12 @@ return read32((void *)pmc_bar + IRQ_REG); } +void soc_write_sci_irq_select(uint32_t scis) +{ + uintptr_t pmc_bar = soc_read_pmc_base(); + write32((void *)pmc_bar + IRQ_REG, scis); +} + acpi_cstate_t *soc_get_cstate_map(size_t *entries) { *entries = ARRAY_SIZE(cstate_map); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 2c47766..cdeb0a0 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 - 2017 Intel Corp. + * Copyright 2017 Siemens AG. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * @@ -25,6 +26,7 @@ #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> +#include <intelblocks/acpi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> #include <fsp/api.h> @@ -287,6 +289,29 @@ MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN; } +/* Overwrites the SCI IRQ if another IRQ number is given by device tree. */ +static void set_sci_irq(void) +{ + static struct soc_intel_apollolake_config *cfg; + struct device *dev = SA_DEV_ROOT; + uint32_t scis; + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + + cfg = dev->chip_info; + + /* Change only if an device tree entry exists. */ + if (cfg->sci_irq) { + scis = soc_read_sci_irq_select(); + scis &= ~SCI_IRQ_SEL; + scis |= (cfg->sci_irq << SCI_IRQ_ADJUST); + soc_write_sci_irq_select(scis); + } +} + static void soc_init(void *data) { struct global_nvs_t *gnvs; @@ -319,6 +344,12 @@ /* Set RAPL MSR for Package power limits*/ set_power_limits(); + + /* + * FSP-S routes SCI to IRQ 9. With the help of this function you can + * select another IRQ for SCI. + */ + set_sci_irq(); } static void soc_final(void *data) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 33e2dad..882e481 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Intel Corp. + * Copyright 2017 Siemens AG. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -78,6 +79,9 @@ */ uint32_t emmc_rx_cmd_data_cntl2; + /* Specifies on which IRQ the SCI will internally appear. */ + uint8_t sci_irq; + /* Configure serial IRQ (SERIRQ) line. */ enum serirq_mode serirq_mode; diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 010773b..85e6ca3 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Intel Corp. + * Copyright 2017 Siemens AG. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,6 +32,9 @@ /* Read the scis from soc specific register. Returns int scis value */ uint32_t soc_read_sci_irq_select(void); +/* Write the scis from soc specific register. */ +void soc_write_sci_irq_select(uint32_t scis); + /* * Calls acpi_write_hpet which creates and fills HPET table and * adds it to the RSDT (and XSDT) structure. -- To view, visit https://review.coreboot.org/21584 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1 Gerrit-Change-Number: 21584 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: device/dram/ddr2.c: Improve error returning and debug output
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21480 ) Change subject: device/dram/ddr2.c: Improve error returning and debug output ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60669/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15871/ : SUCCESS -- To view, visit https://review.coreboot.org/21480 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Gerrit-Change-Number: 21480 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 10:40:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 58: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60668/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/15870/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-Change-Number: 18305 Gerrit-PatchSet: 58 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Sep 2017 10:13:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: Improve error returning and debug output
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21480 ) Change subject: device/dram/ddr2.c: Improve error returning and debug output ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/60666/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/15868/ : SUCCESS -- To view, visit https://review.coreboot.org/21480 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Gerrit-Change-Number: 21480 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 10:05:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 57: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/60665/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/15867/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-Change-Number: 18305 Gerrit-PatchSet: 57 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Sep 2017 09:57:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ifdtool: port the feature to set AltMeDisable/HAP bit here
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21437 ) Change subject: ifdtool: port the feature to set AltMeDisable/HAP bit here ...................................................................... Patch Set 26: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15866/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60664/ : SUCCESS -- To view, visit https://review.coreboot.org/21437 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a2ecc60cfbb9ee9d96f15be3d53226cb428729a Gerrit-Change-Number: 21437 Gerrit-PatchSet: 26 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 08:06:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ifdtool: refactor region-permission-related feature
by build bot (Jenkins) (Code Review) 18 Sep '17

18 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21416 ) Change subject: ifdtool: refactor region-permission-related feature ...................................................................... Patch Set 32: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15865/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60663/ : SUCCESS -- To view, visit https://review.coreboot.org/21416 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4d34606545db4d970ce3ec202da4bf4c5cbad18c Gerrit-Change-Number: 21416 Gerrit-PatchSet: 32 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Sep 2017 07:43:30 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017