coreboot-gerrit August 2017

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Change in coreboot[master]: src/mainboard/intel/cannonlake: Add gpio support for cannonlake
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21139 ) Change subject: src/mainboard/intel/cannonlake: Add gpio support for cannonlake ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/59034/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14372/ : SUCCESS -- To view, visit https://review.coreboot.org/21139 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc Gerrit-Change-Number: 21139 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Aug 2017 01:53:15 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: src/mainboard/intel/cannonlake: Add gpio support for cannonlake
by John Zhao (Code Review) 22 Aug '17

22 Aug '17

Hello John Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/21139 to review the following change. Change subject: src/mainboard/intel/cannonlake: Add gpio support for cannonlake ...................................................................... src/mainboard/intel/cannonlake: Add gpio support for cannonlake Add gpio pins configuration for cannonlake rvp u/y boards. Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc Signed-off-by: john zhao <john.zhao(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig M src/mainboard/intel/cannonlake_rvp/Makefile.inc A src/mainboard/intel/cannonlake_rvp/bootblock.c A src/mainboard/intel/cannonlake_rvp/chromeos.c A src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc A src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c A src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h A src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variants/gpio.h A src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h 10 files changed, 548 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/21139/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index c59abcf..7715b72 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -4,6 +4,7 @@ def_bool y select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_CANNONLAKE + select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select GENERIC_SPD_BIN config MAINBOARD_DIR diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc index dd8303f..91820b2 100644 --- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc +++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc @@ -16,5 +16,10 @@ subdirs-y += spd +bootblock-y += bootblock.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/cannonlake_rvp/bootblock.c b/src/mainboard/intel/cannonlake_rvp/bootblock.c new file mode 100644 index 0000000..781273f --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/bootblock.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c new file mode 100644 index 0000000..6067aed --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <rules.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include <variant/gpio.h> + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif /* ENV_RAMSTAGE */ + +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc new file mode 100644 index 0000000..9fb63f5 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c new file mode 100644 index 0000000..7c0909e --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c @@ -0,0 +1,348 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* GPPC */ + /* A0 : RCINB_TIME_SYNC_1 */ + /* A1 : ESPI_IO_0 */ + /* A2 : ESPI_IO_1 */ + /* A3 : ESPI_IO_2 */ + /* A4 : ESPI_IO_3 */ + /* A5 : ESPI_CSB */ + /* A6 : SERIRQ */ + /* A7 : PRIQAB_GSP10_CS1B */ + PAD_CFG_GPI_ACPI_SCI(GPP_A7, 20K_PU, PLTRST, NONE), + /* A8 : CLKRUNB */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_GPO(GPP_A8, 1, PLTRST), +#endif + /* A9 : CLKOUT_LPC_0_ESPI_CLK */ + /* A10 : CLKOUT_LPC_1 */ + /* A11 : PMEB_GSP11_CS1B */ + PAD_CFG_GPI_SCI_LOW(GPP_A11, 20K_PU, DEEP, LEVEL), + /* A12 : BM_BUSYB_ISH__GP_6 */ + /* A13 : SUSWARNB_SUSPWRDNACK */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* A14 : SUS_STATB_ESPI_RESETB */ + /* A15 : SUSACKB */ + PAD_CFG_GPO(GPP_A15, 1, PLTRST), + /* A16 : SD_1P8_SEL */ + PAD_CFG_GPO(GPP_A16, 0, PLTRST), + /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */ + /* A18 : ISH_GP_0 */ + PAD_CFG_NF(GPP_A18, 20K_PU, DEEP, GPIO), + /* A19 : ISH_GP_1 */ + PAD_CFG_NF(GPP_A18, 20K_PU, DEEP, GPIO), + /* A20 : ISH_GP_2 */ + PAD_CFG_NF(GPP_A18, 20K_PU, DEEP, GPIO), + /* A21 : ISH_GP_3 */ + PAD_CFG_NF(GPP_A18, 20K_PU, DEEP, GPIO), + /* A22 : ISH_GP_4 */ + PAD_CFG_NF(GPP_A23, 20K_PU, DEEP, GPIO), + /* A23 : ISH_GP_5 */ + PAD_CFG_NF(GPP_A23, 20K_PU, DEEP, GPIO), + + /* B0 : CORE_VID_0 */ + /* B1 : CORE_VID_1 */ + /* B2 : VRALERTB */ + PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP), + /* B3 : CPU_GP_2 */ + PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + /* B4 : CPU_GP_3 */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B5 : SRCCLKREQB_0 */ + /* B6 : SRCCLKREQB_1 */ + /* B7 : SRCCLKREQB_2 */ + /* B8 : SRCCLKREQB_3 */ + /* B9 : SRCCLKREQB_4 */ + /* B10 : SRCCLKREQB_5 */ + /* B11 : EXT_PWR_GATEB */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +#else + PAD_CFG_GPO(GPP_B11, 1, PLTRST), +#endif + /* B12 : SLP_S0B */ + /* B13 : PLTRSTB */ + /* B14 : SPKR */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + /* B15 : GSPI0_CS0B */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, GPIO), + /* B16 : GSPI0_CLK */ + PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST), + /* B17 : GSPI0_MISO */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), + /* B18 : GSPI0_MOSI */ + PAD_CFG_GPO(GPP_B18, 1, PLTRST), + /* B19 : GSPI1_CS0B */ + /* B20 : GSPI1_CLK_NFC_CLK */ + /* B21 : GSPI1_MISO_NFC_CLKREQ */ + /* B22 : GSP1_MOSI */ + /* B23 : SML1ALERTB_PCHHOTB */ + PAD_CFG_GPO(GPP_B23, 1, DEEP), + + /* C0 : SMBCLK */ + /* C1 : SMBDATA */ + /* C2 : SMBALERTB */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), + /* C3 : SML0CLK */ + /* C4 : SML0DATA */ + /* C5 : SML0ALERTB */ + PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL), + /* C6 : SML1CLK */ + /* C7 : SML1DATA */ + /* C8 : UART0_RXD */ + PAD_CFG_GPI_APIC_INVERT(GPP_C8, 20K_PU, DEEP), + /* C9 : UART0_TXD */ + PAD_CFG_GPI_SCI_LOW(GPP_C9, 20K_PU, PLTRST, EDGE_SINGLE), + /* C10 : UART0_RTSB */ + PAD_CFG_GPO(GPP_C10, 0, PLTRST), + /* C11 : UART0_CTSB */ + PAD_CFG_GPI_SCI_LOW(GPP_C11, 20K_PU, DEEP, LEVEL), + /* C12 : UART1_RXD_ISH_UART1_RXD */ + PAD_CFG_GPO(GPP_C12, 1, PLTRST), + /* C13 : UART1_RXD_ISH_UART1_TXD */ + /* C14 : UART1_RXD_ISH_UART1_RTSB */ + /* C15 : UART1_RXD_ISH_UART1_CTSB */ + PAD_CFG_GPO(GPP_C15, 1, PLTRST), + /* C16 : I2C0_SDA */ + /* C17 : I2C0_SCL */ + /* C18 : I2C1_SDA */ + /* C19 : I2C1_SCL */ + /* C20 : UART2_RXD */ + /* C21 : UART2_TXD */ + /* C22 : UART2_RTSB */ + /* C23 : UART2_CTSB */ + + /* D0 : SPI1_CSB_BK_0 */ + /* D1 : SPI1_CLK_BK_1 */ + /* D2 : SPI1_MISO_IO_1_BK_2 */ + /* D3 : SPI1_MOSI_IO_0_BK_3 */ + /* D4 : IMGCLKOUT_0_BK_4 */ + /* D5 : ISH_I2C0_SDA */ + /* D6 : ISH_I2C0_SCL */ + /* D7 : ISH_I2C1_SDA */ + /* D8 : ISH_I2C1_SCL */ + /* D9 : ISH_SPI_CSB */ + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + /* D10 : ISH_SPI_CLK */ + PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST), + /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */ + PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL), + /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */ + /* D13 : ISH_UART0_RXD_SML0BDATA */ + PAD_CFG_GPO(GPP_D13, 1, DEEP), + /* D14 : ISH_UART0_TXD_SML0BCLK */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */ + /* D16 : ISH_UART0_CTSB_SML0BALERTB */ + PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL), + /* D17 : DMIC_CLK_1_SNDW3_CLK */ + /* D18 : DMIC_DATA_1_SNDW3_DATA */ + /* D19 : DMIC_CLK_0_SNDW4_CLK */ + /* D20 : DMIC_DATA_0_SNDW4_DATA */ + /* D21 : SPI1_IO_2 */ + PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1), + /* D22 : SPI1_IO_3 */ + PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), + /* D23 : SPP_MCLK */ + + /* E0 : SATAXPCIE_0_SATAGP_0 */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1), +#endif + /* E1 : SATAXPCIE_1_SATAGP_1 */ + /* E2 : SATAXPCIE_2_SATAGP_2 */ + PAD_CFG_GPI_APIC(GPP_E2, 20K_PU, PLTRST), + /* E3 : CPU_GP_0 */ + PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), + /* E4 : SATA_DEVSLP_0 */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +#else + PAD_CFG_GPI_SCI_HIGH(GPP_E4, NONE, PLTRST, LEVEL), +#endif + /* E5 : SATA_DEVSLP_1 */ + /* E6 : SATA_DEVSLP_2 */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_GPI_ACPI_SCI(GPP_E6, NONE, DEEP, NONE), +#endif + /* E7 : CPU_GP_1 */ + //PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE, NONE), + /* E8 : SATA_LEDB */ + /* E9 : USB2_OCB_0_GP_BSSB_CLK */ + /* E10 : USB2_OCB_1_GP_BSSB_DI */ + /* E11 : USB2_OCB_2 */ + /* E12 : USB2_OCB_3 */ + /* E13 : DDSP_HPD_0_DISP_MISC_0 */ + /* E14 : DDSP_HPD_0_DISP_MISC_1 */ + /* E15 : DDSP_HPD_0_DISP_MISC_2 */ + /* E16 : DDSP_HPD_0_DISP_MISC_3 */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_GPO(GPP_E16, 1, DEEP), +#else + PAD_CFG_GPI_SCI_HIGH(GPP_E16, NONE, DEEP, LEVEL), +#endif + /* E17 : EDP_HPD_DISP_MISC_4 */ + /* E18 : DDPB_CTRLCLK */ + /* E19 : DDPB_CTRLDATA */ + /* E20 : DDPC_CTRLCLK */ + /* E21 : DDPC_CTRLDATA */ + /* E22 : DDPD_CTRLCLK */ + /* E23 : DDPD_CTRLDATA */ + + /* F0 : CNV_GNSS_PA_BLANKING */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, GPIO), + /* F1 : CNV_GNSS_FAT */ + PAD_CFG_TERM_GPO(GPP_F1, 1, 20K_PU, DEEP), + /* F2 : CNV_GNSS_SYSCK */ + PAD_CFG_TERM_GPO(GPP_F2, 1, 20K_PU, PLTRST), + /* F3 : GPP_F_3 */ + PAD_CFG_TERM_GPO(GPP_F3, 0, 20K_PU, PLTRST), + /* F4 : CNV_BRI_DT_UART0_RTSB */ + PAD_CFG_NF(GPP_F4, 20K_PU, DEEP, GPIO), + /* F5 : CNV_BRI_RSP_UART0_RXD */ + PAD_CFG_NF(GPP_F5, 20K_PU, DEEP, GPIO), + /* F6 : CNV_RGI_DT_UART0_TXD */ + PAD_CFG_NF(GPP_F6, 20K_PU, DEEP, GPIO), + /* F7 : CNV_RGI_DT_RSP_UART9_CTSB */ + PAD_CFG_NF(GPP_F7, 20K_PU, DEEP, GPIO), + /* F8 : CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_F8, 20K_PU, DEEP, NF1), + /* F9 : CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_F9, 20K_PU, DEEP, NF1), + /* F10 : GPP_F_10 */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_GPO(GPP_F10, 1, DEEP), +#endif + PAD_CFG_GPI_APIC(GPP_F11, 20K_PU, PLTRST), + /* F11 : EMMC_CMD */ + /* F12 : EMMC_DATA0 */ + /* F13 : EMMC_DATA1 */ + /* F14 : EMMC_DATA2 */ + /* F15 : EMMC_DATA3 */ + /* F16 : EMMC_DATA4 */ + /* F17 : EMMC_DATA5 */ + /* F18 : EMMC_DATA6 */ + /* F19 : EMMC_DATA9 */ + /* F20 : EMMC_RCLK */ + /* F21 : EMMC_CLK */ + /* F22 : EMMC_RESETB */ + /* F23 : EMMC_PRESENT */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_GPI(GPP_F23, 20K_PU, DEEP), +#endif + /* G0 : SD3_D2 */ + /* G1 : SD3_D0_SD4_RCLK_P */ + /* G2 : SD3_D1_SD4_RCLK_N */ + /* G3 : SD3_D2 */ + /* G4 : SD3_D3 */ + /* G5 : SD3_CDB */ + PAD_CFG_NF(GPP_G5, 20K_PU, DEEP, GPIO), + /* G6 : SD3_CLK */ + /* G7 : SD3_WP */ + PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, GPIO), + + /* H0 : SSP2_SCLK */ + PAD_CFG_NF(GPP_H0, 20K_PU, DEEP, GPIO), + /* H1 : SSP2_SFRM */ + PAD_CFG_NF(GPP_H1, 20K_PU, DEEP, GPIO), + /* H2 : SSP2_TXD */ + PAD_CFG_NF(GPP_H2, 20K_PU, DEEP, GPIO), + /* H3 : SSP2_RXD */ + PAD_CFG_NF(GPP_H3, 20K_PU, DEEP, GPIO), + /* H4 : I2C2_SDA */ + /* H5 : I2C2_SCL */ + /* H6 : I2C3_SDA */ + /* H7 : I2C3_SCL */ + /* H8 : I2C4_SDA */ + /* H9 : I2C4_SCL */ + /* H10 : I2C5_SDA_ISH_I2C2_SDA */ + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + /* H11 : I2C5_SCL_ISH_I2C2_SCL */ + PAD_CFG_GPO(GPP_H11, 1, PLTRST), + /* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */ + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + /* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */ + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + /* H14 : M2_SKT2_CFG_2 */ + PAD_CFG_GPO(GPP_H14, 0, PLTRST), + /* H15 : M2_SKT2_CFG_3 */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* H16 : DDPF_CTRLCLK */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_GPO(GPP_H16, 1, DEEP), +#endif + /* H17 : DDPF_CTRLDATA */ +#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + PAD_CFG_GPO(GPP_H17, 1, DEEP), +#endif + /* H18 : BOOTMPC */ + /* H19 : TIMESYNC_0 */ + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + /* H20 : IMGCLKOUT_1 */ + /* H21 : GPPC_H_21 */ + /* H22 : GPPC_H_22 */ + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + /* H23 : GPPC_H_23 */ + + /* GPD */ + /* GPD_0 : BATLOWB */ + /* GPD_1 : ACPRESENT */ + /* GPD_2 : LAN_WAKEB */ + /* GPD_3 : PWRBTNB */ + /* GPD_4 : SLP_S3B */ + /* GPD_5 : SLP_S4B */ + /* GPD_6 : SLP_AB */ + /* GPD_7 : GPD_7 */ + /* GPD-8 : SUSCLK */ + /* GPD-9 : SLP_WLANB */ + /* GPD-10 : SLP_5B */ + /* GPD_11 : LANPHYPC */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + +}; + +const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__attribute__((weak)) + variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..323a904 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpio.h> + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..19dfc89 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +const struct cros_gpio *variant_cros_gpios(size_t *num); + + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variants/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variants/gpio.h new file mode 100644 index 0000000..6c824b3 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variants/gpio.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ + diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h new file mode 100644 index 0000000..6c824b3 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ + -- To view, visit https://review.coreboot.org/21139 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc Gerrit-Change-Number: 21139 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Define soc_intel_cannonlake_config
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21080 ) Change subject: soc/intel/cannonlake: Define soc_intel_cannonlake_config ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/59031/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/14371/ : SUCCESS -- To view, visit https://review.coreboot.org/21080 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Gerrit-Change-Number: 21080 Gerrit-PatchSet: 5 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Aug 2017 01:52:17 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/padmelon: Add fintek superio to devicetree
by John E. Kabat Jr. (Code Review) 22 Aug '17

22 Aug '17

John E. Kabat Jr. has abandoned this change. ( https://review.coreboot.org/21138 ) Change subject: amd/padmelon: Add fintek superio to devicetree ...................................................................... Abandoned mistake in push -- To view, visit https://review.coreboot.org/21138 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I10024d380f1d18e374ab309bc992749688c54e79 Gerrit-Change-Number: 21138 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arch/x86/Kconfig: Add deprecation warning to LATE_CBMEM_INIT's help text
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21112 ) Change subject: arch/x86/Kconfig: Add deprecation warning to LATE_CBMEM_INIT's help text ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59030/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14369/ : SUCCESS -- To view, visit https://review.coreboot.org/21112 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Gerrit-Change-Number: 21112 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Aug 2017 01:25:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/padmelon: Enable DRAM
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21036 ) Change subject: amd/padmelon: Enable DRAM ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59029/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14368/ : SUCCESS -- To view, visit https://review.coreboot.org/21036 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f0cf3c24a9d0311432f9224b45296ef5167ed91 Gerrit-Change-Number: 21036 Gerrit-PatchSet: 6 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Aug 2017 00:17:13 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: amd/padmelon: Enable DRAM
by John E. Kabat Jr. (Code Review) 22 Aug '17

22 Aug '17

John E. Kabat Jr. has uploaded a new patch set (#6) to the change originally created by John E. Kabat. ( https://review.coreboot.org/21036 ) Change subject: amd/padmelon: Enable DRAM ...................................................................... amd/padmelon: Enable DRAM Use the normal SPD read callout function. Remove the board-specific function for SPD. Remove the board_id check for the AmdInitPost DDR configuration. Change to a single DIMM per channel and update the devicetree accordingly. Change-Id: I3f0cf3c24a9d0311432f9224b45296ef5167ed91 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/BiosCallOuts.c M src/mainboard/amd/padmelon/OemCustomize.c M src/mainboard/amd/padmelon/devicetree.cb 3 files changed, 7 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/21036/6 -- To view, visit https://review.coreboot.org/21036 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3f0cf3c24a9d0311432f9224b45296ef5167ed91 Gerrit-Change-Number: 21036 Gerrit-PatchSet: 6 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: amd/padmelon: Add fintek superio to devicetree
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21038 ) Change subject: amd/padmelon: Add fintek superio to devicetree ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59028/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14367/ : SUCCESS -- To view, visit https://review.coreboot.org/21038 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I73d128d5fa4227c05fcebe1ed2a3ac98b4923426 Gerrit-Change-Number: 21038 Gerrit-PatchSet: 6 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Aug 2017 00:04:58 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: amd/padmelon: Add fintek superio to devicetree
by John E. Kabat Jr. (Code Review) 21 Aug '17

21 Aug '17

John E. Kabat Jr. has uploaded a new patch set (#6) to the change originally created by John E. Kabat. ( https://review.coreboot.org/21038 ) Change subject: amd/padmelon: Add fintek superio to devicetree ...................................................................... amd/padmelon: Add fintek superio to devicetree Add the path to the device and enable the two UARTs. Leave other devices disabled. Change-Id: I73d128d5fa4227c05fcebe1ed2a3ac98b4923426 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/devicetree.cb 1 file changed, 29 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/21038/6 -- To view, visit https://review.coreboot.org/21038 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I73d128d5fa4227c05fcebe1ed2a3ac98b4923426 Gerrit-Change-Number: 21038 Gerrit-PatchSet: 6 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: amd/padmelon: Add fintek superio to devicetree
by build bot (Jenkins) (Code Review) 21 Aug '17

21 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21138 ) Change subject: amd/padmelon: Add fintek superio to devicetree ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59027/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14366/ : SUCCESS -- To view, visit https://review.coreboot.org/21138 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I10024d380f1d18e374ab309bc992749688c54e79 Gerrit-Change-Number: 21138 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 23:45:48 +0000 Gerrit-HasComments: No

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