coreboot-gerrit August 2017

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Change in coreboot[master]: sb/intel/common/spi.c: Port to i82801gx
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21113 ) Change subject: sb/intel/common/spi.c: Port to i82801gx ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59074/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14410/ : SUCCESS -- To view, visit https://review.coreboot.org/21113 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23 Gerrit-Change-Number: 21113 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Aug 2017 13:56:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Usable dram top calculation based on HW registers
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21150 ) Change subject: soc/intel/skylake: Usable dram top calculation based on HW registers ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59075/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14411/ : SUCCESS -- To view, visit https://review.coreboot.org/21150 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Gerrit-Change-Number: 21150 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 22 Aug 2017 13:54:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/common/spi.c: Port to i82801gx
by Arthur Heymans (Code Review) 22 Aug '17

22 Aug '17

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21113 to look at the new patch set (#4). Change subject: sb/intel/common/spi.c: Port to i82801gx ...................................................................... sb/intel/common/spi.c: Port to i82801gx Offsets are a little different. TESTED on Thinkpad X60 Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Kconfig M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/Makefile.inc 4 files changed, 43 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/21113/4 -- To view, visit https://review.coreboot.org/21113 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I39199f3279a8b76e290b6693adc50dc2ac0ccf23 Gerrit-Change-Number: 21113 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: amd/padmelon: Enable DRAM
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21036 ) Change subject: amd/padmelon: Enable DRAM ...................................................................... Patch Set 7: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59073/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14409/ : SUCCESS -- To view, visit https://review.coreboot.org/21036 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f0cf3c24a9d0311432f9224b45296ef5167ed91 Gerrit-Change-Number: 21036 Gerrit-PatchSet: 7 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Aug 2017 13:26:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/padmelon: Enable DRAM
by John E. Kabat Jr. (Code Review) 22 Aug '17

22 Aug '17

John E. Kabat Jr. has uploaded a new patch set (#7) to the change originally created by John E. Kabat. ( https://review.coreboot.org/21036 ) Change subject: amd/padmelon: Enable DRAM ...................................................................... amd/padmelon: Enable DRAM Use the normal SPD read callout function. Remove the board-specific function for SPD. Remove the board_id check for the AmdInitPost DDR configuration. Change to a single DIMM per channel and update the devicetree accordingly. Change-Id: I3f0cf3c24a9d0311432f9224b45296ef5167ed91 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Signed-off-by: John Kabat <john.kabat(a)scarletltd.com> --- M src/mainboard/amd/padmelon/BiosCallOuts.c M src/mainboard/amd/padmelon/OemCustomize.c M src/mainboard/amd/padmelon/devicetree.cb 3 files changed, 6 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/21036/7 -- To view, visit https://review.coreboot.org/21036 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3f0cf3c24a9d0311432f9224b45296ef5167ed91 Gerrit-Change-Number: 21036 Gerrit-PatchSet: 7 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Usable dram top calculation based on HW registers
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21150 ) Change subject: soc/intel/skylake: Usable dram top calculation based on HW registers ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59072/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14408/ : SUCCESS -- To view, visit https://review.coreboot.org/21150 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Gerrit-Change-Number: 21150 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 22 Aug 2017 12:42:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Early system agent lirary access in postcar stage
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21149 ) Change subject: soc/intel/common: Early system agent lirary access in postcar stage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59070/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14406/ : SUCCESS -- To view, visit https://review.coreboot.org/21149 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie5558cdb7acacc34451e1cf63a3e4239e7901c67 Gerrit-Change-Number: 21149 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Tue, 22 Aug 2017 12:41:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Usable dram top calculation based on HW registers
by build bot (Jenkins) (Code Review) 22 Aug '17

22 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21150 ) Change subject: soc/intel/skylake: Usable dram top calculation based on HW registers ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/59071/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/14407/ : SUCCESS -- To view, visit https://review.coreboot.org/21150 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Gerrit-Change-Number: 21150 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Aug 2017 12:36:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Usable dram top calculation based on HW registers
by Subrata Banik (Code Review) 22 Aug '17

22 Aug '17

Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/21150 ) Change subject: soc/intel/skylake: Usable dram top calculation based on HW registers ...................................................................... soc/intel/skylake: Usable dram top calculation based on HW registers This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot eve and poppy successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/memmap.c 2 files changed, 89 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21150/2 -- To view, visit https://review.coreboot.org/21150 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Gerrit-Change-Number: 21150 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Usable dram top calculation based on HW registers
by Subrata Banik (Code Review) 22 Aug '17

22 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21150 Change subject: soc/intel/skylake: Usable dram top calculation based on HW registers ...................................................................... soc/intel/skylake: Usable dram top calculation based on HW registers This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot eve and poppy successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/memmap.c 2 files changed, 89 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21150/1 diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 52ef640..a7c159a 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -59,6 +59,15 @@ /* CPU Trace reserved memory size */ #define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */ +/* Probeless Trace memory size */ +#define GDXC_MOT_MEMORY_SIZE 0x6000000 /* 96MiB */ +#define GDXC_IOT_MEMORY_SIZE 0x2000000 /* 32MiB */ +#define PSMI_BUFFER_AREA_SIZE 0x4000000 /* 64MiB */ + +/* PTT registers */ +#define PTT_TXT_BASE_ADDRESS 0xfed30800 +#define PTT_PRESENT 0x00070000 + /* * I/O port address space */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 43faabb..34d2e10 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -17,8 +17,10 @@ #include <arch/io.h> #include <cbmem.h> #include <chip.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <intelblocks/systemagent.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/smm.h> @@ -106,6 +108,15 @@ return 0; } +static bool is_ptt_enable(void) +{ + if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == + PTT_PRESENT) + return true; + + return false; +} + /* * Host Memory Map: * @@ -125,6 +136,8 @@ * | PRM (C6DRAM/SGX) | * +--------------------------+ PRMRR * | Trace Memory | + * +--------------------------+ Probless Trace + * | PTT | * +--------------------------+ top_of_ram * | Reserved - FSP/CBMEM | * +--------------------------+ TOLUM @@ -136,41 +149,84 @@ * the base registers from each other to determine sizes of the regions. In * other words, the memory map is in a fixed order no matter what. */ +static u32 calculate_dram_base(void) +{ + const struct soc_intel_skylake_config *config; + const struct device *dev; + uint32_t tolud_base; + uint32_t dram_base; + uint32_t prmrr_base; + size_t prmrr_size; + dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); + + /* Read TOLUD from Host Bridge offset */ + dram_base = tolud_base = sa_get_tolud_base(); + + if (dev->enabled) { + /* Read BDSM from Host Bridge */ + dram_base -= sa_get_dsm_size(); + + /* Read BGSM from Host Bridge */ + dram_base -= sa_get_gsm_size(); + } + /* Get TSEG size */ + dram_base -= smm_region_size(); + + /* Get DPR size */ + if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + dram_base -= sa_get_dpr_size(); + + dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); + config = dev->chip_info; + prmrr_size = config->PrmrrSize; + + /* + * PRMRR Sizes that are > 1MB and < 32MB are + * not supported and will fail out. + */ + if ((prmrr_size > (1*MiB)) && (prmrr_size < (32*MiB))) + die("PRMRR Sizes that are > 1MB and < 32MB are not" + "supported!\n"); + + if (prmrr_size > 0) { + prmrr_base = dram_base - prmrr_size; + if (prmrr_size >= 32*MiB) + /* Make 128 MB align code */ + prmrr_base &= ~(128*MiB - 1); + dram_base = prmrr_base; + } + + if (config->ProbelessTrace) { + /* GDXC MOT */ + dram_base -= GDXC_MOT_MEMORY_SIZE; + /* Round down to natual boundary accroding to PSMI size */ + dram_base &= ~(PSMI_BUFFER_AREA_SIZE - 1); + /* GDXC IOT */ + dram_base -= GDXC_IOT_MEMORY_SIZE; + /* PSMI buffer area */ + dram_base -= PSMI_BUFFER_AREA_SIZE; + } + + if (is_ptt_enable()) + dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */ + + return dram_base; +} + +/* Get usable system memory start address */ static u32 top_of_32bit_ram(void) { - msr_t prmrr_base; - u32 top_of_ram; - const struct device *dev; - const struct soc_intel_skylake_config *config; - /* * Check if Tseg has been initialized, we will use this as a flag * to check if the MRC is done, and only then continue to read the * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before * PRMRR_MASK MSR lock bit is set. */ - top_of_ram = smm_region_start(); - if (top_of_ram == 0) + if (smm_region_start() == 0) return 0; - dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); - config = dev->chip_info; - - /* - * On Skylake, cbmem_top is offset down from PRMRR_BASE by reserved - * memory (128MiB) for CPU trace if enabled, then reserved memory (4KB) - * for PTT if enabled. PTT is in fact not used on Skylake platforms. - * Refer to Fsp Integration Guide for the memory mapping layout. - */ - prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR); - if (prmrr_base.lo) - top_of_ram = prmrr_base.lo; - - if (config->ProbelessTrace) - top_of_ram -= TRACE_MEMORY_SIZE; - - return top_of_ram; + return calculate_dram_base(); } void *cbmem_top(void) -- To view, visit https://review.coreboot.org/21150 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Gerrit-Change-Number: 21150 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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coreboot-gerrit August 2017