John Zhao has posted comments on this change. ( https://review.coreboot.org/21139 )
Change subject: src/mainboard/intel/cannonlake: Add gpio support for cannonlake
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/…
File src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c:
https://review.coreboot.org/#/c/21139/1/src/mainboard/intel/cannonlake_rvp/…
PS1, Line 30: /* A7 : PRIQAB_GSP10_CS1B */
: PAD_CFG_GPI_ACPI_SCI(GPP_A7, 20K_PU, PLTRST, NONE),
> i think you should put the comment after macro for the same pin.
The gpio pins configuration and comments format is consistent with other platforms like poppy.
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Gerrit-Project: coreboot
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Gerrit-MessageType: comment
Gerrit-Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc
Gerrit-Change-Number: 21139
Gerrit-PatchSet: 2
Gerrit-Owner: John Zhao <john.zhao(a)intel.corp-partner.google.com>
Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com>
Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Tue, 22 Aug 2017 16:32:15 +0000
Gerrit-HasComments: Yes
Hello Pratikkumar V Prajapati, John Zhao, Paul Menzel, build bot (Jenkins), Lijian Zhao,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/21139
to look at the new patch set (#2).
Change subject: src/mainboard/intel/cannonlake: Add gpio support for cannonlake
......................................................................
src/mainboard/intel/cannonlake: Add gpio support for cannonlake
Add gpio pins configuration for cannonlake rvp u/y boards.
Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc
Signed-off-by: john zhao <john.zhao(a)intel.com>
---
M src/mainboard/intel/cannonlake_rvp/Kconfig
M src/mainboard/intel/cannonlake_rvp/Makefile.inc
A src/mainboard/intel/cannonlake_rvp/bootblock.c
A src/mainboard/intel/cannonlake_rvp/chromeos.c
A src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc
A src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
A src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h
A src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variants/gpio.h
A src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h
10 files changed, 545 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/21139/2
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Gerrit-Change-Number: 21139
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Gerrit-Owner: John Zhao <john.zhao(a)intel.corp-partner.google.com>
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Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>
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Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
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John E. Kabat Jr. has uploaded a new patch set (#6) to the change originally created by John E. Kabat. ( https://review.coreboot.org/21039 )
Change subject: amd/padmelon: Fix up PCIe settings
......................................................................
amd/padmelon: Fix up PCIe settings
Change devicetree.cb and OemCustomize.c to match the board's
design. This has been checked with a Merlin Falcon APU. Brown
Falcon supports only 4 Gfx lanes.
Add the missing PSP device to the devicetree, remove the
extraneous "hudson" HDA device, and move the two "kern" HDAs
to northbridge (see "root complex" diagram in the BKDG).
Change-Id: Id638c2bc980d5d2bfb4d49290fa24b9869543814
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Signed-off-by: John Kabat <john.kabat(a)scarletltd.com>
---
M src/mainboard/amd/padmelon/OemCustomize.c
M src/mainboard/amd/padmelon/devicetree.cb
2 files changed, 21 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/21039/6
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Gerrit-Change-Id: Id638c2bc980d5d2bfb4d49290fa24b9869543814
Gerrit-Change-Number: 21039
Gerrit-PatchSet: 6
Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com>
Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
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John E. Kabat Jr. has uploaded a new patch set (#9) to the change originally created by John E. Kabat. ( https://review.coreboot.org/21038 )
Change subject: amd/padmelon: Add fintek superio to devicetree
......................................................................
amd/padmelon: Add fintek superio to devicetree
Add the path to the device and enable the two UARTs. Leave
other devices disabled.
Change-Id: I73d128d5fa4227c05fcebe1ed2a3ac98b4923426
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Signed-off-by: John Kabat <john.kabat(a)scarletltd.com>
---
M src/mainboard/amd/padmelon/devicetree.cb
1 file changed, 27 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/21038/9
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Gerrit-Change-Id: I73d128d5fa4227c05fcebe1ed2a3ac98b4923426
Gerrit-Change-Number: 21038
Gerrit-PatchSet: 9
Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com>
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