Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21217 )
Change subject: amd/sb/sb700: Allocate wide LPC I/O devices where possible
......................................................................
Patch Set 1: Code-Review+2
(2 comments)
Patch looks fine but indentation levels could be reduced/improved so that's easier to read on smaller screens. Can happen in a follow up patch ofc.
https://review.coreboot.org/#/c/21217/1/src/southbridge/amd/sb700/lpc.c
File src/southbridge/amd/sb700/lpc.c:
https://review.coreboot.org/#/c/21217/1/src/southbridge/amd/sb700/lpc.c@a166
PS1, Line 166:
:
Could the indentation be reduced by simply doing "continue" on the opposite of this conditional?
https://review.coreboot.org/#/c/21217/1/src/southbridge/amd/sb700/lpc.c@222
PS1, Line 222: "I/O window exhaustion\n", __func__, dev_path(child), base, end);
could this have a few tabs less so it fits the screen more easily?
--
To view, visit https://review.coreboot.org/21217
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I004bd0be31c91b76ae2a5e72690b44dca2fd9297
Gerrit-Change-Number: 21217
Gerrit-PatchSet: 1
Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Sun, 27 Aug 2017 06:58:55 +0000
Gerrit-HasComments: Yes
Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/21219
Change subject: cpu/x86/smm: Fix explicit 'addr32' usage in clang builds
......................................................................
cpu/x86/smm: Fix explicit 'addr32' usage in clang builds
The addr32 prefix is required by binutils, because even when
given an explicit address which is greater than 64KiB, it will
throw a warning about truncation, and stupidly emit the opcode
with a 16-bit addressing mode and the wrong address.
However, in the case of LLVM, this doesn't happen, and is happy
to just use 32-bit addressing whenever it may require it. This
means that LLVM never really needs an explicit addr32 prefix to
use 32-bit addressing in 16-bit mode.
Change-Id: Ia160d3f7da6653ea24c8229dc26f265e5f15aabb
Signed-off-by: Edward O'Callaghan <funfunctor(a)folklore1984.net>
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
M src/cpu/x86/smm/smmrelocate.S
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/21219/1
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 4d388a9..22fbaea 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -112,7 +112,11 @@
*/
mov $0x38000 + 0x7efc, %ebx
+#if IS_ENABLED(CONFIG_COMPILER_LLVM_CLANG)
+ mov (%ebx), %al
+#else
addr32 mov (%ebx), %al
+#endif
cmp $0x64, %al
je 1f
@@ -124,7 +128,11 @@
smm_relocate:
/* Get this CPU's LAPIC ID */
movl $LAPIC_ID, %esi
+#if IS_ENABLED(CONFIG_COMPILER_LLVM_CLANG)
+ movl (%esi), %ecx
+#else
addr32 movl (%esi), %ecx
+#endif
shr $24, %ecx
/* calculate offset by multiplying the
@@ -136,7 +144,11 @@
movl $0xa0000, %eax
subl %edx, %eax /* subtract offset, see above */
+#if IS_ENABLED(CONFIG_COMPILER_LLVM_CLANG)
+ movl %eax, (%ebx)
+#else
addr32 movl %eax, (%ebx)
+#endif
/* The next section of code is potentially southbridge specific */
--
To view, visit https://review.coreboot.org/21219
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia160d3f7da6653ea24c8229dc26f265e5f15aabb
Gerrit-Change-Number: 21219
Gerrit-PatchSet: 1
Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com>