Timothy Pearson has uploaded this change for review. ( https://review.coreboot.org/21217
Change subject: amd/sb/sb700: Allocate wide LPC I/O devices where possible
......................................................................
amd/sb/sb700: Allocate wide LPC I/O devices where possible
When more than 2 wide I/O LPC devices were requested, none of
the devices were actually allocated. Furthermore, even though
more than three wide I/O devices are not permitted, it is better
to allocate the first three than to allocate none.
Always allocate the first three wide I/O devices from the wide
I/O request list.
Change-Id: I004bd0be31c91b76ae2a5e72690b44dca2fd9297
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com>
---
M src/southbridge/amd/sb700/lpc.c
1 file changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/21217/1
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 8ee0395..98d6256 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -217,8 +217,11 @@
reg_x |= (1 << 23);
break;
default:
- if (var_num >= 3)
+ if (var_num >= 3) {
+ printk(BIOS_WARNING, "%s: Ignoring resource %s [base=0x%08x, end=0x%08x] due to"
+ "I/O window exhaustion\n", __func__, dev_path(child), base, end);
continue; /* only 3 var ; compact them ? */
+ }
switch (var_num) {
case 0:
reg_x |= (1 << 2);
@@ -232,7 +235,6 @@
break;
case 2:
reg_x |= (1 << 25);
- reg_x |= (1 << 24);
if ((end - base) < 16)
wiosize |= (1 << 3);
break;
@@ -248,6 +250,7 @@
pci_write_config32(dev, 0x48, reg_x);
/* Set WideIO for as many IOs found (fall through is on purpose) */
switch (var_num) {
+ default:
case 2:
pci_write_config16(dev, 0x90, reg_var[2]);
case 1:
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I004bd0be31c91b76ae2a5e72690b44dca2fd9297
Gerrit-Change-Number: 21217
Gerrit-PatchSet: 1
Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com>
Felix Held has posted comments on this change. ( https://review.coreboot.org/21216 )
Change subject: dp training: Allow to adjust pre-emphasis during clock recovery
......................................................................
Patch Set 1: Code-Review+2
this fixes the issue on the apple minidp->vga adapter
--
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Gerrit-Project: libgfxinit
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ibef5236ca771e0e02beb4e76650ffb6974657846
Gerrit-Change-Number: 21216
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Sun, 27 Aug 2017 00:59:12 +0000
Gerrit-HasComments: No
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21216
Change subject: dp training: Allow to adjust pre-emphasis during clock recovery
......................................................................
dp training: Allow to adjust pre-emphasis during clock recovery
That's not demanded by the spec but there are sinks in the wild that
need it.
Change-Id: Ibef5236ca771e0e02beb4e76650ffb6974657846
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M common/hw-gfx-dp_training.adb
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/16/21216/1
diff --git a/common/hw-gfx-dp_training.adb b/common/hw-gfx-dp_training.adb
index e7411d0..a2d00a7 100644
--- a/common/hw-gfx-dp_training.adb
+++ b/common/hw-gfx-dp_training.adb
@@ -257,8 +257,9 @@
-- According to DP spec, only change preemphasis during channel
-- equalization. What to do if sink requests it during clock recovery?
- -- Linux always accepts new values from the sink, we don't, for now.
- if Success and then (CR_Was_Done and not EQ_Done) then
+ -- Linux always accepts new values from the sink, we too, now: There
+ -- are sinks in the wild that need this.
+ if Success and not EQ_Done then
Train_Set.Pre_Emph :=
DP_Info.Max_Requested_Emph (Status, Link);
if Train_Set.Pre_Emph > Max_Pre_Emph (Port, Train_Set)
--
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Gerrit-Project: libgfxinit
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibef5236ca771e0e02beb4e76650ffb6974657846
Gerrit-Change-Number: 21216
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21215
Change subject: dp training: Fix channel equalization phase
......................................................................
dp training: Fix channel equalization phase
First, allow updates to voltage swing too during channel equalization.
Spec just says to adjust the settings as requested.
Second, the loop conditions differ from the clock recovery phase. We
have only 6 tries in total but no particular order is enforced.
Change-Id: I4673390d8c0f9a5642702872e5b4ab11f54797c7
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M common/hw-gfx-dp_training.adb
1 file changed, 4 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/15/21215/1
diff --git a/common/hw-gfx-dp_training.adb b/common/hw-gfx-dp_training.adb
index 19aa4d3..e7411d0 100644
--- a/common/hw-gfx-dp_training.adb
+++ b/common/hw-gfx-dp_training.adb
@@ -1,5 +1,6 @@
--
-- Copyright (C) 2015-2016 secunet Security Networks AG
+-- Copyright (C) 2017 Nico Huber <nico.h(a)gmx.de>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
@@ -244,7 +245,8 @@
EQ_Done := Success and then DP_Info.All_EQ_Done (Status, Link);
Success := Success and then (CR_Done or not CR_Was_Done);
- if Success and not CR_Done then
+ -- Voltage swing may be updated during channel equalization too.
+ if Success and not EQ_Done then
Train_Set.Voltage_Swing :=
DP_Info.Max_Requested_VS (Status, Link);
if Train_Set.Voltage_Swing > Max_V_Swing (Port)
@@ -366,25 +368,12 @@
end if;
if Success then
- Retries := 0;
- for Tries in 1 .. 32 loop
- pragma Loop_Invariant (Retries <= Max_Retry);
-
+ for Tries in 1 .. 6 loop
Time.U_Delay (EQ_Delay);
- Last_Train_Set := Train_Set;
Sink_Adjust_Training
(Port, DP, Link, Train_Set, CR_Done, EQ_Done, Success);
exit when EQ_Done or not Success;
-
- if Train_Set.Pre_Emph = Last_Train_Set.Pre_Emph then
- exit when Retries = Max_Retry;
- Retries := Retries + 1;
- else
- exit when Last_Train_Set.Pre_Emph =
- Max_Pre_Emph (Port, Last_Train_Set);
- Retries := 0;
- end if;
Set_Signal_Levels (Port, Link, Train_Set);
Sink_Set_Signal_Levels (Port, DP, Link, Train_Set, Success);
--
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Gerrit-Change-Id: I4673390d8c0f9a5642702872e5b4ab11f54797c7
Gerrit-Change-Number: 21215
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/21214 )
Change subject: nb/intel/pineview: Fix typo in DRAM timing computation
......................................................................
Patch Set 2: Code-Review+1
good catch
--
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Gerrit-Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd
Gerrit-Change-Number: 21214
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Sat, 26 Aug 2017 22:48:14 +0000
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/21178 )
Change subject: sb/intel/bd82x6x: make hotplug map consistent to remapped ports
......................................................................
Patch Set 8: Code-Review+2
I've also looked through the affected devicetrees, looks like if it
changes something, than to the better.
--
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Gerrit-Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Gerrit-Change-Number: 21178
Gerrit-PatchSet: 8
Gerrit-Owner: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Sat, 26 Aug 2017 20:42:19 +0000
Gerrit-HasComments: No