Nico Huber has posted comments on this change. ( https://review.coreboot.org/21178 )
Change subject: sb/intel/bd82x6x: make hotplug map consistent to remapped ports
......................................................................
Patch Set 7:
(1 comment)
Looks good now. Alas, I spotted a semantical problem.
https://review.coreboot.org/#/c/21178/7/src/southbridge/intel/bd82x6x/pch.c
File src/southbridge/intel/bd82x6x/pch.c:
https://review.coreboot.org/#/c/21178/7/src/southbridge/intel/bd82x6x/pch.c…
PS7, Line 294: [PCI_FUNC(dev->path.pci.devfn)];
This should be done before the `if`. Slots that didn't move
need the hotplug setting copied too. Alternatively you could
initialize `new_hotplug_map` with the values of the old map.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Gerrit-Change-Number: 21178
Gerrit-PatchSet: 7
Gerrit-Owner: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Sat, 26 Aug 2017 11:44:06 +0000
Gerrit-HasComments: Yes
Hello Arthur Heymans, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/21178
to look at the new patch set (#7).
Change subject: sb/intel/bd82x6x: make hotplug map consistent to remapped ports
......................................................................
sb/intel/bd82x6x: make hotplug map consistent to remapped ports
"pcie_port_coalesce" will cause pcie being remapped under certain
conditions, but flags within "pcie_hotplug_map" should be updated
along with ports.
Test on my lenovo t430s.
Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Signed-off-by: Bill XIE <persmule(a)gmail.com>
---
M src/southbridge/intel/bd82x6x/pch.c
1 file changed, 24 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/21178/7
--
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Gerrit-Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Gerrit-Change-Number: 21178
Gerrit-PatchSet: 7
Gerrit-Owner: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Nico Huber has posted comments on this change. ( https://review.coreboot.org/21178 )
Change subject: sb/intel/bd82x6x: make hotplug map consistent to remapped ports
......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/#/c/21178/6/src/southbridge/intel/bd82x6x/pch.c
File src/southbridge/intel/bd82x6x/pch.c:
https://review.coreboot.org/#/c/21178/6/src/southbridge/intel/bd82x6x/pch.c…
PS6, Line 259: southbridge_intel_bd82x6x_config
> In order to make the 80-char-per-line limit happy, I have to write it like
just write it like this:
static void pch_pcie_devicetree_update(
struct southbridge_intel_bd82x6x_config *config)
(two tabs indent is common in this case)
https://review.coreboot.org/#/c/21178/6/src/southbridge/intel/bd82x6x/pch.c…
PS6, Line 312: return;
Not that I care, but others demand that code follows declarations.
So this should come after the `u32 reg32;`.
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Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
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Gerrit-Comment-Date: Sat, 26 Aug 2017 11:24:54 +0000
Gerrit-HasComments: Yes
Bill XIE has posted comments on this change. ( https://review.coreboot.org/21178 )
Change subject: sb/intel/bd82x6x: make hotplug map consistent to remapped ports
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/21178/6/src/southbridge/intel/bd82x6x/pch.c
File src/southbridge/intel/bd82x6x/pch.c:
https://review.coreboot.org/#/c/21178/6/src/southbridge/intel/bd82x6x/pch.c…
PS6, Line 259: southbridge_intel_bd82x6x_config
In order to make the 80-char-per-line limit happy, I have to write it like this.
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Gerrit-Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Gerrit-Change-Number: 21178
Gerrit-PatchSet: 6
Gerrit-Owner: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Sat, 26 Aug 2017 10:41:29 +0000
Gerrit-HasComments: Yes
Hello Arthur Heymans, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/21178
to look at the new patch set (#6).
Change subject: sb/intel/bd82x6x: make hotplug map consistent to remapped ports
......................................................................
sb/intel/bd82x6x: make hotplug map consistent to remapped ports
"pcie_port_coalesce" will cause pcie being remapped under certain
conditions, but flags within "pcie_hotplug_map" should be updated
along with ports.
Test on my lenovo t430s.
Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Signed-off-by: Bill XIE <persmule(a)gmail.com>
---
M src/southbridge/intel/bd82x6x/pch.c
1 file changed, 25 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/21178/6
--
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Gerrit-Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Gerrit-Change-Number: 21178
Gerrit-PatchSet: 6
Gerrit-Owner: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Bill XIE has posted comments on this change. ( https://review.coreboot.org/21178 )
Change subject: sb/intel/bd82x6x: make hotplug map consistent to remapped ports
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/21178/5/src/southbridge/intel/bd82x6x/pch.c
File src/southbridge/intel/bd82x6x/pch.c:
https://review.coreboot.org/#/c/21178/5/src/southbridge/intel/bd82x6x/pch.c…
PS5, Line 258: void *chip_info
> No need for `void *` here, just give it the correct type please.
but its original type will break the 80-char-per-line limit.
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Gerrit-Owner: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com>
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Gerrit-Comment-Date: Sat, 26 Aug 2017 10:28:07 +0000
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