coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/pineview: Fix typo in DRAM timing computation
by build bot (Jenkins) (Code Review) 26 Aug '17

26 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21214 ) Change subject: nb/intel/pineview: Fix typo in DRAM timing computation ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59357/ : SUCCESS -- To view, visit https://review.coreboot.org/21214 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd Gerrit-Change-Number: 21214 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 26 Aug 2017 19:33:21 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP, TEST]mb/g41c-gs: Attempt to fix broken SATA (in payload and linux)
by Arthur Heymans (Code Review) 26 Aug '17

26 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21212 ) Change subject: [WIP,TEST]mb/g41c-gs: Attempt to fix broken SATA (in payload and linux) ...................................................................... Patch Set 3: Code-Review-2 Makes things worse, hangs in payload -- To view, visit https://review.coreboot.org/21212 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8067080ce7c3f080ad9ebcbb27086f8a048aff6b Gerrit-Change-Number: 21212 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 26 Aug 2017 19:33:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/pineview: Fix typo in DRAM timing computation
by build bot (Jenkins) (Code Review) 26 Aug '17

26 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21214 ) Change subject: nb/intel/pineview: Fix typo in DRAM timing computation ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/14667/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/59356/ : ABORTED -- To view, visit https://review.coreboot.org/21214 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd Gerrit-Change-Number: 21214 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 26 Aug 2017 19:27:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/pineview: Fix typo in DRAM timing computation
by Arthur Heymans (Code Review) 26 Aug '17

26 Aug '17

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/21214 ) Change subject: nb/intel/pineview: Fix typo in DRAM timing computation ...................................................................... nb/intel/pineview: Fix typo in DRAM timing computation This problem was introduced in 12a4e98c "nb/intel/pineview/raminit: Refactor timings selection" Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/21214/2 -- To view, visit https://review.coreboot.org/21214 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd Gerrit-Change-Number: 21214 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/pineview: Fix typo in DRAM timing computation
by Arthur Heymans (Code Review) 26 Aug '17

26 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21214 Change subject: nb/intel/pineview: Fix typo in DRAM timing computation ...................................................................... nb/intel/pineview: Fix typo in DRAM timing computation Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/21214/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index eae136e..9bb8fd8 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -396,7 +396,7 @@ mult[s->selected_timings.mem_clock])); s->selected_timings.tRRD = MIN(15, DIV_ROUND_UP(maxtrrd, mult[s->selected_timings.mem_clock])); - s->selected_timings.tRTP = MIN(15, DIV_ROUND_UP(maxtras, + s->selected_timings.tRTP = MIN(15, DIV_ROUND_UP(maxtrtp, mult[s->selected_timings.mem_clock])); PRINTK_DEBUG("Selected timings:\n"); -- To view, visit https://review.coreboot.org/21214 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd Gerrit-Change-Number: 21214 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: inteltool: add support for 8 Series/C220 Series Chipset
by build bot (Jenkins) (Code Review) 26 Aug '17

26 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21213 ) Change subject: inteltool: add support for 8 Series/C220 Series Chipset ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14666/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59355/ : SUCCESS -- To view, visit https://review.coreboot.org/21213 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ec155f67c7b6eda47557d00a3d0bcfe4ef98d08 Gerrit-Change-Number: 21213 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 26 Aug 2017 16:52:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: inteltool: add support for 8 Series/C220 Series Chipset
by Iru Cai (Code Review) 26 Aug '17

26 Aug '17

Iru Cai has uploaded this change for review. ( https://review.coreboot.org/21213 Change subject: inteltool: add support for 8 Series/C220 Series Chipset ...................................................................... inteltool: add support for 8 Series/C220 Series Chipset Change-Id: I2ec155f67c7b6eda47557d00a3d0bcfe4ef98d08 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/inteltool/gpio.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/powermgt.c M util/inteltool/rootcmplx.c 5 files changed, 125 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/21213/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 5fd160b..6f21068 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -416,7 +416,42 @@ { 0x64, 0x00000000 }, { 0x68, 0x00000000 }, }; - +/* Default values for Lynx Point desktop chipsets */ +static const gpio_default_t lp_pch_desktop_defaults[] = { + { 0x00, 0xb96ba1ff }, + { 0x04, 0xeeff6eff }, + { 0x0c, 0x02fe0100 }, + { 0x18, 0x00040000 }, + { 0x28, 0x00000000 }, + { 0x2c, 0x00000000 }, + { 0x30, 0x020300ff }, + { 0x34, 0x1f57fff4 }, + { 0x38, 0xa4aa0007 }, + { 0x40, 0x00000130 }, + { 0x44, 0x00000ff0 }, + { 0x48, 0x000000c0 }, + { 0x60, 0x01000000 }, + { 0x64, 0x00000000 }, + { 0x68, 0x00000000 }, +}; +/* Default values for Lynx Point mobile chipsets */ +static const gpio_default_t lp_pch_mobile_defaults[] = { + { 0x00, 0xb96ba1ff }, + { 0x04, 0xeeff6eff }, + { 0x0c, 0x02fe0100 }, + { 0x18, 0x00040000 }, + { 0x28, 0x00000000 }, + { 0x2c, 0x00000000 }, + { 0x30, 0x020300fe }, + { 0x34, 0x1f57fff4 }, + { 0x38, 0xa4aa0007 }, + { 0x40, 0x00000030 }, + { 0x44, 0x00000ff0 }, + { 0x48, 0x000000c0 }, + { 0x60, 0x01000000 }, + { 0x64, 0x00000000 }, + { 0x68, 0x00000000 }, +}; /* Baytrail */ static const io_register_t baytrail_score_ssus_gpio_registers[] = { { 0x00, 4, "SC_USE_SEL_31_0_" }, @@ -940,6 +975,33 @@ gpio_defaults = pp_pch_mobile_defaults; defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults); break; + case PCI_DEVICE_ID_INTEL_LYNXPOINT_DESKTOP_FULL: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: + gpiobase = pci_read_word(sb, 0x48) & 0xff80; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = lp_pch_desktop_defaults; + defaults_size = ARRAY_SIZE(ip_pch_desktop_defaults); + break; + case PCI_DEVICE_ID_INTEL_LYNXPOINT_MOBILE_FULL: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_QM87: + gpiobase = pci_read_word(sb, 0x48) & 0xff80; + gpio_registers = pch_gpio_registers; + size = ARRAY_SIZE(pch_gpio_registers); + gpio_defaults = lp_pch_mobile_defaults; + defaults_size = ARRAY_SIZE(ip_pch_desktop_defaults); + break; case PCI_DEVICE_ID_INTEL_ICH10: case PCI_DEVICE_ID_INTEL_ICH10R: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index f873590..6ccd877 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -182,6 +182,23 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B75, "B75" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H77, "H77" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C216, "C216" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_MOBILE_FULL, + "Lynx Point Mobile Full Featured Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_DESKTOP_FULL, + "Lynx Point Desktop Full Featured Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z87, "Z87" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z85, "Z85" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM86, "HM86" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H87, "H87" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM87, "HM87" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q85, "Q85" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q87, "Q87" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM87, "QM87" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B85, "B85" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C222, "C222" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224, "C224" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226, "C226" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81, "H81" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM77, "QM77" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QS77, "QS77" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM77, "HM77" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index d4aa96f..ab7e358 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -133,6 +133,21 @@ #define PCI_DEVICE_ID_INTEL_HM75 0x1e5d #define PCI_DEVICE_ID_INTEL_HM70 0x1e5e #define PCI_DEVICE_ID_INTEL_NM70 0x1e5f +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_MOBILE_FULL 0x8c41 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_DESKTOP_FULL 0x8c42 +#define PCI_DEVICE_ID_INTEL_Z87 0x8c44 +#define PCI_DEVICE_ID_INTEL_Z85 0x8c46 +#define PCI_DEVICE_ID_INTEL_HM86 0x8c49 +#define PCI_DEVICE_ID_INTEL_H87 0x8c4a +#define PCI_DEVICE_ID_INTEL_HM87 0x8c4b +#define PCI_DEVICE_ID_INTEL_Q85 0x8c4c +#define PCI_DEVICE_ID_INTEL_Q87 0x8c4e +#define PCI_DEVICE_ID_INTEL_QM87 0x8c4f +#define PCI_DEVICE_ID_INTEL_B85 0x8c50 +#define PCI_DEVICE_ID_INTEL_C222 0x8c52 +#define PCI_DEVICE_ID_INTEL_C224 0x8c54 +#define PCI_DEVICE_ID_INTEL_C226 0x8c56 +#define PCI_DEVICE_ID_INTEL_H81 0x8c5c #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index f022904..871f64c 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -724,6 +724,21 @@ case PCI_DEVICE_ID_INTEL_HM76: case PCI_DEVICE_ID_INTEL_HM75: case PCI_DEVICE_ID_INTEL_HM70: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_MOBILE_FULL: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_DESKTOP_FULL: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_QM87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 2ad3410..7583c21 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -92,6 +92,21 @@ case PCI_DEVICE_ID_INTEL_HM75: case PCI_DEVICE_ID_INTEL_HM70: case PCI_DEVICE_ID_INTEL_NM70: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_MOBILE_FULL: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_DESKTOP_FULL: + case PCI_DEVICE_ID_INTEL_Z87: + case PCI_DEVICE_ID_INTEL_Z85: + case PCI_DEVICE_ID_INTEL_HM86: + case PCI_DEVICE_ID_INTEL_H87: + case PCI_DEVICE_ID_INTEL_HM87: + case PCI_DEVICE_ID_INTEL_Q85: + case PCI_DEVICE_ID_INTEL_Q87: + case PCI_DEVICE_ID_INTEL_QM87: + case PCI_DEVICE_ID_INTEL_B85: + case PCI_DEVICE_ID_INTEL_C222: + case PCI_DEVICE_ID_INTEL_C224: + case PCI_DEVICE_ID_INTEL_C226: + case PCI_DEVICE_ID_INTEL_H81: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: -- To view, visit https://review.coreboot.org/21213 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2ec155f67c7b6eda47557d00a3d0bcfe4ef98d08 Gerrit-Change-Number: 21213 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com>

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Change in coreboot[master]: drivers/intel/fsp2_0: Link Post PCI enumeration Notify with BS_DEV_EN...
by build bot (Jenkins) (Code Review) 26 Aug '17

26 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21084 ) Change subject: drivers/intel/fsp2_0: Link Post PCI enumeration Notify with BS_DEV_ENABLE ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14665/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59354/ : SUCCESS -- To view, visit https://review.coreboot.org/21084 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4cb4eac5256c1ce98f51adad0be6e69f7d05d8e1 Gerrit-Change-Number: 21084 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Sat, 26 Aug 2017 14:10:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Move SPI lock down config after resource allocation
by build bot (Jenkins) (Code Review) 26 Aug '17

26 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21064 ) Change subject: soc/intel/skylake: Move SPI lock down config after resource allocation ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14664/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59353/ : SUCCESS -- To view, visit https://review.coreboot.org/21064 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5 Gerrit-Change-Number: 21064 Gerrit-PatchSet: 9 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 26 Aug 2017 14:08:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP, TEST]mb/g41c-gs: Attempt to fix broken SATA (in payload and linux)
by build bot (Jenkins) (Code Review) 26 Aug '17

26 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21212 ) Change subject: [WIP,TEST]mb/g41c-gs: Attempt to fix broken SATA (in payload and linux) ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14661/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59350/ : SUCCESS -- To view, visit https://review.coreboot.org/21212 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8067080ce7c3f080ad9ebcbb27086f8a048aff6b Gerrit-Change-Number: 21212 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 26 Aug 2017 14:05:22 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017