coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/common/uart: Add support for enabling UART debug controller...
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20835 ) Change subject: soc/intel/common/uart: Add support for enabling UART debug controller on resume ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58236/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13654/ : SUCCESS -- To view, visit https://review.coreboot.org/20835 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 Gerrit-Change-Number: 20835 Gerrit-PatchSet: 10 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 18:59:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Enable UART debug controller on S3 resume
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20888 ) Change subject: soc/intel/apollolake: Enable UART debug controller on S3 resume ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58238/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13656/ : SUCCESS -- To view, visit https://review.coreboot.org/20888 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171 Gerrit-Change-Number: 20888 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 18:48:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable UART debug controller on S3 resume
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20886 ) Change subject: soc/intel/skylake: Enable UART debug controller on S3 resume ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58237/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13655/ : SUCCESS -- To view, visit https://review.coreboot.org/20886 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Gerrit-Change-Number: 20886 Gerrit-PatchSet: 5 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 18:45:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/lpss: Add lpss_is_controller_in_reset
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20885 ) Change subject: soc/intel/common/lpss: Add lpss_is_controller_in_reset ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58235/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13653/ : SUCCESS -- To view, visit https://review.coreboot.org/20885 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461 Gerrit-Change-Number: 20885 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 18:43:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/uart: Refactor uart_common_init
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20884 ) Change subject: soc/intel/common/uart: Refactor uart_common_init ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58234/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13652/ : SUCCESS -- To view, visit https://review.coreboot.org/20884 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a Gerrit-Change-Number: 20884 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 18:43:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Enable UART debug controller on S3 resume
by Furquan Shaikh (Code Review) 05 Aug '17

05 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20888 Change subject: soc/intel/apollolake: Enable UART debug controller on S3 resume ...................................................................... soc/intel/apollolake: Enable UART debug controller on S3 resume 1. Add a new variable to GNVS to store information during S3 suspend whether UART debug controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helper functions required by intel/common UARRT driver for enabling controller on S3 resume. BUG=b:64030366 Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/acpi/globalnvs.asl M src/soc/intel/apollolake/include/soc/nvs.h M src/soc/intel/apollolake/uart.c M src/soc/intel/common/block/smm/smihandler.c 5 files changed, 36 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/20888/1 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 07bbdcd..589b846 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -42,6 +42,7 @@ smm-y += smihandler.c smm-y += spi.c smm-y += uart_early.c +smm-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 1548c30..6431fae 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -41,6 +41,8 @@ PRT0, 32, // 0x25 - 0x28 - PERST_0 Address SCDP, 8, // 0x29 - SD_CD GPIO portid SCDO, 8, // 0x2A - GPIO pad offset relative to the community + UIOR, 8, // 0x2B - UART debug controller init on S3 resume + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 56085b2..9a09800 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -42,7 +42,9 @@ uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */ - uint8_t unused[213]; + uint8_t uior; /* 0x2B - UART debug controller init on S3 + resume */ + uint8_t unused[212]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 3db460a..14dc5f1 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -20,20 +20,44 @@ * shouldn't cause any fragmentation. */ +#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <intelblocks/uart.h> +#include <soc/nvs.h> #include <soc/pci_devs.h> +bool pch_uart_is_debug_controller(struct device *dev) +{ + return dev->path.pci.devfn == _PCH_DEVFN(UART, + CONFIG_UART_FOR_CONSOLE); +} + +#if ENV_RAMSTAGE void pch_uart_read_resources(struct device *dev) { pci_dev_read_resources(dev); - if ((IS_ENABLED(CONFIG_SOC_UART_DEBUG) && - dev->path.pci.devfn == _PCH_DEVFN(UART, - CONFIG_UART_FOR_CONSOLE))) { + if (IS_ENABLED(CONFIG_SOC_UART_DEBUG) && + pch_uart_is_debug_controller(dev)) { /* will override existing resource. */ fixed_mem_resource(dev, PCI_BASE_ADDRESS_0, CONFIG_CONSOLE_UART_BASE_ADDRESS >> 10, 4, 0); } } +#endif + +bool pch_uart_init_debug_controller_on_resume(void) +{ + global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) + return !!gnvs->uior; + + return false; +} + +device_t pch_uart_get_debug_controller(void) +{ + return _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE); +} diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index b620ff9..dde9b1f 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <elog.h> #include <intelblocks/smihandler.h> +#include <intelblocks/uart.h> #include <soc/nvs.h> #include <soc/pm.h> #include <soc/gpio.h> @@ -160,6 +161,8 @@ case ACPI_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + gnvs->uior = uart_debug_controller_is_initialized(); + /* Invalidate the cache before going to S3 */ wbinvd(); break; -- To view, visit https://review.coreboot.org/20888 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171 Gerrit-Change-Number: 20888 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20887 ) Change subject: mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58233/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13651/ : SUCCESS -- To view, visit https://review.coreboot.org/20887 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I218fd48c8e29563ef089d60ebde7bc36ac8ab189 Gerrit-Change-Number: 20887 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 17:35:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2
by Nico Huber (Code Review) 05 Aug '17

05 Aug '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/20887 Change subject: mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2 ...................................................................... mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2 Change-Id: I218fd48c8e29563ef089d60ebde7bc36ac8ab189 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc A src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex 3 files changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/20887/1 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index a07df70..458b862 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -109,7 +109,7 @@ */ /* we only support elpida. Because the spd data is missing */ - if (spd_index != 0) + if (spd_index != 0 && spd_index != 2) die("Unsupported Memory. Please add your SPD dump to coreboot."); memory = get_spd_data(spd_index); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc index d1cca03..ec6e4f3 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc @@ -16,6 +16,8 @@ SPD_BIN = $(obj)/spd.bin SPD_SOURCES = elpida.hex # 0b0000 Single Channel 2GB +SPD_SOURCES = samsung.hex # 0b0001 placeholder +SPD_SOURCES = samsung.hex # 0b0010 4GiB SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f)) # Include spd ROM data diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex b/src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex new file mode 100644 index 0000000..2418636 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex @@ -0,0 +1,16 @@ +92 11 0b 03 04 00 00 0a 03 52 01 08 0c 00 20 00 +6c 78 6c 3c 6c 11 20 81 28 08 3c 3c 01 68 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 65 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 75 c6 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/20887 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I218fd48c8e29563ef089d60ebde7bc36ac8ab189 Gerrit-Change-Number: 20887 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/intel/skylake: Enable UART debug controller on S3 resume
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20886 ) Change subject: soc/intel/skylake: Enable UART debug controller on S3 resume ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58232/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13650/ : SUCCESS -- To view, visit https://review.coreboot.org/20886 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Gerrit-Change-Number: 20886 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 03:49:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable UART debug controller on S3 resume
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20886 ) Change subject: soc/intel/skylake: Enable UART debug controller on S3 resume ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58231/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13649/ : SUCCESS -- To view, visit https://review.coreboot.org/20886 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Gerrit-Change-Number: 20886 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 03:41:26 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017