coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/common/uart: Add support for enabling UART debug controller...
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20835 ) Change subject: soc/intel/common/uart: Add support for enabling UART debug controller on resume ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58230/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13648/ : SUCCESS -- To view, visit https://review.coreboot.org/20835 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 Gerrit-Change-Number: 20835 Gerrit-PatchSet: 9 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 03:41:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable UART debug controller on S3 resume
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20886 ) Change subject: soc/intel/skylake: Enable UART debug controller on S3 resume ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58229/ : SUCCESS -- To view, visit https://review.coreboot.org/20886 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Gerrit-Change-Number: 20886 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 02:01:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/lpss: Add lpss_is_controller_in_reset
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20885 ) Change subject: soc/intel/common/lpss: Add lpss_is_controller_in_reset ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58226/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13645/ : SUCCESS -- To view, visit https://review.coreboot.org/20885 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461 Gerrit-Change-Number: 20885 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 01:58:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/uart: Refactor uart_common_init
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20884 ) Change subject: soc/intel/common/uart: Refactor uart_common_init ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58227/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13646/ : SUCCESS -- To view, visit https://review.coreboot.org/20884 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a Gerrit-Change-Number: 20884 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 01:54:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/uart: Add support for enabling UART debug controller...
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20835 ) Change subject: soc/intel/common/uart: Add support for enabling UART debug controller on resume ...................................................................... Patch Set 8: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58225/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13644/ : SUCCESS -- To view, visit https://review.coreboot.org/20835 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 Gerrit-Change-Number: 20835 Gerrit-PatchSet: 8 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 01:50:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable UART debug controller on S3 resume
by Furquan Shaikh (Code Review) 05 Aug '17

05 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20886 to look at the new patch set (#2). Change subject: soc/intel/skylake: Enable UART debug controller on S3 resume ...................................................................... soc/intel/skylake: Enable UART debug controller on S3 resume 1. Add a new variable to GNVS to store information during S3 suspend whether UART debug port controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helpers functions required by intel/common UART driver for enabling controller on S3 resume. BUG=b:64030366 TEST=Verified behavior with different combinations: 1. Serial console enabled in coreboot: No change in behavior. 2. Serial console enabled only in kernel: coreboot initializes debug controller on S3 resume. 3. Serial console not enabled in coreboot and kernel: coreboot skips initialization of debug controller on S3 resume. Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/uart.c 5 files changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/20886/2 -- To view, visit https://review.coreboot.org/20886 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Gerrit-Change-Number: 20886 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Enable UART debug controller on S3 resume
by build bot (Jenkins) (Code Review) 05 Aug '17

05 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20886 ) Change subject: soc/intel/skylake: Enable UART debug controller on S3 resume ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58228/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/13647/ : SUCCESS -- To view, visit https://review.coreboot.org/20886 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Gerrit-Change-Number: 20886 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 05 Aug 2017 01:40:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable UART debug controller on S3 resume
by Furquan Shaikh (Code Review) 05 Aug '17

05 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20886 Change subject: soc/intel/skylake: Enable UART debug controller on S3 resume ...................................................................... soc/intel/skylake: Enable UART debug controller on S3 resume 1. Add a new variable to GNVS to store information during S3 suspend whether UART debug port controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helpers functions required by intel/common UART driver for enabling controller on S3 resume. BUG=b:64030366 TEST=Verified behavior with different combinations: 1. Serial console enabled in coreboot: No change in behavior. 2. Serial console enabled only in kernel: Coreboot initializes debug controller on S3 resume. 3. Serial console not enabled in coreboot and kernel: Coreboot skips initialization of debug controller on S3 resume. Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c --- M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/smihandler.c M src/soc/intel/skylake/uart.c 5 files changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/20886/1 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 7f618d4..baf6f01 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -76,6 +76,7 @@ smm-y += smihandler.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c smm-$(CONFIG_UART_DEBUG) += uart_debug.c +smm-y += uart.c postcar-y += memmap.c postcar-$(CONFIG_UART_DEBUG) += uart_debug.c diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index d06269f..8a7606c 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -66,6 +66,7 @@ CID1, 16, // 0x3d - Wifi Country Identifier U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap + UIOR, 8, // 0x42 - UART debug controller init on S3 resume /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 4ca3d22..8272336 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -57,7 +57,8 @@ u16 cid1; /* 0x3d - Wifi Country Identifier */ u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */ u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */ - u8 unused[190]; + u8 uior; /* 0x42 - UART debug controller init on S3 resume */ + u8 unused[189]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index c4c4a7b..d87994e 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -24,6 +24,7 @@ #include <elog.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> +#include <intelblocks/uart.h> #include <delay.h> #include <device/pci_def.h> #include <elog.h> @@ -165,6 +166,8 @@ case ACPI_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + gnvs->uior = uart_debug_controller_is_initialized(); + /* Invalidate the cache before going to S3 */ wbinvd(); break; diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 07326d5..f254400 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -14,16 +14,19 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <device/pci.h> #include <intelblocks/uart.h> #include <soc/iomap.h> +#include <soc/nvs.h> #include <soc/pci_devs.h> -static int pch_uart_is_debug(struct device *dev) +bool pch_uart_is_debug(struct device *dev) { return dev->path.pci.devfn == PCH_DEVFN_UART2; } +#if ENV_RAMSTAGE void pch_uart_read_resources(struct device *dev) { pci_dev_read_resources(dev); @@ -38,3 +41,19 @@ IORESOURCE_FIXED; } } +#endif + +bool pch_uart_init_debug_controller_on_resume(void) +{ + global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) + return !!gnvs->uior; + + return false; +} + +device_t pch_uart_get_debug_controller(void) +{ + return PCH_DEV_UART2; +} -- To view, visit https://review.coreboot.org/20886 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Gerrit-Change-Number: 20886 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/common/lpss: Add lpss_is_controller_in_reset
by Furquan Shaikh (Code Review) 05 Aug '17

05 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20885 Change subject: soc/intel/common/lpss: Add lpss_is_controller_in_reset ...................................................................... soc/intel/common/lpss: Add lpss_is_controller_in_reset Add new API function lpss_is_controller_in_reset that returns whether the LPSS controller is in reset. Also, add lpss.c to smm stage so that lpss_is_controller_in_reset can be used in smihandler. BUG=b:64030366 Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/lpss/Makefile.inc M src/soc/intel/common/block/lpss/lpss.c 3 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/20885/1 diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h index 03a4714..138340d 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpss.h +++ b/src/soc/intel/common/block/include/intelblocks/lpss.h @@ -27,4 +27,7 @@ */ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); +/* Check if controller is in reset. */ +bool lpss_is_controller_in_reset(uintptr_t base); + #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ diff --git a/src/soc/intel/common/block/lpss/Makefile.inc b/src/soc/intel/common/block/lpss/Makefile.inc index 50d1c10..6ed654f 100644 --- a/src/soc/intel/common/block/lpss/Makefile.inc +++ b/src/soc/intel/common/block/lpss/Makefile.inc @@ -2,3 +2,4 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c index 146fdab..feacef3 100644 --- a/src/soc/intel/common/block/lpss/lpss.c +++ b/src/soc/intel/common/block/lpss/lpss.c @@ -39,6 +39,17 @@ /* DMA Software Reset Control */ #define LPSS_DMA_RST_RELEASE (1 << 2) +bool lpss_is_controller_in_reset(uintptr_t base) +{ + uint8_t *addr = (void *)base; + uint32_t val = read32(addr + LPSS_RESET_CTL_REG); + + if (val == 0xFFFFFFFF) + return true; + + return !(val & LPSS_CNT_RST_RELEASE); +} + void lpss_reset_release(uintptr_t base) { uint8_t *addr = (void *)base; -- To view, visit https://review.coreboot.org/20885 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461 Gerrit-Change-Number: 20885 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/common/uart: Refactor uart_common_init
by Furquan Shaikh (Code Review) 05 Aug '17

05 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20884 Change subject: soc/intel/common/uart: Refactor uart_common_init ...................................................................... soc/intel/common/uart: Refactor uart_common_init 1. Create a new function uart_lpss_init which takes the UART LPSS controller out of reset and initializes and enables clock. 2. Instead of passing in m/n clock divider values as parameters to uart_common_init, introduce Kconfig variables so that uart_lpss_init can use the values directly without having to query the SoC. BUG=b:64030366 TEST=Verified that UART still works on APL and KBL boards. Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/uart.h M src/soc/intel/apollolake/uart_early.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/Kconfig M src/soc/intel/common/block/uart/uart.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/bootblock/uart.c 8 files changed, 51 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/20884/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 2d8838a..ba311f5 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -350,4 +350,14 @@ Limits (RAPL) algorithm for a constant power management. Set this config option to skip the RAPL configuration. +# M and N divisor values for clock frequency configuration. +# These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x25a + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0x7fff + endif diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h index b2b1bb8..bf8b9d7 100644 --- a/src/soc/intel/apollolake/include/soc/uart.h +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -18,13 +18,6 @@ #ifndef _SOC_APOLLOLAKE_UART_H_ #define _SOC_APOLLOLAKE_UART_H_ -/* -* M and N divisor values for clock frequency configuration. -* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) -*/ -#define CLK_M_VAL 0x025a -#define CLK_N_VAL 0x7fff - /* Initialize the console UART including the pads for the configured UART. */ void pch_uart_init(void); diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index 4c143ad..d3c1b0d 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -69,6 +69,6 @@ gpio_configure_pads(&uart_gpios[pad_index * 2], 2); /* Program UART2 BAR0, command, reset and clock register */ - uart_common_init(uart, base, CLK_M_VAL, CLK_N_VAL); + uart_common_init(uart, base); } diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index b46edd7..9ec5004 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -19,8 +19,12 @@ #include <arch/io.h> #include <device/device.h> -void uart_common_init(device_t dev, uintptr_t baseaddr, - uint32_t clk_m_val, uint32_t clk_n_val); +/* + * Common routine to initialize UART controller PCI config space, take it out of + * reset and configure M/N dividers. + */ +void uart_common_init(device_t dev, uintptr_t baseaddr); + void pch_uart_read_resources(struct device *dev); diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig index 103659f..f4a0e4e 100644 --- a/src/soc/intel/common/block/uart/Kconfig +++ b/src/soc/intel/common/block/uart/Kconfig @@ -3,3 +3,15 @@ select SOC_INTEL_COMMON_BLOCK_LPSS help Intel Processor common UART support + +config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL + depends on SOC_INTEL_COMMON_BLOCK_UART + hex + help + Clock m-divisor value for m/n divider + +config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL + depends on SOC_INTEL_COMMON_BLOCK_UART + hex + help + Clock m-divisor value for m/n divider diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index e8f1bc8..be30464 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -19,8 +19,17 @@ #include <intelblocks/lpss.h> #include <intelblocks/uart.h> -void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val, - uint32_t clk_n_val) +static void uart_lpss_init(uintptr_t baseaddr) +{ + /* Take UART out of reset */ + lpss_reset_release(baseaddr); + + /* Set M and N divisor inputs and enable clock */ + lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL, + CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); +} + +void uart_common_init(device_t dev, uintptr_t baseaddr) { /* Set UART base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); @@ -29,11 +38,8 @@ pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - /* Take UART out of reset */ - lpss_reset_release(baseaddr); + uart_lpss_init(baseaddr); - /* Set M and N divisor inputs and enable clock */ - lpss_clk_update(baseaddr, clk_m_val, clk_n_val); } #if ENV_RAMSTAGE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 32c2654..f0402a9 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -317,4 +317,13 @@ int default 100 +# Clock divider parameters for 115200 baud rate +config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL + hex + default 0x30 + +config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL + hex + default 0xc35 + endif diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c index 26b81c0..b7ab241 100644 --- a/src/soc/intel/skylake/bootblock/uart.c +++ b/src/soc/intel/skylake/bootblock/uart.c @@ -31,10 +31,6 @@ #define PCR_SIO_PCH_LEGACY_UART1 (1 << 1) #define PCR_SIO_PCH_LEGACY_UART2 (1 << 2) -/* Clock divider parameters for 115200 baud rate */ -#define CLK_M_VAL 0x30 -#define CLK_N_VAL 0xc35 - /* UART2 pad configuration. Support RXD and TXD for now. */ static const struct pad_config uart2_pads[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), @@ -45,7 +41,7 @@ { uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - uart_common_init(PCH_DEV_UART2, base, CLK_M_VAL, CLK_N_VAL); + uart_common_init(PCH_DEV_UART2, base); /* Put UART2 in byte access mode for 16550 compatibility */ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) -- To view, visit https://review.coreboot.org/20884 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a Gerrit-Change-Number: 20884 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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coreboot-gerrit August 2017