coreboot-gerrit August 2017

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Change in coreboot[master]: [WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Nico Huber (Code Review) 08 Aug '17

08 Aug '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/20913 ) Change subject: [WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/20913/1/src/mainboard/lenovo/x200/acpi/bat_… File src/mainboard/lenovo/x200/acpi/bat_thresh.asl: PS1: I think we agreed to keep the tree consistent in the old syntax for the moment. https://review.coreboot.org/#/c/20913/1/src/mainboard/lenovo/x200/acpi/bat_… PS1, Line 32: 1 Why not place them below BAT0/BAT1? instead of numbering the methods? (not to mention that it's weird to have a different numbering, 1 based here, 0 based there) -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 08 Aug 2017 19:09:55 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add ramstage SystemAgent support
by Lijian Zhao (Code Review) 08 Aug '17

08 Aug '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20914 Change subject: soc/intel/cannonlake: Add ramstage SystemAgent support ...................................................................... soc/intel/cannonlake: Add ramstage SystemAgent support Revered memory resource within SA, also perform necessary routine for initialization during ramstage. Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/systemagent.c 2 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/20914/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 537a973..37434bc 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -19,6 +19,7 @@ ramstage-y += cbmem.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += systemagent.c ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20 diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c new file mode 100644 index 0000000..d006fb5 --- /dev/null +++ b/src/soc/intel/cannonlake/systemagent.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <intelblocks/systemagent.h> +#include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/systemagent.h> + +/* + * SoC implementation + * + * Add all known fixed memory ranges for Host Controller/Mmeory + * controller. + */ +void soc_add_fixed_mmio_resources(struct device *dev, int *index) +{ + static const struct sa_mmio_descriptor soc_fixed_resources[] = { + { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, + "PCIEXBAR" }, + { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" }, + { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" }, + { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" }, + { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" }, + { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, + }; + + sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, + ARRAY_SIZE(soc_fixed_resources)); +} + +/* + * SoC implementation + * + * Perform System Agent Initialization during Ramstage phase. + */ +void soc_systemagent_init(struct device *dev) +{ + /* Enable Power Aware Interrupt Routing */ + enable_power_aware_intr(); + + /* Enable BIOS Reset CPL */ + enable_bios_reset_cpl(); +} + -- To view, visit https://review.coreboot.org/20914 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb Gerrit-Change-Number: 20914 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: [WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Arthur Heymans (Code Review) 08 Aug '17

08 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20913 ) Change subject: [WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... Patch Set 1: Seems to work fine with acpi_call module. -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 08 Aug 2017 18:50:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Arthur Heymans (Code Review) 08 Aug '17

08 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20913 Change subject: [WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... [WIP]mb/lenovo/x200: Add ACPI methods to set battery thresholds Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/lenovo/x200/acpi/bat_thresh.asl M src/mainboard/lenovo/x200/dsdt.asl 2 files changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/20913/1 diff --git a/src/mainboard/lenovo/x200/acpi/bat_thresh.asl b/src/mainboard/lenovo/x200/acpi/bat_thresh.asl new file mode 100644 index 0000000..6a30008 --- /dev/null +++ b/src/mainboard/lenovo/x200/acpi/bat_thresh.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x03), + , 2, + BSTP, 1, /* Battery start/stop threshold */ + Offset (0x24), + TSH1, 8, /* Battery1 threshold */ + Offset (0x25), + TSH2, 8 /* Battery2 threshold */ + } + + /* Set upper threshold on battery1 */ + Method (SUT1, 1, NotSerialized) + { + BSTP = 1 + Local0 = Arg0 | 0x80 + TSH1 = Local0 + } + /* Set lower threshold on battery1 */ + Method (SLT1, 1, NotSerialized) + { + BSTP = 0 + Local0 = Arg0 | 0x80 + TSH1 = Local0 + } + + Method (SUT2, 1, NotSerialized) + { + BSTP = 1 + Local0 = Arg0 | 0x80 + TSH2 = Local0 + } + + Method (SLT2, 1, NotSerialized) + { + BSTP = 0 + Local0 = Arg0 | 0x80 + TSH2 = Local0 + } +} \ No newline at end of file diff --git a/src/mainboard/lenovo/x200/dsdt.asl b/src/mainboard/lenovo/x200/dsdt.asl index 0706249..5705033 100644 --- a/src/mainboard/lenovo/x200/dsdt.asl +++ b/src/mainboard/lenovo/x200/dsdt.asl @@ -56,4 +56,5 @@ /* Dock support code */ #include "acpi/dock.asl" + #include "acpi/bat_thresh.asl" } -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add Kconfig option for fuses
by Patrick Rudolph (Code Review) 08 Aug '17

08 Aug '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/20907 ) Change subject: nb/intel/sandybridge/raminit: Add Kconfig option for fuses ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/20907/1/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_common.c: https://review.coreboot.org/#/c/20907/1/src/northbridge/intel/sandybridge/r… PS1, Line 406: TCK_1333MHZ > Is faster than both ivy and sandy can run but that's not an issue I suppose Ivybridge supports this frequency, but there's no board in tree that does. At the end the value here doesn't matter, but I don't want to return 0... https://review.coreboot.org/#/c/20907/1/src/northbridge/intel/sandybridge/r… PS1, Line 443: if (cfg->max_mem_clock_mhz >= 1066) : return TCK_1066MHZ; > unrelated but should be adapted for ivy bridge since that one can run faste Yes, at the moment only 666mhz and 933mhz is being used. As this commit removes 933 I don't care that much. -- To view, visit https://review.coreboot.org/20907 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Gerrit-Change-Number: 20907 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 18:07:01 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add LPC Common code and use it for APL
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20659 ) Change subject: soc/intel/common/block: Add LPC Common code and use it for APL ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58313/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13724/ : SUCCESS -- To view, visit https://review.coreboot.org/20659 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a Gerrit-Change-Number: 20659 Gerrit-PatchSet: 10 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 16:40:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: stoneyridge: Rename hudson to southbridge
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20912 ) Change subject: stoneyridge: Rename hudson to southbridge ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58311/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13722/ : SUCCESS -- To view, visit https://review.coreboot.org/20912 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Gerrit-Change-Number: 20912 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 16:12:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Set eMMC slot
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20911 ) Change subject: google/kahlee: Set eMMC slot ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58312/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13723/ : SUCCESS -- To view, visit https://review.coreboot.org/20911 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16 Gerrit-Change-Number: 20911 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 16:09:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Set eMMC slot
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20911 ) Change subject: google/kahlee: Set eMMC slot ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58310/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13721/ : SUCCESS -- To view, visit https://review.coreboot.org/20911 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16 Gerrit-Change-Number: 20911 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 15:56:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: stoneyridge: Fix CPU ASL \_PR table
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20910 ) Change subject: stoneyridge: Fix CPU ASL \_PR table ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58309/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13720/ : SUCCESS -- To view, visit https://review.coreboot.org/20910 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f Gerrit-Change-Number: 20910 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 15:52:35 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017