coreboot-gerrit August 2017

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Change in coreboot[master]: stoneyridge: Rename hudson to southbridge
by Marc Jones (Code Review) 08 Aug '17

08 Aug '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/20912 Change subject: stoneyridge: Rename hudson to southbridge ...................................................................... stoneyridge: Rename hudson to southbridge Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/google/kahlee/BiosCallOuts.c M src/mainboard/google/kahlee/bootblock/BiosCallOuts.c M src/mainboard/google/kahlee/bootblock/bootblock.c M src/mainboard/google/kahlee/ec.c M src/mainboard/google/kahlee/gpio.c M src/mainboard/google/kahlee/mptable.c M src/soc/amd/common/def_callouts.c M src/soc/amd/common/dimmSpd.h M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/acpi/fch.asl M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/dimmSpd.c M src/soc/amd/stoneyridge/early_setup.c M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/hda.c M src/soc/amd/stoneyridge/include/soc/smi.h R src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/reset.c M src/soc/amd/stoneyridge/romstage.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/amd/stoneyridge/smi.c M src/soc/amd/stoneyridge/smi_util.c M src/soc/amd/stoneyridge/smihandler.c R src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/uart.c M src/soc/amd/stoneyridge/usb.c 34 files changed, 111 insertions(+), 115 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/20912/1 diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index fd03f4e..31681cb 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -17,7 +17,7 @@ #include <BiosCallOuts.h> #include <FchPlatform.h> #include <soc/imc.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <stdlib.h> static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c index a54078a..b0a3e23 100644 --- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c @@ -16,7 +16,7 @@ #include <AGESA.h> #include <BiosCallOuts.h> #include <FchPlatform.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <stdlib.h> static const GPIO_CONTROL oem_gardenia_gpio[] = { @@ -53,8 +53,8 @@ FCH_RESET_DATA_BLOCK *FchParams_reset; FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - FchParams_reset->FchReset.SataEnable = hudson_sata_enable(); - FchParams_reset->FchReset.IdeEnable = hudson_ide_enable(); + FchParams_reset->FchReset.SataEnable = sb_sata_enable(); + FchParams_reset->FchReset.IdeEnable = sb_ide_enable(); FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio; printk(BIOS_DEBUG, "Done\n"); } diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c index f32b8da..c329558 100644 --- a/src/mainboard/amd/gardenia/mptable.c +++ b/src/mainboard/amd/gardenia/mptable.c @@ -23,7 +23,7 @@ #include <cpu/amd/amdfam15.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <amd_pci_util.h> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index 7bef2f3..b32a984 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -16,7 +16,7 @@ #include <AGESA.h> #include <BiosCallOuts.h> #include <FchPlatform.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <stdlib.h> extern const GPIO_CONTROL oem_kahlee_gpio[]; diff --git a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c index b70db1d..162fc50 100644 --- a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c @@ -16,7 +16,7 @@ #include <AGESA.h> #include <BiosCallOuts.h> #include <FchPlatform.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <stdlib.h> extern const GPIO_CONTROL oem_kahlee_gpio[]; @@ -29,8 +29,8 @@ FCH_RESET_DATA_BLOCK *FchParams_reset; FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - FchParams_reset->FchReset.SataEnable = hudson_sata_enable(); - FchParams_reset->FchReset.IdeEnable = hudson_ide_enable(); + FchParams_reset->FchReset.SataEnable = sb_sata_enable(); + FchParams_reset->FchReset.IdeEnable = sb_ide_enable(); FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio; printk(BIOS_DEBUG, "Done\n"); } diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index caa24d5..3041a8f 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -15,7 +15,7 @@ #include <bootblock_common.h> #include <ec.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> void bootblock_mainboard_init(void) { @@ -23,5 +23,5 @@ mainboard_ec_init(); /* Setup TPM decode before verstage */ - hudson_tpm_decode_spi(); + sb_tpm_decode_spi(); } diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index 71c6e10..75ed1fa 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -18,7 +18,7 @@ #include <ec/google/chromeec/ec.h> #include "ec.h" #include <rules.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> static void ramstage_ec_init(void) { diff --git a/src/mainboard/google/kahlee/gpio.c b/src/mainboard/google/kahlee/gpio.c index 56a5e3d..b815ac3 100644 --- a/src/mainboard/google/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/gpio.c @@ -15,7 +15,7 @@ #include <AGESA.h> #include <FchPlatform.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <stdlib.h> const GPIO_CONTROL oem_kahlee_gpio[] = { diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c index f32b8da..c329558 100644 --- a/src/mainboard/google/kahlee/mptable.c +++ b/src/mainboard/google/kahlee/mptable.c @@ -23,7 +23,7 @@ #include <cpu/amd/amdfam15.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <amd_pci_util.h> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/def_callouts.c index f923b13..fda0013 100644 --- a/src/soc/amd/common/def_callouts.c +++ b/src/soc/amd/common/def_callouts.c @@ -23,7 +23,7 @@ #include <agesawrapper.h> #include <BiosCallOuts.h> #include <dimmSpd.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr) { diff --git a/src/soc/amd/common/dimmSpd.h b/src/soc/amd/common/dimmSpd.h index ea7a7e9..75a7990 100644 --- a/src/soc/amd/common/dimmSpd.h +++ b/src/soc/amd/common/dimmSpd.h @@ -20,7 +20,7 @@ AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData); -int hudson_readSpd(int spdAddress, char *buf, size_t len); +int sb_readSpd(int spdAddress, char *buf, size_t len); int smbus_readSpd(int spdAddress, char *buf, size_t len); #endif diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 30006b3..8fa5afb 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -66,7 +66,7 @@ ramstage-y += fixme.c ramstage-y += gpio.c ramstage-y += hda.c -ramstage-y += hudson.c +ramstage-y += southbridge.c ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c ramstage-y += lpc.c ramstage-y += model_15_init.c diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 327faef..adf906b 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -28,7 +28,7 @@ #include <device/device.h> #include <device/pci.h> #include <soc/acpi.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <soc/nvs.h> #include <soc/smi.h> @@ -85,7 +85,7 @@ fadt->dsdt = (u32) dsdt; fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; - fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ + fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; @@ -112,7 +112,7 @@ fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */ + fadt->gpe1_blk = 0x0000; /* No gpe1 block */ fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */ diff --git a/src/soc/amd/stoneyridge/acpi/fch.asl b/src/soc/amd/stoneyridge/acpi/fch.asl index 1e0c889..6a815b3 100644 --- a/src/soc/amd/stoneyridge/acpi/fch.asl +++ b/src/soc/amd/stoneyridge/acpi/fch.asl @@ -157,7 +157,7 @@ #if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) /* TODO: It is unstable. */ - #include "acpi/AmdImc.asl" /* Hudson IMC function */ + #include "acpi/AmdImc.asl" ITZE() /* enable IMC Fan Control*/ #endif } /* End Method(_SB._INI) */ diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 473b118..3f01603 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -20,7 +20,7 @@ #include <bootblock_common.h> #include <agesawrapper.h> #include <agesawrapper_call.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -47,7 +47,7 @@ post_code(0x90); if (CONFIG_STONEYRIDGE_UART) - configure_hudson_uart(); + configure_stoneyridge_uart(); } void bootblock_soc_init(void) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 487201b..14f76b7 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -18,7 +18,7 @@ #include <cpu/cpu.h> #include <device/device.h> #include <device/pci.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <soc/northbridge.h> static void cpu_bus_init(device_t dev) @@ -59,17 +59,17 @@ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; else if (dev->path.type == DEVICE_PATH_PCI) - hudson_enable(dev); + sb_enable(dev); } static void soc_init(void *chip_info) { - hudson_init(chip_info); + southbridge_init(chip_info); } static void soc_final(void *chip_info) { - hudson_final(chip_info); + southbridge_final(chip_info); fam15_finalize(chip_info); } diff --git a/src/soc/amd/stoneyridge/dimmSpd.c b/src/soc/amd/stoneyridge/dimmSpd.c index a69b80c..ace22bb 100644 --- a/src/soc/amd/stoneyridge/dimmSpd.c +++ b/src/soc/amd/stoneyridge/dimmSpd.c @@ -43,7 +43,7 @@ [info->SocketId][info->MemChannelId][info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *)info->Buffer, 128); + int err = sb_readSpd(spdAddress, (void *)info->Buffer, 128); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index c1a2978..5166a7f 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -21,13 +21,13 @@ #include <reset.h> #include <arch/cpu.h> #include <cbmem.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <soc/pci_devs.h> #include <Fch/Fch.h> #include <cpu/x86/msr.h> #include <delay.h> -void configure_hudson_uart(void) +void configure_stoneyridge_uart(void) { u8 byte; @@ -50,7 +50,7 @@ + 0x88, 0x01); } -void hudson_pci_port80(void) +void sb_pci_port80(void) { u8 byte; pci_devfn_t dev; @@ -62,7 +62,7 @@ pci_write_config8(dev, 0x4a, byte); } -void hudson_lpc_port80(void) +void sb_lpc_port80(void) { u8 byte; pci_devfn_t dev; @@ -81,7 +81,7 @@ pci_write_config8(dev, 0x4a, byte); } -void hudson_lpc_decode(void) +void sb_lpc_decode(void) { pci_devfn_t dev; u32 tmp = 0; @@ -222,7 +222,7 @@ return nvram_pos; } -void hudson_clk_output_48Mhz(void) +void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -237,7 +237,7 @@ write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); } -static uintptr_t hudson_spibase(void) +static uintptr_t sb_spibase(void) { /* Make sure the base address is predictable */ device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); @@ -256,9 +256,9 @@ return (uintptr_t)base; } -void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) +void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { - uintptr_t base = hudson_spibase(); + uintptr_t base = sb_spibase(); write16((void *)base + SPI100_SPEED_CONFIG, (norm << SPI_NORM_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) | @@ -267,33 +267,32 @@ write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); } -void hudson_disable_4dw_burst(void) +void sb_disable_4dw_burst(void) { - uintptr_t base = hudson_spibase(); + uintptr_t base = sb_spibase(); write16((void *)base + SPI100_HOST_PREF_CONFIG, read16((void *)base + SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST); } -/* Hudson 1-3 only. For Hudson 1, call with fast=1 */ -void hudson_set_readspeed(u16 norm, u16 fast) +void sb_set_readspeed(u16 norm, u16 fast) { - uintptr_t base = hudson_spibase(); + uintptr_t base = sb_spibase(); write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) & ~SPI_CNTRL1_SPEED_MASK) | (norm << SPI_NORM_SPEED_SH) | (fast << SPI_FAST_SPEED_SH)); } -void hudson_read_mode(u32 mode) +void sb_read_mode(u32 mode) { - uintptr_t base = hudson_spibase(); + uintptr_t base = sb_spibase(); write32((void *)base + SPI_CNTRL0, (read32((void *)base + SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode); } -void hudson_tpm_decode_spi(void) +void sb_tpm_decode_spi(void) { device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* LPC device */ @@ -308,10 +307,10 @@ * Hardware should enable LPC ROM by pin straps. This function does not * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. * - * The HUDSON power-on default is to map 512K ROM space. + * The southbridge power-on default is to map 512K ROM space. * */ -void hudson_enable_rom(void) +void sb_enable_rom(void) { u8 reg8; pci_devfn_t dev; @@ -345,7 +344,7 @@ void bootblock_fch_early_init(void) { - hudson_enable_rom(); - hudson_lpc_port80(); - hudson_lpc_decode(); + sb_enable_rom(); + sb_lpc_port80(); + sb_lpc_decode(); } diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index 7ed6721..efe34e5 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <device/pci_ehci.h> #include <device/pci_def.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #define DEBUGPORT_MISC_CONTROL 0x80 diff --git a/src/soc/amd/stoneyridge/hda.c b/src/soc/amd/stoneyridge/hda.c index 2623236..b41b999 100644 --- a/src/soc/amd/stoneyridge/hda.c +++ b/src/soc/amd/stoneyridge/hda.c @@ -20,7 +20,7 @@ #include <device/pci_ops.h> #include <arch/io.h> #include <delay.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 7a3c804..193fb0c 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -54,12 +54,12 @@ write16((void *)(SMI_BASE + offset), value); } -void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); -void hudson_disable_gevent_smi(uint8_t gevent); -void hudson_enable_acpi_cmd_smi(void); +void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); +void disable_gevent_smi(uint8_t gevent); +void enable_acpi_cmd_smi(void); #ifndef __SMM__ -void hudson_enable_smi_generation(void); +void enable_smi_generation(void); #endif #endif /* _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h similarity index 88% rename from src/soc/amd/stoneyridge/include/soc/hudson.h rename to src/soc/amd/stoneyridge/include/soc/southbridge.h index 48f5e0d..de481f0 100644 --- a/src/soc/amd/stoneyridge/include/soc/hudson.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -138,13 +138,11 @@ #define SPI_READ_MODE_DUAL122 (BIT(30) ) #define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) #define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) -/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */ -#define SPI_READ_MODE_FAST_HUDSON1 ( BIT(18)) #define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) #define SPI_ARB_ENABLE BIT(19) #define SPI_CNTRL1 0x0c -/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ #define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) #define SPI_NORM_SPEED_SH 12 #define SPI_FAST_SPEED_SH 8 @@ -167,34 +165,34 @@ #define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) -static inline int hudson_sata_enable(void) +static inline int sb_sata_enable(void) { /* True if IDE or AHCI. */ return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 2); } -static inline int hudson_ide_enable(void) +static inline int sb_ide_enable(void) { /* True if IDE or LEGACY IDE. */ return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3); } -void hudson_enable_rom(void); -void configure_hudson_uart(void); -void hudson_clk_output_48Mhz(void); -void hudson_disable_4dw_burst(void); -void hudson_enable(device_t dev); -void hudson_final(void *chip_info); -void hudson_init(void *chip_info); -void hudson_lpc_port80(void); -void hudson_lpc_decode(void); -void hudson_pci_port80(void); -void hudson_read_mode(u32 mode); -void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void hudson_set_readspeed(u16 norm, u16 fast); -void hudson_tpm_decode_spi(void); +void sb_enable_rom(void); +void configure_stoneyridge_uart(void); +void sb_clk_output_48Mhz(void); +void sb_disable_4dw_burst(void); +void sb_enable(device_t dev); +void southbridge_final(void *chip_info); +void southbridge_init(void *chip_info); +void sb_lpc_port80(void); +void sb_lpc_decode(void); +void sb_pci_port80(void); +void sb_read_mode(u32 mode); +void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); +void sb_set_readspeed(u16 norm, u16 fast); +void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); u8 pm_read8(u8 reg); diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index fae5c55..75cedfe 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -31,7 +31,7 @@ #include <pc80/i8259.h> #include <soc/acpi.h> #include <soc/pci_devs.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <soc/nvs.h> #include <vboot/vbnv.h> @@ -105,7 +105,7 @@ pm_write8(PM_SERIRQ_CONF, byte); } -static void hudson_lpc_read_resources(device_t dev) +static void lpc_read_resources(device_t dev) { struct resource *res; global_nvs_t *gnvs; @@ -141,7 +141,7 @@ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); } -static void hudson_lpc_set_resources(struct device *dev) +static void lpc_set_resources(struct device *dev) { struct resource *res; u32 spi_enable_bits; @@ -162,7 +162,7 @@ * @param dev the device whose children's resources are to be enabled * */ -static void hudson_lpc_enable_childrens_resources(device_t dev) +static void lpc_enable_childrens_resources(device_t dev) { struct bus *link; u32 reg, reg_x; @@ -218,7 +218,7 @@ base = res->base; end = resource_end(res); /* find a resource size */ - printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n", + printk(BIOS_DEBUG, "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n", dev_path(child), base, end); switch (base) { case 0x60: /* KB */ @@ -342,10 +342,10 @@ pci_write_config8(dev, 0x74, wiosize); } -static void hudson_lpc_enable_resources(device_t dev) +static void lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); - hudson_lpc_enable_childrens_resources(dev); + lpc_enable_childrens_resources(dev); } unsigned long acpi_fill_mcfg(unsigned long current) @@ -359,9 +359,9 @@ }; static struct device_operations lpc_ops = { - .read_resources = hudson_lpc_read_resources, - .set_resources = hudson_lpc_set_resources, - .enable_resources = hudson_lpc_enable_resources, + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 8553025..73f944d 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -18,7 +18,7 @@ #include <arch/io.h> #include <reset.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #define HT_INIT_CONTROL 0x6c #define HTIC_BIOSR_Detect (1 << 5) diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 1380fb7..c69bbf6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -19,7 +19,7 @@ #include <agesawrapper.h> #include <agesawrapper_call.h> #include <soc/northbridge.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <amdblocks/psp.h> asmlinkage void car_stage_entry(void) diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index bd013c8..e2de3e6 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -20,7 +20,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/io.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> static void sata_init(struct device *dev) diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 421151a..0c31a3e 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -24,7 +24,7 @@ #include <cpu/x86/lapic.h> #include <arch/ioapic.h> #include <stdlib.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <soc/smbus.h> #define NMI_OFF 0 @@ -37,8 +37,8 @@ #endif /* -* HUDSON enables all USB controllers by default in SMBUS Control. -* HUDSON enables SATA by default in SMBUS Control. +* The southbridge enables all USB controllers by default in SMBUS Control. +* The southbridge enables SATA by default in SMBUS Control. */ static void sm_init(device_t dev) @@ -108,11 +108,11 @@ .write_byte = lsmbus_write_byte, }; -static void hudson_sm_read_resources(device_t dev) +static void sm_read_resources(device_t dev) { } -static void hudson_sm_set_resources(struct device *dev) +static void sm_set_resources(struct device *dev) { } @@ -120,8 +120,8 @@ .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations smbus_ops = { - .read_resources = hudson_sm_read_resources, - .set_resources = hudson_sm_set_resources, + .read_resources = sm_read_resources, + .set_resources = sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, .scan_bus = scan_smbus, diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 73e6702..6669ccb 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -20,7 +20,7 @@ #include <Porting.h> #include <AGESA.h> #include <amdlib.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <dimmSpd.h> /*----------------------------------------------------------------------------- @@ -144,7 +144,7 @@ __outbyte(ioBase + 0x0e, 66000000 / 400000 / 4); } -int hudson_readSpd(int spdAddress, char *buf, size_t len) +int sb_readSpd(int spdAddress, char *buf, size_t len) { int ioBase = 0xb00; setupFch(ioBase); diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index c92697c..31ca5d1 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -17,7 +17,7 @@ } /** Set the EOS bit and enable SMI generation from southbridge */ -void hudson_enable_smi_generation(void) +void enable_smi_generation(void) { uint32_t reg = smi_read32(SMI_REG_SMITRIG0); reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index fecaf90..822738c 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -39,7 +39,7 @@ * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. * @param level SMI_LVL_LOW or SMI_LVL_HIGH */ -void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) +void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) { uint32_t reg32; /* GEVENT pins range from [0:23] */ @@ -59,7 +59,7 @@ } /** Disable events from given GEVENT pin */ -void hudson_disable_gevent_smi(uint8_t gevent) +void disable_gevent_smi(uint8_t gevent) { /* GEVENT pins range from [0:23] */ if (gevent > 23) { @@ -72,7 +72,7 @@ } /** Enable SMIs on writes to ACPI SMI command port */ -void hudson_enable_acpi_cmd_smi(void) +void enable_acpi_cmd_smi(void) { configure_smi(STONEYRIDGE_SMI_ACPI_COMMAND, SMI_MODE_SMI); } diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 5a646a6..a8ff96a 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -9,9 +9,8 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <delay.h> -#include <soc/hudson.h> #include <soc/smi.h> - +#include <soc/southbridge.h> #define SMI_0x88_ACPI_COMMAND (1 << 11) @@ -25,7 +24,7 @@ SMI_SOURCE_0x90 = (1 << 5) }; -static void hudson_apmc_smi_handler(void) +static void sb_apmc_smi_handler(void) { u32 reg32; const uint8_t cmd = inb(ACPI_SMI_CTL_PORT); @@ -88,7 +87,7 @@ if (status & SMI_0x88_ACPI_COMMAND) { /* Command received via ACPI SMI command port */ - hudson_apmc_smi_handler(); + sb_apmc_smi_handler(); } /* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x88, status); diff --git a/src/soc/amd/stoneyridge/hudson.c b/src/soc/amd/stoneyridge/southbridge.c similarity index 90% rename from src/soc/amd/stoneyridge/hudson.c rename to src/soc/amd/stoneyridge/southbridge.c index 0eee351..5e36100 100644 --- a/src/soc/amd/stoneyridge/hudson.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -25,7 +25,7 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <amd_pci_util.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> #include <soc/smbus.h> #include <soc/smi.h> #if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) @@ -60,12 +60,12 @@ return read16((void *)(PM_MMIO_BASE + reg)); } -void hudson_enable(device_t dev) +void sb_enable(device_t dev) { - printk(BIOS_DEBUG, "hudson_enable()\n"); + printk(BIOS_DEBUG, "%s\n", __func__); } -static void hudson_init_acpi_ports(void) +static void sb_init_acpi_ports(void) { /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. @@ -80,7 +80,7 @@ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT); - hudson_enable_acpi_cmd_smi(); + enable_acpi_cmd_smi(); } else { pm_write16(PM_ACPI_SMI_CMD, 0); } @@ -91,12 +91,12 @@ pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2)); } -void hudson_init(void *chip_info) +void southbridge_init(void *chip_info) { - hudson_init_acpi_ports(); + sb_init_acpi_ports(); } -void hudson_final(void *chip_info) +void southbridge_final(void *chip_info) { #if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) agesawrapper_fchecfancontrolservice(); diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 7919207..9cc0c94 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -14,7 +14,7 @@ */ #include <console/uart.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> uintptr_t uart_platform_base(int idx) { diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index 6f27395..c1caf7d 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -20,7 +20,7 @@ #include <device/pci_ops.h> #include <device/pci_ehci.h> #include <arch/io.h> -#include <soc/hudson.h> +#include <soc/southbridge.h> static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, -- To view, visit https://review.coreboot.org/20912 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Gerrit-Change-Number: 20912 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: google/kahlee: Set eMMC slot
by Marc Jones (Code Review) 08 Aug '17

08 Aug '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/20911 Change subject: google/kahlee: Set eMMC slot ...................................................................... google/kahlee: Set eMMC slot Set AGESA SD/eMMc variable to non-removable eMMc. BUG=b:63891719 BRANCH=none TEST=Boot eMMC on Kahlee. Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/google/kahlee/BiosCallOuts.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/20911/1 diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index c65c930..7bef2f3 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -54,7 +54,11 @@ FchParams_env->Sata.SataIdeMode = TRUE; break; } - printk(BIOS_DEBUG, "Done\n"); + + /* SDHCI/MMC configuration */ + FchParams_env->Sd.SdSlotType = 1; /* eMMC */ + + printk(BIOS_DEBUG, "Done\n"); } return AGESA_SUCCESS; -- To view, visit https://review.coreboot.org/20911 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16 Gerrit-Change-Number: 20911 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

1 0

Change in coreboot[master]: stoneyridge: Fix CPU ASL \_PR table
by Marc Jones (Code Review) 08 Aug '17

08 Aug '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/20910 Change subject: stoneyridge: Fix CPU ASL \_PR table ...................................................................... stoneyridge: Fix CPU ASL \_PR table The PMIO region was moved, but not updated in the ASL. Change to generate \_PR table runtime and to report the correct PMIO region. Fix on Kahlee, where the EC overlaps the region: [ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0 [ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16 BUG=b:63902389 BRANCH=none TEST=Cros_ec_lps can reserve the region. ACPI tables are correct. Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/acpi/cpu.asl M src/soc/amd/stoneyridge/chip.c 3 files changed, 36 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/20910/1 diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 54af59b..327faef 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -26,6 +26,7 @@ #include <arch/ioapic.h> #include <cbmem.h> #include <device/device.h> +#include <device/pci.h> #include <soc/acpi.h> #include <soc/hudson.h> #include <soc/nvs.h> @@ -231,6 +232,31 @@ header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } +void generate_cpu_entries(device_t device) +{ + int cores, cpu, plen = 6; + u32 pcontrol_blk = ACPI_GPE0_BLK; + device_t cdb_dev; + + /* Stoney Ridge is single node, just report # of cores */ + cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5)); + cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1; + + printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); + + for (cpu = 0; cpu < cores; cpu++) { + if (cpu > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor(cpu, pcontrol_blk, plen); + + acpigen_pop_len(); + } +} + unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 32dad76..9da1550 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -21,62 +21,12 @@ /* * Processor Object */ -Scope (\_PR) { /* define processor scope */ - Processor( - P000, /* name space name */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - - Processor( - P001, /* name space name */ - 1, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P002, /* name space name */ - 2, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P003, /* name space name */ - 3, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P004, /* name space name */ - 4, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P005, /* name space name */ - 5, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P006, /* name space name */ - 6, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - P007, /* name space name */ - 7, /* Unique number for this processor */ - 0x0810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } -} /* End _PR scope */ +/* These devices are created at runtime */ +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) +External (\_PR.CP04, DeviceObj) +External (\_PR.CP05, DeviceObj) +External (\_PR.CP06, DeviceObj) +External (\_PR.CP07, DeviceObj) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 2af466b..487201b 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -32,6 +32,7 @@ .enable_resources = DEVICE_NOOP, .init = &cpu_bus_init, .scan_bus = cpu_bus_scan, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; struct device_operations pci_domain_ops = { -- To view, visit https://review.coreboot.org/20910 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f Gerrit-Change-Number: 20910 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: drivers/i2c: Add driver for rt5663 codec
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20904 ) Change subject: drivers/i2c: Add driver for rt5663 codec ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58308/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13719/ : SUCCESS -- To view, visit https://review.coreboot.org/20904 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3425fcbe13c9a5987fc91086d283a86db55c0819 Gerrit-Change-Number: 20904 Gerrit-PatchSet: 2 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 14:45:01 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/apollolake: Provide option to use Common MP Init
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20895 ) Change subject: soc/intel/apollolake: Provide option to use Common MP Init ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58307/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13718/ : SUCCESS -- To view, visit https://review.coreboot.org/20895 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I35d012785000d3f3bfcc34138cda9cd4591559f6 Gerrit-Change-Number: 20895 Gerrit-PatchSet: 3 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 13:44:25 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/apollolake: Provide option to use Common MP Init
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20895 ) Change subject: soc/intel/apollolake: Provide option to use Common MP Init ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58306/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/13717/ : SUCCESS -- To view, visit https://review.coreboot.org/20895 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I35d012785000d3f3bfcc34138cda9cd4591559f6 Gerrit-Change-Number: 20895 Gerrit-PatchSet: 2 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 13:38:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/t*00/romstage: Switch to new hybrid driver
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20794 ) Change subject: mb/lenovo/t*00/romstage: Switch to new hybrid driver ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58303/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13714/ : SUCCESS -- To view, visit https://review.coreboot.org/20794 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73 Gerrit-Change-Number: 20794 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 12:54:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Improve IGD detection
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20909 ) Change subject: nb/intel/sandybridge/raminit: Improve IGD detection ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58304/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13715/ : SUCCESS -- To view, visit https://review.coreboot.org/20909 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4bace296ead8220c930a49686f62e94d93da7f39 Gerrit-Change-Number: 20909 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 12:53:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [NOTFORMERGE] mb/lenovo/t400: Remove false docking events
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20908 ) Change subject: [NOTFORMERGE] mb/lenovo/t400: Remove false docking events ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58305/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13716/ : SUCCESS -- To view, visit https://review.coreboot.org/20908 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I327002f5626316948c806f4afcb6466575ffc55c Gerrit-Change-Number: 20908 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 12:49:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drvs/lenovo/hybrid_graphics: Add new hybrid graphics driver
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20792 ) Change subject: drvs/lenovo/hybrid_graphics: Add new hybrid graphics driver ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58301/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13712/ : SUCCESS -- To view, visit https://review.coreboot.org/20792 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie467f9a18b35ab3b8a523dbf51c5575db5b374a5 Gerrit-Change-Number: 20792 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 12:44:35 +0000 Gerrit-HasComments: No

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