coreboot-gerrit August 2017

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Change in coreboot[master]: mb/intel/dg43gt: Add mainboard
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19256 ) Change subject: mb/intel/dg43gt: Add mainboard ...................................................................... Patch Set 18: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58298/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13708/ : SUCCESS -- To view, visit https://review.coreboot.org/19256 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4 Gerrit-Change-Number: 19256 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 11:44:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/i82801jx: Remove dead code
by Arthur Heymans (Code Review) 08 Aug '17

08 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20906 Change subject: sb/intel/i82801jx: Remove dead code ...................................................................... sb/intel/i82801jx: Remove dead code Setting up default BARs and DMI init code is done in northbridge code. Change-Id: I6cfa3018ca7f5ef351415c4ec6e178ade353f7a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/southbridge/intel/i82801jx/dmi_setup.c D src/southbridge/intel/i82801jx/early_init.c M src/southbridge/intel/i82801jx/i82801jx.h 3 files changed, 0 insertions(+), 203 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/20906/1 diff --git a/src/southbridge/intel/i82801jx/dmi_setup.c b/src/southbridge/intel/i82801jx/dmi_setup.c deleted file mode 100644 index 83633a4..0000000 --- a/src/southbridge/intel/i82801jx/dmi_setup.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_def.h> -#include <console/console.h> -#include <northbridge/intel/gm45/gm45.h> -#include "i82801jx.h" - -/* VC1 Port Arbitration Table */ -static const u8 vc1_pat[] = { - 0x0f, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x0f, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0xf0, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0f, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0xf0, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x0f, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x0f, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0xf0, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0f, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0xf0, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, -}; -void i82801jx_dmi_setup(void) -{ - int i; - u32 reg32; - - RCBA32(RCBA_V1CAP) = (RCBA32(RCBA_V1CAP) & ~(0x7f<<16)) | (0x12<<16); - - RCBA32(0x0088) = 0x00109000; - RCBA16(0x01fc) = 0x060b; - RCBA32(0x01f4) = 0x86000040; - RCBA8 (0x0220) = 0x45; - RCBA32(0x2024) &= ~(1 << 7); - - - /* VC1 setup for isochronous transfers: */ - - /* Set VC1 virtual channel id to 1. */ - RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 24)) | (0x1 << 24); - /* Enable TC7 traffic on VC1. */ - RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7f << 1)) | (1 << 7); - /* Disable TC7-TC1 traffic on VC0. */ - RCBA32(RCBA_V0CTL) &= ~(0x7f << 1); - /* TC7-TC1 traffic on PCIe root ports will be disabled in pci driver. */ - - /* Set table type to time-based WRR. */ - RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 17)) | (0x4 << 17); - /* Program port arbitration table. */ - for (i = 0; i < sizeof(vc1_pat); ++i) - RCBA8(RCBA_PAT + i) = vc1_pat[i]; - /* Load port arbitration table. */ - RCBA32(RCBA_V1CTL) |= (1 << 16); - - /* Enable VC1. */ - RCBA32(RCBA_V1CTL) |= (1 << 31); - - - /* Setup RCRB: */ - - /* Set component id to 2 for southbridge, northbridge has id 1. */ - RCBA8(RCBA_ESD + 2) = 2; - /* Set target port number and target component id of the northbridge. */ - RCBA8(RCBA_ULD + 3) = 1; - RCBA8(RCBA_ULD + 2) = 1; - /* Set target rcrb base address, i.e. DMIBAR. */ - RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR; - - /* Enable ASPM. */ - if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) { - reg32 = RCBA32(RCBA_DMC); - /* Enable mobile specific power saving (set this first). */ - reg32 = (reg32 & ~(3 << 10)) | (1 << 10); - RCBA32(RCBA_DMC) = reg32; - /* Enable DMI power savings. */ - reg32 |= (1 << 19); - RCBA32(RCBA_DMC) = reg32; - /* Advertise L0s and L1. */ - RCBA32(RCBA_LCAP) |= (3 << 10); - /* Enable L0s and L1. */ - RCBA32(RCBA_LCTL) |= (3 << 0); - } else { - /* Enable DMI power savings. */ - RCBA32(RCBA_DMC) |= (1 << 19); - /* Advertise L0s only. */ - RCBA32(RCBA_LCAP) = (RCBA32(RCBA_LCAP) & ~(3<<10)) | (1<<10); - /* Enable L0s only. */ - RCBA32(RCBA_LCTL) = (RCBA32(RCBA_LCTL) & ~(3<< 0)) | (1<< 0); - } -} - -/* Should be called after VC1 has been enabled on both sides. */ -void i82801jx_dmi_poll_vc1(void) -{ - int timeout; - - timeout = 0x7ffff; - printk(BIOS_DEBUG, "ICH10 waits for VC1 negotiation... "); - while ((RCBA32(RCBA_V1STS) & (1 << 1)) && --timeout) {} - if (!timeout) - printk(BIOS_DEBUG, "timeout!\n"); - else - printk(BIOS_DEBUG, "done.\n"); - - /* Check for x2 DMI link. */ - if (((RCBA16(RCBA_LSTS) >> 4) & 0x3f) == 2) { - printk(BIOS_DEBUG, "x2 DMI link detected.\n"); - RCBA32(0x2024) = (RCBA32(0x2024) & ~(7 << 21)) | (3 << 21); - RCBA16(0x20c4) |= (1 << 15); - RCBA16(0x20e4) |= (1 << 15); - /* TODO: Maybe we have to save and - restore these settings across S3. */ - } - - timeout = 0x7ffff; - printk(BIOS_DEBUG, "ICH10 waits for port arbitration table update... "); - while ((RCBA32(RCBA_V1STS) & (1 << 0)) && --timeout) {} - if (!timeout) - printk(BIOS_DEBUG, "timeout!\n"); - else - printk(BIOS_DEBUG, "done.\n"); -} diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c deleted file mode 100644 index e2ac852..0000000 --- a/src/southbridge/intel/i82801jx/early_init.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include "i82801jx.h" - -void i82801jx_early_init(void) -{ - const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - - /* Set up RCBA. */ - pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - /* Set up PMBASE. */ - pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); - /* Enable PMBASE. */ - pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); - - /* Set up GPIOBASE. */ - pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); - /* Enable GPIO. */ - pci_write_config8(d31f0, D31F0_GPIO_CNTL, - pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); - - /* Reset watchdog. */ - outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ - outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */ - - /* Enable upper 128bytes of CMOS. */ - RCBA32(0x3400) = (1 << 2); - - /* Initialize power management initialization - register early as it affects reboot behavior. */ - /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6 - and 0xe (required if ME is disabled but present), bit 31 locks it. - The other bits are 'must write'. */ - u8 reg8 = pci_read_config8(d31f0, 0xac); - reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); - pci_write_config8(d31f0, 0xac, reg8); - - /* TODO: If RTC power failed, reset RTC state machine - (set, then reset RTC 0x0b bit7) */ - - /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) - before they get cleared. */ -} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index fe55157..9b0f955 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -229,9 +229,6 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -void i82801jx_early_init(void); -void i82801jx_dmi_setup(void); -void i82801jx_dmi_poll_vc1(void); int southbridge_detect_s3_resume(void); #endif -- To view, visit https://review.coreboot.org/20906 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6cfa3018ca7f5ef351415c4ec6e178ade353f7a7 Gerrit-Change-Number: 20906 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/google/poppy: Set I2C frequency to 1MHz
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20174 ) Change subject: mb/google/poppy: Set I2C frequency to 1MHz ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58295/ : SUCCESS -- To view, visit https://review.coreboot.org/20174 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05c56bcbecd093565549d5996179cac393b22635 Gerrit-Change-Number: 20174 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 09:15:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/l520/Kconfig: Remove hybrid graphics driver support
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20798 ) Change subject: mb/lenovo/l520/Kconfig: Remove hybrid graphics driver support ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58296/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13707/ : SUCCESS -- To view, visit https://review.coreboot.org/20798 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4bfa02fdbc5da5b556010c2f300faaf6dc845b80 Gerrit-Change-Number: 20798 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 09:13:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use common PMC for apollolake
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19375 ) Change subject: soc/intel/apollolake: Use common PMC for apollolake ...................................................................... Patch Set 25: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58294/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13706/ : SUCCESS -- To view, visit https://review.coreboot.org/19375 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2 Gerrit-Change-Number: 19375 Gerrit-PatchSet: 25 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 06:35:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/i2c: Add driver for rt5663 codec
by Furquan Shaikh (Code Review) 08 Aug '17

08 Aug '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/20904 ) Change subject: drivers/i2c: Add driver for rt5663 codec ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/20904 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3425fcbe13c9a5987fc91086d283a86db55c0819 Gerrit-Change-Number: 20904 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 05:53:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Log wakes caused by PME on internal bus and PCIE RP
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20532 ) Change subject: soc/intel/skylake: Log wakes caused by PME on internal bus and PCIE RP ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58293/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13705/ : SUCCESS -- To view, visit https://review.coreboot.org/20532 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7 Gerrit-Change-Number: 20532 Gerrit-PatchSet: 8 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 04:44:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: payloads/external/tianocore: Add and apply patches for tianocore
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20639 ) Change subject: payloads/external/tianocore: Add and apply patches for tianocore ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58292/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13704/ : SUCCESS -- To view, visit https://review.coreboot.org/20639 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4eaa602418995a68753b1ed13af8c6374eaa312f Gerrit-Change-Number: 20639 Gerrit-PatchSet: 8 Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Prabal Saha <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 01:56:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: lint: Update lint-stable-021-coreboot-lowercase
by build bot (Jenkins) (Code Review) 08 Aug '17

08 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20905 ) Change subject: lint: Update lint-stable-021-coreboot-lowercase ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58291/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13703/ : SUCCESS -- To view, visit https://review.coreboot.org/20905 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I82186f401d267d7594fe1cd88c818c4a7015ba91 Gerrit-Change-Number: 20905 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 01:54:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: lint: Update lint-stable-021-coreboot-lowercase
by Martin Roth (Code Review) 08 Aug '17

08 Aug '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20905 Change subject: lint: Update lint-stable-021-coreboot-lowercase ...................................................................... lint: Update lint-stable-021-coreboot-lowercase - Exclude .patch files from check - Exclude 'CorebootBdsLib' path in Tianocore. Change-Id: I82186f401d267d7594fe1cd88c818c4a7015ba91 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M util/lint/lint-stable-021-coreboot-lowercase 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/20905/1 diff --git a/util/lint/lint-stable-021-coreboot-lowercase b/util/lint/lint-stable-021-coreboot-lowercase index 0df70b8..ef83a66 100755 --- a/util/lint/lint-stable-021-coreboot-lowercase +++ b/util/lint/lint-stable-021-coreboot-lowercase @@ -16,7 +16,7 @@ LC_ALL=C export LC_ALL -EXCLUDE='^3rdparty/\|util/crossgcc/xgcc\|Binary file\|coreboot\|COREBOOT\|CorebootPayload\|CorebootModule\|minnowboard.org/…' +EXCLUDE='^3rdparty/\|util/crossgcc/xgcc\|Binary file\|coreboot\|COREBOOT\|CorebootPayload\|CorebootModule\|minnowboard.org/…' # Use git grep if the code is in a git repo, otherwise use grep. if [ -n "$(command -v git)" ] && [ -d .git ]; then -- To view, visit https://review.coreboot.org/20905 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I82186f401d267d7594fe1cd88c818c4a7015ba91 Gerrit-Change-Number: 20905 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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coreboot-gerrit August 2017