coreboot-gerrit August 2017

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Change in coreboot[master]: [RFC] Reinvent I2C ops
by Nico Huber (Code Review) 09 Aug '17

09 Aug '17

Nico Huber has uploaded a new patch set (#3). ( https://review.coreboot.org/20846 ) Change subject: [RFC] Reinvent I2C ops ...................................................................... [RFC] Reinvent I2C ops Do not use the global platform_i2c_transfer() function that can only be implemented by a single driver. Instead, make a `struct device` aware transfer() function the only interface function for I2C controller dri- vers to implement. To not force the slave device drivers to be implemented either above generic I2C or specialized SMBus operations, we support SMBus control- lers in the slave device interface too. We start with four simple slave functions: i2c_readb(), i2c_writeb(), i2c_readb_at() and i2c_writeb_at(). They are all compatible to respec- tive SMBus functions. But we keep aliases because it would be weird to force e.g. an I2C EEPROM driver to call smbus_read_byte(). Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/Makefile.inc M src/device/i2c.c A src/device/i2c_bus.c M src/include/device/i2c_bus.h M src/include/device/i2c_simple.h M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/i2c/lpss_i2c.c M src/soc/intel/common/block/i2c/lpss_i2c.h 8 files changed, 266 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/20846/3 -- To view, visit https://review.coreboot.org/20846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818 Gerrit-Change-Number: 20846 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Nico Huber (Code Review) 09 Aug '17

09 Aug '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/20913 ) Change subject: mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... Patch Set 4: (1 comment) > Why don't you use existing interface to make coreboot compatible > with tpacpi-bat and thinkpad_acpi? I think a diff of patch set 3 and 4 answers the question: Left-hand side looks good, right-hand side looks like shit. https://review.coreboot.org/#/c/20913/3/src/mainboard/lenovo/x200/acpi/bat_… File src/mainboard/lenovo/x200/acpi/bat_thresh.asl: https://review.coreboot.org/#/c/20913/3/src/mainboard/lenovo/x200/acpi/bat_… PS3, Line 38: * =0: Use battery default setting Why is there a space after `Store` but not after `Or`? -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Aug 2017 10:28:55 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: util/cbmem, util/cbfstool: resolve macro errors on FreeBSD
by Idwer Vollering (Code Review) 09 Aug '17

09 Aug '17

Idwer Vollering has uploaded this change for review. ( https://review.coreboot.org/20924 Change subject: util/cbmem, util/cbfstool: resolve macro errors on FreeBSD ...................................................................... util/cbmem, util/cbfstool: resolve macro errors on FreeBSD Using sys/cdefs.h would come to mind, however this include would not solve the build error. Built and runtime tested on FreeBSD 12.0-CURRENT, r322031 Change-Id: I6ec9bc7fea72aa69a41439e002f381bd5e5b6bc6 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- M util/cbfstool/compiler.h M util/cbmem/compiler.h 2 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/20924/1 diff --git a/util/cbfstool/compiler.h b/util/cbfstool/compiler.h index a830239..80d2476 100644 --- a/util/cbfstool/compiler.h +++ b/util/cbfstool/compiler.h @@ -18,11 +18,12 @@ #if defined(__WIN32) || defined(__WIN64) #define __packed __attribute__((gcc_struct, packed)) -#else +#endif +#if !defined(__FreeBSD__) #define __packed __attribute__((packed)) +#define __aligned(x) __attribute__((aligned(x))) #endif -#define __aligned(x) __attribute__((aligned(x))) #define __always_unused __attribute__((unused)) #define __must_check __attribute__((warn_unused_result)) diff --git a/util/cbmem/compiler.h b/util/cbmem/compiler.h index a830239..80d2476 100644 --- a/util/cbmem/compiler.h +++ b/util/cbmem/compiler.h @@ -18,11 +18,12 @@ #if defined(__WIN32) || defined(__WIN64) #define __packed __attribute__((gcc_struct, packed)) -#else +#endif +#if !defined(__FreeBSD__) #define __packed __attribute__((packed)) +#define __aligned(x) __attribute__((aligned(x))) #endif -#define __aligned(x) __attribute__((aligned(x))) #define __always_unused __attribute__((unused)) #define __must_check __attribute__((warn_unused_result)) -- To view, visit https://review.coreboot.org/20924 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6ec9bc7fea72aa69a41439e002f381bd5e5b6bc6 Gerrit-Change-Number: 20924 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com>

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Change in coreboot[master]: mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Arthur Heymans (Code Review) 09 Aug '17

09 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20913 ) Change subject: mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/20913/4/src/mainboard/lenovo/x200/acpi/bat_… File src/mainboard/lenovo/x200/acpi/bat_thresh.asl: https://review.coreboot.org/#/c/20913/4/src/mainboard/lenovo/x200/acpi/bat_… PS4, Line 34: /* SetBatteryCharge Start/Stop Capacity Threshold : * In Parameter: : * DWORD : * Bit 7-0: Charge stop capacity (Unit:%) : * =0: Use battery default setting : * =1-99: Threshold to stop charging battery (Relative capacity) : * Bit 9-8:BatteryID : * = 0: Any battery : * = 1: Primary battery : * = 2: Secondary battery : * = Others: Reserved (0) : * Bit 31-10: Reserved (0) : * Must be Zero : * : * Out Parameter: : * DWORD : * Bit 30-0: Reserved (0) : * Bit 31: Error status : * 0 ... Success : * 1 ... Fail : */ These comments are taken from the tpacpi-bat (https://github.com/teleshoes/tpacpi-bat) project documentation which afaict is GPL3. IANAL so is this acceptable or does it need a rewrite? -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Aug 2017 08:37:01 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Arthur Heymans (Code Review) 09 Aug '17

09 Aug '17

Hello Patrick Rudolph, Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/20913 to look at the new patch set (#4). Change subject: mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... mb/lenovo/x200: Add ACPI methods to set battery thresholds Partially implements the calls tpacpi-bat (pretty standard utility for for setting these advanced battery settings on later thinkpads) needs. What works: Setting and reading thresholds. Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/lenovo/x200/acpi/bat_thresh.asl M src/mainboard/lenovo/x200/dsdt.asl 2 files changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/20913/4 -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Arthur Heymans (Code Review) 09 Aug '17

09 Aug '17

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Change in coreboot[master]: mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Patrick Rudolph (Code Review) 09 Aug '17

09 Aug '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/20913 ) Change subject: mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... Patch Set 3: Why don't you use existing interface to make coreboot compatible with tpacpi-bat and thinkpad_acpi? They use the following ACPI methods: * BCCS * BCSS * BICS * BDSS * PSSS They allow to set thresholds, inhibit charge, peak shift, ... -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Aug 2017 07:11:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Adding in my mainboard source files.
by Arthur Heymans (Code Review) 09 Aug '17

09 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20921 ) Change subject: Adding in my mainboard source files. ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/20921/1/src/mainboard/gigabyte/ga-h61m-ds2/… File src/mainboard/gigabyte/ga-h61m-ds2/romstage.c: https://review.coreboot.org/#/c/20921/1/src/mainboard/gigabyte/ga-h61m-ds2/… PS1, Line 67: RCBA32(FD) = 0x17ee1fe1; This one might be disabling your pcie bridge required for wifi? -- To view, visit https://review.coreboot.org/20921 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I999f632748e4b6bc52cc0c5dbd1f3aebc6cad04a Gerrit-Change-Number: 20921 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Morgan <xamboni(a)protonmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 09 Aug 2017 06:24:30 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: Adding in my mainboard source files.
by Alexander Morgan (Code Review) 09 Aug '17

09 Aug '17

Alexander Morgan has uploaded this change for review. ( https://review.coreboot.org/20921 Change subject: Adding in my mainboard source files. ...................................................................... Adding in my mainboard source files. Change-Id: I999f632748e4b6bc52cc0c5dbd1f3aebc6cad04a --- A src/mainboard/gigabyte/ga-h61m-ds2/Kconfig A src/mainboard/gigabyte/ga-h61m-ds2/Kconfig.name A src/mainboard/gigabyte/ga-h61m-ds2/Makefile.inc A src/mainboard/gigabyte/ga-h61m-ds2/acpi/ec.asl A src/mainboard/gigabyte/ga-h61m-ds2/acpi/platform.asl A src/mainboard/gigabyte/ga-h61m-ds2/acpi/superio.asl A src/mainboard/gigabyte/ga-h61m-ds2/acpi/thermal.asl A src/mainboard/gigabyte/ga-h61m-ds2/acpi/video.asl A src/mainboard/gigabyte/ga-h61m-ds2/acpi_tables.c A src/mainboard/gigabyte/ga-h61m-ds2/board_info.txt A src/mainboard/gigabyte/ga-h61m-ds2/cmos.default A src/mainboard/gigabyte/ga-h61m-ds2/cmos.layout A src/mainboard/gigabyte/ga-h61m-ds2/devicetree.cb A src/mainboard/gigabyte/ga-h61m-ds2/dsdt.asl A src/mainboard/gigabyte/ga-h61m-ds2/gma-mainboard.ads A src/mainboard/gigabyte/ga-h61m-ds2/gpio.c A src/mainboard/gigabyte/ga-h61m-ds2/hda_verb.c A src/mainboard/gigabyte/ga-h61m-ds2/mainboard.c A src/mainboard/gigabyte/ga-h61m-ds2/romstage.c A src/mainboard/gigabyte/ga-h61m-ds2/thermal.h 20 files changed, 1,279 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/20921/1 diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/Kconfig b/src/mainboard/gigabyte/ga-h61m-ds2/Kconfig new file mode 100644 index 0000000..ff22853 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/Kconfig @@ -0,0 +1,71 @@ +if BOARD_GIGABYTE_GA_H61M_DS2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA1155 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select INTEL_INT15 + select UDELAY_TSC + select SERIRQ_CONTINUOUS_MODE + select MAINBOARD_HAS_LIBGFXINIT +# select MAINBOARD_HAS_NATIVE_VGA_INIT + +config MMCONF_BASE_ADDRESS + hex + default 0xf8000000 + +config DRAM_RESET_GATE_GPIO + int + default 25 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + string + default gigabyte/ga-h61m-ds2 + +config MAINBOARD_PART_NUMBER + string + default "GA-H61M-DS2" + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,0102" + +config VGA_BIOS_FILE + string + default "pci8086,0102.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config IFD_BIOS_SECTION + string + default "0x00600000:0x007fffff" + +config IFD_ME_SECTION + string + default "0x00001000:0x004fffff" + +endif # BOARD_GIGABYTE_GA_H61M_DS2 diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-ds2/Kconfig.name new file mode 100644 index 0000000..296b2c7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_H61M_DS2 + bool "GA-H61M-DS2" diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-ds2/Makefile.inc new file mode 100644 index 0000000..63976c4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/acpi/ec.asl b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/ec.asl diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/acpi/platform.asl b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/platform.asl new file mode 100644 index 0000000..d8d3320 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/acpi/superio.asl b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/superio.asl new file mode 100644 index 0000000..4c50b6c --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/superio.asl @@ -0,0 +1,4 @@ +/* mainboard configuration */ + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/acpi/thermal.asl b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/thermal.asl new file mode 100644 index 0000000..c2bc80c --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/thermal.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/acpi/video.asl b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/video.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/acpi/video.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-ds2/acpi_tables.c new file mode 100644 index 0000000..05a21ae --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/acpi_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/board_info.txt b/src/mainboard/gigabyte/ga-h61m-ds2/board_info.txt new file mode 100644 index 0000000..ede1945 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4151#ov +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release date: 2012 diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/cmos.default b/src/mainboard/gigabyte/ga-h61m-ds2/cmos.default new file mode 100644 index 0000000..767372c --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/cmos.default @@ -0,0 +1,8 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +sata_mode=AHCI +hyper_threading=Enable diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/cmos.layout b/src/mainboard/gigabyte/ga-h61m-ds2/cmos.layout new file mode 100644 index 0000000..5600a6b --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-ds2/devicetree.cb new file mode 100644 index 0000000..aa39fc4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/devicetree.cb @@ -0,0 +1,113 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "1" + register "gpu_panel_power_backlight_off_delay" = "500" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "5000" + register "gpu_panel_power_up_delay" = "2100" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1458 0x5000 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1458 0x5000 + end + device pci 1c.1 on # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1458 0x5000 + end + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x1458 0x5000 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device pci 1e.0 on # PCI bridge VGA controller + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1458 0x5001 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMBus + subsystemid 0x1458 0x5001 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1458 0x5000 + end + device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0101 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1458 0xd000 + end + device pci 03.0 on # PCIe Bridge for Wifi Card + subsystemid 0x1458 0xd000 + end + end +end diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/dsdt.asl b/src/mainboard/gigabyte/ga-h61m-ds2/dsdt.asl new file mode 100644 index 0000000..10faccd --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/dsdt.asl @@ -0,0 +1,29 @@ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } +} diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/gma-mainboard.ads b/src/mainboard/gigabyte/ga-h61m-ds2/gma-mainboard.ads new file mode 100644 index 0000000..06511f9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/gma-mainboard.ads @@ -0,0 +1,13 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/gpio.c b/src/mainboard/gigabyte/ga-h61m-ds2/gpio.c new file mode 100644 index 0000000..10501e7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/gpio.c @@ -0,0 +1,476 @@ +#include <southbridge/intel/common/gpio.h> + +// GPIO_USE_SEL +// 7 Series Default: 0xB96BA1FF +// Inteltool: 0xB96BB9C3 +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +// GP_IO_SEL +// 7 Series Default: 0xEEFF6EFF +// Inteltool: 0xAEFF6EC3 +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +// GP_LVL +// 7 Series Default: 0x02FE0100 +// Inteltool: 0xE8FB6FBD +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +// GP_RST_SEL1 +// 7 Series Default: 0x01000000 +// Inteltool: 0x01000000 +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +// GPI_INV +// 7 Series Default: 0x00000000 +// Inteltool: 0x00002800 +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_NO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +// GPO_BLINK +// 7 Series Default: 0x00040000 +// Inteltool: 0x00040000 +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +// GPIO_USE_SEL2 +// 7 Series Default: 0x020300FF +// Inteltool: 0x020380FF +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +// GP_IO_SEL2 +// 7 Series Default: 0x1F57FFF4 +// Inteltool: 0x1F57FFF4 +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +// GP_LVL2 +// 7 Series Default: 0xA4AA0007 +// Inteltool: 0xFEFF7FC7 +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +// GP_RST_SEL2 +// 7 Series Default: 0x00000000 +// Inteltool: 0x00000000 +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +// GPIO_USE_SEL3 +// 7 Series Default: 0x00000130 +// Inteltool: 0x00000130 +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +// GP_IO_SEL3 +// 7 Series Default: 0x00000FF0 +// Inteltool: 0x00000FF0 +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +// GP_LVL3 +// 7 Series Default: 0x000000C0 +// Inteltool: 0x00000DDF +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_HIGH, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +// GP_RST_SEL3 +// 7 Series Default: 0x00000000 +// Inteltool: 0x00000000 +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-ds2/hda_verb.c new file mode 100644 index 0000000..62688c9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/hda_verb.c @@ -0,0 +1,28 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0887, // Realtek 887 + 0x1458a002, // Subsystem ID + 0x0000000e, // Number of entries + + /* Pin Widget Verb Table */ + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/mainboard.c b/src/mainboard/gigabyte/ga-h61m-ds2/mainboard.c new file mode 100644 index 0000000..f1968db --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/mainboard.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/romstage.c b/src/mainboard/gigabyte/ga-h61m-ds2/romstage.c new file mode 100644 index 0000000..cf5825f --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/romstage.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_BASE 0x2e +#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <superio/ite/it8728f/it8728f.h> +#include <superio/ite/common/ite.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +static void it8728f_h61mds2_disable_reboot(pnp_devfn_t dev) +{ + /* GPIO SIO settings */ + ite_reg_write(dev, 0xEF, 0x7E); // magic + + ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 + ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 + ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port + ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 + ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! + ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! + ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in + ite_reg_write(dev, 0xe9, 0x27); // bus select disable + ite_reg_write(dev, 0xf0, 0x10); // ? + ite_reg_write(dev, 0xf1, 0x42); // ? + ite_reg_write(dev, 0xf6, 0x1c); // hw monitor alert beep -> gp36(pin12) + + /* EC SIO settings */ + ite_reg_write(IT8728F_EC, 0xf1, 0xc0); + ite_reg_write(IT8728F_EC, 0xf6, 0xf0); + ite_reg_write(IT8728F_EC, 0xf9, 0x48); + ite_reg_write(IT8728F_EC, 0x60, 0x0a); + ite_reg_write(IT8728F_EC, 0x61, 0x30); + ite_reg_write(IT8728F_EC, 0x62, 0x0a); + ite_reg_write(IT8728F_EC, 0x63, 0x20); + ite_reg_write(IT8728F_EC, 0x30, 0x01); +} + +void rcba_config(void) +{ + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17ee1fe1; + + /* Enable HECI */ + RCBA32(FD2) &= ~0x2; +} + +void pch_enable_lpc(void) +{ + /* + * Enable: + * EC Decode Range PortA30/A20 + * SuperIO Port2E/2F + * PS/2 Keyboard/Mouse Port60/64 + * FDD Port3F0h-3F5h and Port3F7h + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + + /* Initialize SuperIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8728f_h61mds2_disable_reboot(SUPERIO_GPIO); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/gigabyte/ga-h61m-ds2/thermal.h b/src/mainboard/gigabyte/ga-h61m-ds2/thermal.h new file mode 100644 index 0000000..f14a7e4 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-ds2/thermal.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GAH61MDS2_THERMAL_H +#define GAH61MDS2_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif -- To view, visit https://review.coreboot.org/20921 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I999f632748e4b6bc52cc0c5dbd1f3aebc6cad04a Gerrit-Change-Number: 20921 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Morgan <xamboni(a)protonmail.com>

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Change in coreboot[master]: lint: update commit message check
by Martin Roth (Code Review) 09 Aug '17

09 Aug '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20920 Change subject: lint: update commit message check ...................................................................... lint: update commit message check - Update the commit message check from a lint-stable test to a lint-extended test. - Add the check for signed-off-by to the commit-msg hook Change-Id: I8be8aef25730d988c7cf1586ae66ecb839d5f756 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M util/gitconfig/commit-msg R util/lint/lint-extended-020-signed-off-by 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/20920/1 diff --git a/util/gitconfig/commit-msg b/util/gitconfig/commit-msg index 82f0581..2eef752 100755 --- a/util/gitconfig/commit-msg +++ b/util/gitconfig/commit-msg @@ -169,5 +169,8 @@ git hash-object -t commit --stdin } - +if ! grep -qi '^[[:space:]]*\+Signed-off-by:' "$MSG"; then + printf "\nError: No Signed-off-by line in the commit message.\n" + exit 1 +fi add_ChangeId diff --git a/util/lint/lint-stable-020-signed-off-by b/util/lint/lint-extended-020-signed-off-by similarity index 100% rename from util/lint/lint-stable-020-signed-off-by rename to util/lint/lint-extended-020-signed-off-by -- To view, visit https://review.coreboot.org/20920 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8be8aef25730d988c7cf1586ae66ecb839d5f756 Gerrit-Change-Number: 20920 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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coreboot-gerrit August 2017