coreboot-gerrit August 2017

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Change in coreboot[master]: [WIP] Porting Gigabyte GA-H61M-DS2. VGA and PCIe card issues.
by Alexander Morgan (Code Review) 09 Aug '17

09 Aug '17

Alexander Morgan has uploaded this change for review. ( https://review.coreboot.org/20919 Change subject: [WIP] Porting Gigabyte GA-H61M-DS2. VGA and PCIe card issues. ...................................................................... [WIP] Porting Gigabyte GA-H61M-DS2. VGA and PCIe card issues. Change-Id: I69792873861ab657c83a17f7ec0624a8092e588a --- M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/20919/1 diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index db24dda..1189160 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -32,6 +32,9 @@ #include "sandybridge.h" #include "gma.h" +// Including this c directly to fix the definition error "i915lightup_sandy. +#include "gma_sandybridge_lvds.c" + struct gt_powermeter { u16 reg; u32 value; @@ -648,7 +651,7 @@ physbase, &lightup_ok); } else { lightup_ok = i915lightup_sandy(&conf->gfx, physbase, - iobase, mmiobase, graphics_base); + (u16) iobase, mmiobase, graphics_base); } if (lightup_ok) gfx_set_init_done(1); diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index c3139a9..9a1a4ad 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -134,7 +134,9 @@ return 0; if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - return i915lightup_ivy(info, physbase, piobase, mmio, lfb); +// Commenting this call out. My board is sandy and this non-definition +// breaks build. +// return i915lightup_ivy(info, physbase, piobase, mmio, lfb); } write32(mmio + 0x00070080, 0x00000000); -- To view, visit https://review.coreboot.org/20919 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I69792873861ab657c83a17f7ec0624a8092e588a Gerrit-Change-Number: 20919 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Morgan <xamboni(a)protonmail.com>

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Change in coreboot[master]: mb/lenovo/x1_carbon_gen1: add missing '+' in spd/Makefile
by Alexander Couzens (Code Review) 09 Aug '17

09 Aug '17

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/20918 Change subject: mb/lenovo/x1_carbon_gen1: add missing '+' in spd/Makefile ...................................................................... mb/lenovo/x1_carbon_gen1: add missing '+' in spd/Makefile Each line of spd config overwriting the slot 0 instead of appending it. Change-Id: I0124aa34f1d4fcb30810fb7eef03d4828a7ac430 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Tested-on: lenovo x1 carbon gen 1 with elpida 8GB Fixes: e9787ff61f81 ("mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2") --- M src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/20918/1 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc index ec6e4f3..0c90826 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/spd/Makefile.inc @@ -16,8 +16,8 @@ SPD_BIN = $(obj)/spd.bin SPD_SOURCES = elpida.hex # 0b0000 Single Channel 2GB -SPD_SOURCES = samsung.hex # 0b0001 placeholder -SPD_SOURCES = samsung.hex # 0b0010 4GiB +SPD_SOURCES += samsung.hex # 0b0001 placeholder +SPD_SOURCES += samsung.hex # 0b0010 4GiB SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f)) # Include spd ROM data -- To view, visit https://review.coreboot.org/20918 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0124aa34f1d4fcb30810fb7eef03d4828a7ac430 Gerrit-Change-Number: 20918 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu>

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Change in coreboot[master]: intel/common/block/smm: Update smihandler to handle gpi
by Brandon Breitenstein (Code Review) 09 Aug '17

09 Aug '17

Brandon Breitenstein has removed Alexandru Gagniuc from this change. ( https://review.coreboot.org/20917 ) Change subject: intel/common/block/smm: Update smihandler to handle gpi ...................................................................... Removed reviewer Alexandru Gagniuc. -- To view, visit https://review.coreboot.org/20917 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteReviewer Gerrit-Change-Id: I6273fe846587137938bbcffa3a92736b91982574 Gerrit-Change-Number: 20917 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com>

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Change in coreboot[master]: intel/common/block/smm: Update smihandler to handle gpi
by Brandon Breitenstein (Code Review) 09 Aug '17

09 Aug '17

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/20917 Change subject: intel/common/block/smm: Update smihandler to handle gpi ...................................................................... intel/common/block/smm: Update smihandler to handle gpi Updating the common smihandler to handler gpi events which originally were going to be left to each soc to handle. After some more analysis the gpi handler can also be commonized. Change-Id: I6273fe846587137938bbcffa3a92736b91982574 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/reef/smihandler.c M src/soc/intel/apollolake/include/soc/smm.h M src/soc/intel/apollolake/smihandler.c M src/soc/intel/common/block/smm/smihandler.c 4 files changed, 24 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/20917/1 diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c index fe4f8c4..d8b4702 100644 --- a/src/mainboard/google/reef/smihandler.c +++ b/src/mainboard/google/reef/smihandler.c @@ -18,8 +18,8 @@ #include <baseboard/variants.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> #include <soc/pm.h> -#include <soc/smm.h> #include <soc/gpio.h> #include <variant/ec.h> #include <variant/gpio.h> diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index b37694e..eda0bc4 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -30,7 +30,4 @@ void southbridge_smm_clear_state(void); void southbridge_smm_enable_smi(void); -/* Mainboard handler for GPI SMIs*/ -void mainboard_smi_gpi_handler(const struct gpi_status *sts); - #endif diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index f834b1d..f1de888 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -34,21 +34,6 @@ return &em64t100_smm_ops; } -void __attribute__((weak)) -mainboard_smi_gpi_handler(const struct gpi_status *sts) { } - -static void southbridge_smi_gpi( - const struct smm_save_state_ops *save_state_ops) -{ - struct gpi_status smi_sts; - - gpi_clear_get_smi_status(&smi_sts); - mainboard_smi_gpi_handler(&smi_sts); - - /* Clear again after mainboard handler */ - gpi_clear_get_smi_status(&smi_sts); -} - const smi_handler_t southbridge_smi[32] = { [SLP_SMI_STS] = smihandler_southbridge_sleep, [APM_SMI_STS] = smihandler_southbridge_apmc, diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 7a4be47..90ac61d 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -356,6 +356,29 @@ printk(BIOS_DEBUG, "Periodic SMI.\n"); } +void __attribute__((weak)) +mainboard_smi_gpi_handler(const struct gpi_status *sts) { } + +void smihandler_southbridge_gpi( + const struct smm_save_state_ops *save_state_ops) +{ + struct gpi_status smi_sts; + + gpi_clear_get_smi_status(&smi_sts); + mainboard_smi_gpi_handler(&smi_sts); + + /* Clear again after mainboard handler */ + gpi_clear_get_smi_status(&smi_sts); +} + +void __attribute__((weak)) mainboard_smi_espi_handler(void) { } + +void smihandler_southbridge_espi( + const struct smm_save_state_ops *save_state_ops) +{ + mainboard_smi_espi_handler(); +} + void southbridge_smi_handler(void) { int i; -- To view, visit https://review.coreboot.org/20917 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6273fe846587137938bbcffa3a92736b91982574 Gerrit-Change-Number: 20917 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com>

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Change in coreboot[master]: Initial Kahlee SMM code.
by frank vibrans (Code Review) 08 Aug '17

08 Aug '17

frank vibrans has uploaded this change for review. ( https://review.coreboot.org/20916 Change subject: Initial Kahlee SMM code. ...................................................................... Initial Kahlee SMM code. This code implements SMM handling using an ASEG implementation. There is no real functional capability in place. SMIs are simply cleared and SMM is exited. Change-Id: Ifeca4323626af6089ce23892e79b0e560d92c100 Signed-off-by: frank vibrans <frank.vibrans(a)scarletltd.com> --- M src/cpu/x86/smm/smmhandler.S M src/include/cpu/x86/smm.h M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/model_15_init.c M src/soc/amd/stoneyridge/smi.c M src/soc/amd/stoneyridge/smihandler.c 7 files changed, 135 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/20916/1 diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index dd8a0c0..0617a0d 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -142,7 +142,8 @@ * without relying on the LAPIC ID. */ #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) \ - || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) + || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) \ + || IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI) /* LAPIC IDs start from 0x10; map that to the proper core index */ subl $0x10, %ecx #endif diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index bd0e356..aea4100 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -37,6 +37,8 @@ * starts @ 0x7e00 */ #define SMM_AMD64_ARCH_OFFSET 0x7e00 +#define SMM_AMD64_SAVE_STATE_OFFSET \ + SMM_SAVE_STATE_BEGIN(SMM_AMD64_ARCH_OFFSET) typedef struct { u16 es_selector; diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0425beb..19aa1b2 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -281,6 +281,10 @@ to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh. +config HAVE_SMI_HANDLER + bool "Enable SMM and SMI handling" + default y + config SMM_TSEG_SIZE hex default 0x800000 if HAVE_SMI_HANDLER diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 7a3c804..016ea4a 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -20,7 +20,24 @@ #define SMITRG0_EOS (1 << 28) #define SMITRG0_SMIENB (1 << 31) +#define SMI_REG_GPESTAT 0x00 /* GPE event status */ + +#define SMI_REG_SMISTAT0 0x80 +#define SMI_REG_SMISTAT1 0x84 +#define SMI_REG_SMISTAT2 0x88 +#define SMI_REG_SMISTAT3 0x8C +#define SMI_REG_SMISTAT4 0x90 + #define SMI_REG_CONTROL0 0xa0 + +#define SMI_REG_SMICTRL2 0xA8 /* Routes FakeSMIs reported in SMIx84 */ +#define SMICTRL2_FAKES_EN 0x00000054 /* Enable FakeSMIs reported in SMIx84 */ + +#define SMI_REG_SMICTRL8 0xC0 /* Routes FakeSMIs reported in SMIx90 */ +#define SMICTRL8_FAKES_EN 0x01500000 /* Enable FakeSMIs reported in SMIx90 */ + +#define SMI_REG_SMICTRL9 0xC4 /* Routes trap events reported in SMIx90 */ +#define SMICTRL9_MTRAP_EN 0x00010000 /* Enable memory trap SMI reported in SMIx90 */ enum smi_mode { SMI_MODE_DISABLE = 0, @@ -54,6 +71,9 @@ write16((void *)(SMI_BASE + offset), value); } +void smm_southbridge_enable(void); +void smm_southbridge_clear_state(void); + void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c index a46f322..6003bef 100644 --- a/src/soc/amd/stoneyridge/model_15_init.c +++ b/src/soc/amd/stoneyridge/model_15_init.c @@ -27,6 +27,7 @@ #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> @@ -54,6 +55,9 @@ u8 i; msr_t msr; int msrno; +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + unsigned int cpu_idx; +#endif #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -114,6 +118,21 @@ wrmsr(NB_CFG_MSR, msr); + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + cpu_idx = cpu_info()->index; + printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); + + /* Set SMM base address for this CPU */ + msr = rdmsr(MSR_SMM_BASE); + msr.lo = SMM_BASE - (cpu_idx * 0x400); + wrmsr(MSR_SMM_BASE, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(MSR_SMM_MASK); + msr.lo |= ((1 << 0) | (6 << 8)); /* Enable ASEG SMRAM Range as WB */ + wrmsr(MSR_SMM_MASK, msr); + } + /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index c92697c..e8c1180 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -8,12 +8,22 @@ #include <console/console.h> +#include <arch/io.h> #include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> #include <soc/smi.h> +#include <string.h> + void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { - printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); + printk(BIOS_DEBUG, "smm_setup_structures - STUB.\n"); } /** Set the EOS bit and enable SMI generation from southbridge */ @@ -24,3 +34,57 @@ reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); } + +/* Sets up ASEG MTRR and copies the SMM code to the ASEG. */ +void smm_init(void) +{ + + msr_t msr, syscfg_orig, mtrr_aseg_orig; + + printk(BIOS_DEBUG, "SMM_mem_init\n"); + + /* Back up MSRs for later restore */ + syscfg_orig = rdmsr(SYSCFG_MSR); + mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000); + + /* MTRR changes don't like an enabled cache */ + disable_cache(); + + msr = syscfg_orig; + + /* Allow changes to MTRR extended attributes */ + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + /* turn the extended attributes off until we fix + * them so A0000 is routed to memory + */ + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* set DRAM access to 0xa0000-0xbffff to read, write, UC */ + msr.hi = msr.lo = 0x18181818; + wrmsr(MTRR_FIX_16K_A0000, msr); + + /* enable the extended features */ + msr = syscfg_orig; + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + enable_cache(); + + /* copy the real SMM handler */ + memcpy((void *)SMM_BASE, _binary_smm_start, + _binary_smm_end - _binary_smm_start); + wbinvd(); + + disable_cache(); + + /* Restore SYSCFG and MTRR */ + wrmsr(SYSCFG_MSR, syscfg_orig); + wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig); + + enable_cache(); + + /* CPU MSR are set in CPU init */ +} + diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 5a646a6..cb67801 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -110,8 +110,30 @@ smi_write32(0x90, status); } +void smm_southbridge_enable(void) +{ +} + +void smm_southbridge_clear_state(void) +{ + uint32_t reg = smi_read32(SMI_REG_GPESTAT); + smi_write32(SMI_REG_GPESTAT, reg); + + reg = smi_read32(SMI_REG_SMISTAT0); + smi_write32(SMI_REG_SMISTAT0, reg); + + reg = smi_read32(SMI_REG_SMISTAT1); + smi_write32(SMI_REG_SMISTAT1, reg); + + reg = smi_read32(SMI_REG_SMISTAT2); + smi_write32(SMI_REG_SMISTAT2, reg); + + reg = smi_read32(SMI_REG_SMISTAT4); + smi_write32(SMI_REG_SMISTAT4, reg); +} + void southbridge_smi_handler(unsigned int node, - smm_state_save_area_t *state_save) + smm_state_save_area_t *state_save) { const uint16_t smi_src = smi_read16(0x94); -- To view, visit https://review.coreboot.org/20916 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifeca4323626af6089ce23892e79b0e560d92c100 Gerrit-Change-Number: 20916 Gerrit-PatchSet: 1 Gerrit-Owner: frank vibrans <frank.vibrans(a)scarletltd.com>

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Change in coreboot[master]: mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Arthur Heymans (Code Review) 08 Aug '17

08 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20913 ) Change subject: mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/20913/3/src/mainboard/lenovo/x200/dsdt.asl File src/mainboard/lenovo/x200/dsdt.asl: https://review.coreboot.org/#/c/20913/3/src/mainboard/lenovo/x200/dsdt.asl@… PS3, Line 59: #include "acpi/bat_thresh.asl" should probably go under a different comment. -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 08 Aug 2017 20:01:18 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: util/me_cleaner: Pull the latest changes from upstream
by Nicola Corna (Code Review) 08 Aug '17

08 Aug '17

Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/20915 Change subject: util/me_cleaner: Pull the latest changes from upstream ...................................................................... util/me_cleaner: Pull the latest changes from upstream Relevant changes (commit 2e8761e): * Add an option to truncate the ME image file * Add full support for Skylake (ME 11) and following, including modules removal, truncation informations and partition relocation * Add two options to generate a shrinked ME image file and the corresponding descriptor with a modified flash layout * Update README.md * Bug fixes Also add a link to the usage guide in the Kconfig help. Change-Id: I690c5d558139f64f38babf3c0988b53834ba8b37 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- M src/southbridge/intel/common/firmware/Kconfig M util/me_cleaner/README.md M util/me_cleaner/me_cleaner.py 3 files changed, 378 insertions(+), 153 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/20915/1 diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 9d22b1b..6d33711 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -91,10 +91,11 @@ only on reverse engineering and trial & error. See the project's page - https://github.com/corna/me_cleaner + https://github.com/corna/me_cleaner or the wiki - https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F - https://github.com/corna/me_cleaner/wiki/me_cleaner-status + https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner + https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F + https://github.com/corna/me_cleaner/wiki/me_cleaner-status for more info about this tool If unsure, say N. diff --git a/util/me_cleaner/README.md b/util/me_cleaner/README.md index 0ca3d32..72c1598 100644 --- a/util/me_cleaner/README.md +++ b/util/me_cleaner/README.md @@ -1,26 +1,44 @@ -# ME cleaner +# me_cleaner -A cleaner for Intel ME/TXE images. +Intel ME is a coprocessor integrated in all post-2006 Intel boards, for which +this [Libreboot page](https://libreboot.org/faq.html#intelme) has an excellent +description. The main component of Intel ME is Intel AMT, and I suggest you to +read [this Wikipedia page](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology) +for more information about it. In short, Intel ME is an irremovable environment +with an obscure signed proprietary firmware, with full network and memory +access, which poses a serious security threat. +Even when disabled from the BIOS settings, Intel ME is active: the only way to +be sure it is disabled is to remove its firmware from the flash chip. -This tools removes any unnecessary partition from an Intel ME/TXE firmware, reducing -its size and its ability to interact with the system. -It should work both with coreboot and with the factory firmware. +Before Nehalem (ME version 6, 2008/2009) the ME firmware could be removed +completely from the flash chip by setting a couple of bits inside the flash +descriptor, without the need to reverse-engineer the ME firmware. -Currently this tool: - * Scans the FPT (partition table) and checks that everything is correct - * Removes any partition entry (except for FTPR) from FPT - * Removes any partition except for the fundamental one (FTPR) - * Removes the EFFS presence flag - * Corrects the FPT checksum - * Removes any non-essential LZMA or Huffman compressed module from the FTPR partition (pre-Skylake only) - * Relocates the remaining parts of the FTPR partition to the top of the ME region (pre-Skylake only) - * Checks the validity of the RSA signature of the FTPR partition +Starting from Nehalem the Intel ME firmware can't be removed anymore: without a +valid firmware the PC shuts off forcefully after 30 minutes. This project is an +attempt to remove as much code as possible from such firmware without falling +into the 30 minutes recovery mode. -Don't forget to power cycle your PC after flashing the modified ME/TXE image -(power off and power on, not just reboot). +me_cleaner currently works on most architectures, see [me_cleaner status](https://github.com/corna/me_cleaner/wiki/me_cleaner-status) (or [its discussion](https://github.com/corna/me_cleaner/issues/3)) +for more info about them. me_cleaner works also on the TXE and SPS firmware. -See the [current status](https://github.com/corna/me_cleaner/wiki/me_cleaner-status) -or [a more detailed description](https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F) -of me_cleaner. +If you want to understand how me_cleaner works, you can read the ["How does it work?" page](https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F). -Special thanks to Federico Amedeo Izzo for his help during the study of Intel ME. +If you want to apply me_cleaner on your platform I suggest you to read the +["How does it work?" page](https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F) +and then follow the guide ["How to apply me_cleaner"](https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner). + +For pre-Skylake firmware (ME version < 11) this tool removes almost everything, +leaving only the two fundamental modules needed for the correct boot, ROMP and +BUP. The code size is reduced from 1.5 MB (non-AMT firmware) or 5 MB (AMT +firmware) to ~90 kB of compressed code. + +Starting from Skylake (ME version >= 11) the ME subsystem and the firmware +structure have changed, requiring substantial changes in me_cleaner. +The fundamental modules required for the correct boot are now four (rbe, kernel, +syslib and bup) and the minimum code size is ~300 kB of compressed code (from +the 2 MB of the non-AMT firmware and the 7 MB of the AMT one). + +This project is based on the work of the community; in particular I thank Igor +Skochinsky, for the core information about Intel ME and its firmware structure, +and Federico Amedeo Izzo, for its help during the study of Intel ME. diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py index 8ca5498..e8a89cc 100755 --- a/util/me_cleaner/me_cleaner.py +++ b/util/me_cleaner/me_cleaner.py @@ -25,14 +25,15 @@ min_ftpr_offset = 0x400 spared_blocks = 4 -unremovable_modules = ("BUP", "ROMP") +unremovable_modules = ("ROMP", "BUP") +unremovable_modules_me11 = ("rbe", "kernel", "syslib", "bup") class OutOfRegionException(Exception): pass -class regionFile: +class RegionFile: def __init__(self, f, region_start, region_end): self.f = f self.region_start = region_start @@ -81,6 +82,13 @@ else: raise OutOfRegionException() + def save(self, filename, size): + self.f.seek(self.region_start) + copyf = open(filename, "w+b") + for i in range(0, size, 4096): + copyf.write(self.f.read(4096 if size - i >= 4096 else size - i)) + return copyf + def get_chunks_offsets(llut, me_start): chunk_count = unpack("<I", llut[0x04:0x08])[0] @@ -109,7 +117,7 @@ def remove_modules(f, mod_headers, ftpr_offset, me_end): - comp_str = ("Uncomp.", "Huffman", "LZMA") + comp_str = ("uncomp.", "Huffman", "LZMA") unremovable_huff_chunks = [] chunks_offsets = [] base = 0 @@ -211,6 +219,15 @@ return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME +def print_check_partition_signature(f, offset): + if check_partition_signature(f, offset): + print("VALID") + else: + print("INVALID!!") + sys.exit("The FTPR partition signature is not valid. Is the input " + "ME/TXE image valid?") + + def relocate_partition(f, me_start, me_end, partition_header_offset, new_offset, mod_headers): @@ -226,7 +243,7 @@ llut_start = unpack("<I", mod_header[0x38:0x3C])[0] + old_offset break - if llut_start != 0: + if mod_headers and llut_start != 0: # Bytes 0x9:0xb of the LLUT (bytes 0x1:0x3 of the AddrBase) are added # to the SpiBase (bytes 0xc:0x10 of the LLUT) to compute the final # start of the LLUT. Since AddrBase is not modifiable, we can act only @@ -239,43 +256,45 @@ new_offset = ((new_offset + 0x1f) // 0x20) * 0x20 offset_diff = new_offset - old_offset - print("Relocating {} to {:#x} - {:#x}..." - .format(name, new_offset, new_offset + partition_size)) + print("Relocating {} from {:#x} - {:#x} to {:#x} - {:#x}..." + .format(name, old_offset, old_offset + partition_size, + new_offset, new_offset + partition_size)) print(" Adjusting FPT entry...") f.write_to(partition_header_offset + 0x8, pack("<I", new_offset - me_start)) - if llut_start != 0: - f.seek(llut_start) - if f.read(4) == b"LLUT": - print(" Adjusting LUT start offset...") - lut_offset = llut_start + offset_diff + 0x40 - \ - lut_start_corr - me_start - f.write_to(llut_start + 0x0c, pack("<I", lut_offset)) + if mod_headers: + if llut_start != 0: + f.seek(llut_start) + if f.read(4) == b"LLUT": + print(" Adjusting LUT start offset...") + lut_offset = llut_start + offset_diff + 0x40 - \ + lut_start_corr - me_start + f.write_to(llut_start + 0x0c, pack("<I", lut_offset)) - print(" Adjusting Huffman start offset...") - f.seek(llut_start + 0x14) - old_huff_offset = unpack("<I", f.read(4))[0] - f.write_to(llut_start + 0x14, - pack("<I", old_huff_offset + offset_diff)) + print(" Adjusting Huffman start offset...") + f.seek(llut_start + 0x14) + old_huff_offset = unpack("<I", f.read(4))[0] + f.write_to(llut_start + 0x14, + pack("<I", old_huff_offset + offset_diff)) - print(" Adjusting chunks offsets...") - f.seek(llut_start + 0x4) - chunk_count = unpack("<I", f.read(4))[0] - f.seek(llut_start + 0x40) - chunks = bytearray(chunk_count * 4) - f.readinto(chunks) - for i in range(0, chunk_count * 4, 4): - if chunks[i + 3] != 0x80: - chunks[i:i + 3] = \ - pack("<I", unpack("<I", chunks[i:i + 3] + - b"\x00")[0] + offset_diff)[0:3] - f.write_to(llut_start + 0x40, chunks) + print(" Adjusting chunks offsets...") + f.seek(llut_start + 0x4) + chunk_count = unpack("<I", f.read(4))[0] + f.seek(llut_start + 0x40) + chunks = bytearray(chunk_count * 4) + f.readinto(chunks) + for i in range(0, chunk_count * 4, 4): + if chunks[i + 3] != 0x80: + chunks[i:i + 3] = \ + pack("<I", unpack("<I", chunks[i:i + 3] + + b"\x00")[0] + offset_diff)[0:3] + f.write_to(llut_start + 0x40, chunks) + else: + sys.exit("Huffman modules present but no LLUT found!") else: - sys.exit("Huffman modules present but no LLUT found!") - else: - print(" No Huffman modules found") + print(" No Huffman modules found") print(" Moving data...") partition_size = min(partition_size, me_end - old_offset) @@ -284,25 +303,173 @@ return new_offset +def check_and_remove_modules(f, me_start, me_end, offset, min_offset, + relocate, keep_modules): + + f.seek(offset + 0x20) + num_modules = unpack("<I", f.read(4))[0] + f.seek(offset + 0x290) + data = f.read(0x84) + + module_header_size = 0 + if data[0x0:0x4] == b"$MME": + if data[0x60:0x64] == b"$MME" or num_modules == 1: + module_header_size = 0x60 + elif data[0x80:0x84] == b"$MME": + module_header_size = 0x80 + + if module_header_size != 0: + f.seek(offset + 0x290) + mod_headers = [f.read(module_header_size) + for i in range(0, num_modules)] + + if all(hdr.startswith(b"$MME") for hdr in mod_headers): + if args.keep_modules: + end_addr = offset + ftpr_lenght + else: + end_addr = remove_modules(f, mod_headers, + offset, me_end) + + if args.relocate: + new_offset = relocate_partition(f, me_start, me_end, + me_start + 0x30, + min_offset + me_start, + mod_headers) + end_addr += new_offset - offset + offset = new_offset + + return end_addr, offset + + else: + print("Found less modules than expected in the FTPR " + "partition; skipping modules removal") + else: + print("Can't find the module header size; skipping " + "modules removal") + + return -1, offset + + +def check_and_remove_modules_me11(f, me_start, me_end, partition_offset, + partition_lenght, min_offset, relocate, + keep_modules): + + comp_str = ("LZMA/uncomp.", "Huffman") + + if keep_modules: + end_data = partition_offset + partition_lenght + else: + end_data = 0 + + f.seek(partition_offset + 0x4) + module_count = unpack("<I", f.read(4))[0] + + modules = [] + modules.append(("end", partition_lenght, 0)) + + f.seek(partition_offset + 0x10) + for i in range(0, module_count): + data = f.read(0x18) + name = data[0x0:0xc].rstrip(b"\x00").decode("ascii") + offset_block = unpack("<I", data[0xc:0x10])[0] + offset = offset_block & 0x01ffffff + comp_type = (offset_block & 0x02000000) >> 25 + + modules.append((name, offset, comp_type)) + + modules.sort(key=lambda x: x[1]) + + for i in range(0, module_count): + name = modules[i][0] + offset = partition_offset + modules[i][1] + end = partition_offset + modules[i + 1][1] + removed = False + + if name.endswith(".man") or name.endswith(".met"): + compression = "uncompressed" + else: + compression = comp_str[modules[i][2]] + + sys.stdout.write(" {:<12} ({:<12}, 0x{:06x} - 0x{:06x}): " + .format(name, compression, offset, end)) + + if name.endswith(".man"): + print("NOT removed, partition manif.") + elif name.endswith(".met"): + print("NOT removed, module metadata") + elif any(name.startswith(m) for m in unremovable_modules_me11): + print("NOT removed, essential") + else: + removed = True + f.fill_range(offset, min(end, me_end), b"\xff") + print("removed") + + if not removed: + end_data = max(end_data, end) + + if relocate: + new_offset = relocate_partition(f, me_start, me_end, me_start + 0x30, + min_offset + me_start, []) + end_data += new_offset - partition_offset + partition_offset = new_offset + + return end_data, partition_offset + + +def check_mn2_tag(f, offset): + f.seek(offset + 0x1c) + tag = f.read(4) + if tag != b"$MN2": + sys.exit("Wrong FTPR manifest tag ({}), this image may be corrupted" + .format(tag)) + + +def flreg_to_start_end(flreg): + return (flreg & 0x7fff) << 12, (flreg >> 4 & 0x7fff000 | 0xfff) + 1 + + +def start_end_to_flreg(start, end): + return (start & 0x7fff000) >> 12 | ((end - 1) & 0x7fff000) << 4 + + if __name__ == "__main__": parser = argparse.ArgumentParser(description="Tool to remove as much code " - "as possible from Intel ME/TXE firmwares") + "as possible from Intel ME/TXE firmware " + "images") parser.add_argument("file", help="ME/TXE image or full dump") parser.add_argument("-O", "--output", help="save the modified image in a " "separate file, instead of modifying the original " "file") parser.add_argument("-r", "--relocate", help="relocate the FTPR partition " - "to the top of the ME region", action="store_true") + "to the top of the ME region to save even more space", + action="store_true") parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR " "modules, even when possible", action="store_true") parser.add_argument("-d", "--descriptor", help="remove the ME/TXE " "Read/Write permissions to the other regions on the " "flash from the Intel Flash Descriptor (requires a " "full dump)", action="store_true") + parser.add_argument("-t", "--truncate", help="truncate the empty part of " + "the firmware (requires a separated ME/TXE image or " + "--extract-me)", action="store_true") parser.add_argument("-c", "--check", help="verify the integrity of the " "fundamental parts of the firmware and exit", action="store_true") + parser.add_argument("-D", "--extract-descriptor", help="extract the " + "flash descriptor from a full dump; when used with " + "--truncate save a descriptor with adjusted regions " + "start and end") + parser.add_argument("-M", "--extract-me", help="extract the ME firmware " + "from a full dump; when used with --truncate save a " + "truncated ME/TXE image") + args = parser.parse_args() + + if args.check: + if args.relocate: + sys.exit("-c and -r can't be used together") + elif args.truncate: + sys.exit("-c and -t can't be used together") f = open(args.file, "rb" if args.check or args.output else "r+b") f.seek(0x10) @@ -310,40 +477,47 @@ if magic == b"$FPT": print("ME/TXE image detected") - me_start = 0 - f.seek(0, 2) - me_end = f.tell() if args.descriptor: sys.exit("-d requires a full dump") + if args.extract_descriptor: + sys.exit("-D requires a full dump") + + if args.extract_me: + sys.exit("-M requires a full dump") + + me_start = 0 + f.seek(0, 2) + me_end = f.tell() + elif magic == b"\x5a\xa5\xf0\x0f": print("Full image detected") + + if args.truncate and not args.extract_me: + sys.exit("-t requires a separated ME/TXE image (or --extract-me)") + f.seek(0x14) flmap0, flmap1 = unpack("<II", f.read(8)) - nr = flmap0 >> 24 & 0x7 frba = flmap0 >> 12 & 0xff0 fmba = (flmap1 & 0xff) << 4 - if nr >= 2: - f.seek(frba) - flreg0, flreg1, flreg2 = unpack("<III", f.read(12)) - fd_start = (flreg0 & 0x1fff) << 12 - fd_end = flreg0 >> 4 & 0x1fff000 | 0xfff + 1 - me_start = (flreg2 & 0x1fff) << 12 - me_end = flreg2 >> 4 & 0x1fff000 | 0xfff + 1 - if me_start >= me_end: - sys.exit("The ME/TXE region in this image has been disabled") + f.seek(frba) + flreg = unpack("<III", f.read(12)) - f.seek(me_start + 0x10) - if f.read(4) != b"$FPT": - sys.exit("The ME/TXE region is corrupted or missing") + fd_start, fd_end = flreg_to_start_end(flreg[0]) + bios_start, bios_end = flreg_to_start_end(flreg[1]) + me_start, me_end = flreg_to_start_end(flreg[2]) - print("The ME/TXE region goes from {:#x} to {:#x}" - .format(me_start, me_end)) - else: - sys.exit("This image does not contains a ME/TXE firmware NR = {})" - .format(nr)) + if me_start >= me_end: + sys.exit("The ME/TXE region in this image has been disabled") + + f.seek(me_start + 0x10) + if f.read(4) != b"$FPT": + sys.exit("The ME/TXE region is corrupted or missing") + + print("The ME/TXE region goes from {:#x} to {:#x}" + .format(me_start, me_end)) else: sys.exit("Unknown image") @@ -378,8 +552,28 @@ if f.read(4) == b"$CPD": me11 = True num_entries = unpack("<I", f.read(4))[0] - ftpr_mn2_offset = 0x10 + num_entries * 0x18 + + f.seek(ftpr_offset + 0x10) + ftpr_mn2_offset = -1 + + for i in range(0, num_entries): + data = f.read(0x18) + name = data[0x0:0xc].rstrip(b"\x00").decode("ascii") + offset = unpack("<I", data[0xc:0xf] + b"\x00")[0] + + if name == "FTPR.man": + ftpr_mn2_offset = offset + break + + if ftpr_mn2_offset >= 0: + check_mn2_tag(f, ftpr_offset + ftpr_mn2_offset) + print("Found FTPR manifest at {:#x}" + .format(ftpr_offset + ftpr_mn2_offset)) + else: + sys.exit("Can't find the manifest of the FTPR partition") + else: + check_mn2_tag(f, ftpr_offset) me11 = False ftpr_mn2_offset = 0 @@ -394,7 +588,10 @@ shutil.copy(args.file, args.output) f = open(args.output, "r+b") - mef = regionFile(f, me_start, me_end) + mef = RegionFile(f, me_start, me_end) + + if args.descriptor or args.extract_descriptor: + fdf = RegionFile(f, fd_start, fd_end) print("Removing extra partitions...") mef.fill_range(me_start + 0x30, ftpr_offset, b"\xff") @@ -410,18 +607,15 @@ flags &= ~(0x00000001) mef.write_to(me_start + 0x24, pack("<I", flags)) - if args.descriptor: - print("Removing ME/TXE R/W access to the other flash regions...") - fdf = regionFile(f, fd_start, fd_end) - fdf.write_to(fmba + 0x4, pack("<I", 0x04040000)) - if me11: mef.seek(me_start + 0x10) header = bytearray(mef.read(0x20)) + header[0x0b] = 0x00 else: mef.seek(me_start) header = bytearray(mef.read(0x30)) - checksum = (0x100 - (sum(header) - header[0x1b]) & 0xff) & 0xff + header[0x1b] = 0x00 + checksum = (0x100 - sum(header) & 0xff) & 0xff print("Correcting checksum (0x{:02x})...".format(checksum)) # The checksum is just the two's complement of the sum of the first @@ -430,76 +624,88 @@ # must be always 0x00. mef.write_to(me_start + 0x1b, pack("B", checksum)) - if not me11: - print("Reading FTPR modules list...") - mef.seek(ftpr_offset + 0x1c) - tag = mef.read(4) - - if tag == b"$MN2": - mef.seek(ftpr_offset + 0x20) - num_modules = unpack("<I", mef.read(4))[0] - mef.seek(ftpr_offset + 0x290) - data = mef.read(0x84) - - module_header_size = 0 - if data[0x0:0x4] == b"$MME": - if data[0x60:0x64] == b"$MME" or num_modules == 1: - module_header_size = 0x60 - elif data[0x80:0x84] == b"$MME": - module_header_size = 0x80 - - if module_header_size != 0: - mef.seek(ftpr_offset + 0x290) - mod_headers = [mef.read(module_header_size) - for i in range(0, num_modules)] - - if all(hdr.startswith(b"$MME") for hdr in mod_headers): - if args.keep_modules: - end_addr = ftpr_offset + ftpr_lenght - else: - end_addr = remove_modules(mef, mod_headers, - ftpr_offset, me_end) - - if args.relocate: - new_ftpr_offset = relocate_partition(mef, - me_start, me_end, - me_start + 0x30, - min_ftpr_offset + me_start, - mod_headers) - end_addr += new_ftpr_offset - ftpr_offset - ftpr_offset = new_ftpr_offset - - end_addr = (end_addr // 0x1000 + 1) * 0x1000 - end_addr += spared_blocks * 0x1000 - - print("The ME minimum size should be {0} bytes " - "({0:#x} bytes)".format(end_addr - me_start)) - - if me_start > 0: - print("The ME region can be reduced up to:\n" - " {:08x}:{:08x} me" - .format(me_start, end_addr - 1)) - else: - print("Found less modules than expected in the FTPR " - "partition; skipping modules removal") - else: - print("Can't find the module header size; skipping " - "modules removal") - else: - print("Wrong FTPR partition tag ({}); skipping modules removal" - .format(tag)) + print("Reading FTPR modules list...") + if me11: + end_addr, ftpr_offset = \ + check_and_remove_modules_me11(mef, me_start, me_end, + ftpr_offset, ftpr_lenght, + min_ftpr_offset, args.relocate, + args.keep_modules) else: - print("Modules removal in ME v11 or greater is not yet supported") + end_addr, ftpr_offset = \ + check_and_remove_modules(mef, me_start, me_end, ftpr_offset, + min_ftpr_offset, args.relocate, + args.keep_modules) - sys.stdout.write("Checking FTPR RSA signature... ") - if check_partition_signature(f, ftpr_offset + ftpr_mn2_offset): - print("VALID") - else: - print("INVALID!!") - sys.exit("The FTPR partition signature is not valid. Is the input " - "ME/TXE image valid?") + if end_addr > 0: + end_addr = (end_addr // 0x1000 + 1) * 0x1000 + end_addr += spared_blocks * 0x1000 + + print("The ME minimum size should be {0} bytes " + "({0:#x} bytes)".format(end_addr - me_start)) + + if me_start > 0: + print("The ME region can be reduced up to:\n" + " {:08x}:{:08x} me".format(me_start, end_addr - 1)) + elif args.truncate: + print("Truncating file at {:#x}...".format(end_addr)) + f.truncate(end_addr) + + if args.descriptor: + print("Removing ME/TXE R/W access to the other flash regions...") + fdf.write_to(fmba + 0x4, pack("<I", 0x04040000)) + + if args.extract_descriptor: + if args.truncate: + print("Extracting the descriptor to \"{}\"..." + .format(args.extract_descriptor)) + fdf_copy = fdf.save(args.extract_descriptor, fd_end - fd_start) + + if bios_start == me_end: + print("Modifying the regions of the extracted descriptor...") + print(" {:08x}:{:08x} me --> {:08x}:{:08x} me" + .format(me_start, me_end - 1, me_start, end_addr - 1)) + print(" {:08x}:{:08x} bios --> {:08x}:{:08x} bios" + .format(bios_start, bios_end - 1, end_addr, bios_end - 1)) + + flreg1 = start_end_to_flreg(end_addr, bios_end) + flreg2 = start_end_to_flreg(me_start, end_addr) + + fdf_copy.seek(frba + 0x4) + fdf_copy.write(pack("<II", flreg1, flreg2)) + else: + print("\nWARNING:\n The start address of the BIOS region " + "isn't equal to the end address of the ME\n region: if " + "you want to recover the space from the ME region you " + "have to\n manually modify the descriptor.\n") + + fdf_copy.close() + else: + print("Extracting the descriptor to \"{}\"..." + .format(args.extract_descriptor)) + fdf.save(args.extract_descriptor, fd_end - fd_start).close() + + if args.extract_me: + if args.truncate: + print("Extracting and truncating the ME image to \"{}\"..." + .format(args.extract_me)) + mef_copy = mef.save(args.extract_me, end_addr - me_start) + else: + print("Extracting the ME image to \"{}\"..." + .format(args.extract_me)) + mef_copy = mef.save(args.extract_me, me_end - me_start) + + sys.stdout.write("Checking the FTPR RSA signature of the extracted ME " + "image... ") + print_check_partition_signature(mef_copy, ftpr_offset + + ftpr_mn2_offset - me_start) + mef_copy.close() + + sys.stdout.write("Checking the FTPR RSA signature... ") + print_check_partition_signature(f, ftpr_offset + ftpr_mn2_offset) f.close() if not args.check: print("Done! Good luck!") + -- To view, visit https://review.coreboot.org/20915 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I690c5d558139f64f38babf3c0988b53834ba8b37 Gerrit-Change-Number: 20915 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info>

1 0

Change in coreboot[master]: mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Arthur Heymans (Code Review) 08 Aug '17

08 Aug '17

Hello Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/20913 to look at the new patch set (#3). Change subject: mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... mb/lenovo/x200: Add ACPI methods to set battery thresholds TESTED with acpi_call: install the acpi_call module, and run as root: ``echo "\_SB.PCI0.LPCB.EC.BAT0.SLT xx" > /proc/acpi/call`` and check with ``ectool -d`` that byte 0x24 holds the value in hex that you wanted to set. Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/lenovo/x200/acpi/bat_thresh.asl M src/mainboard/lenovo/x200/dsdt.asl 2 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/20913/3 -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: mb/lenovo/x200: Add ACPI methods to set battery thresholds
by Arthur Heymans (Code Review) 08 Aug '17

08 Aug '17

Hello Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/20913 to look at the new patch set (#2). Change subject: mb/lenovo/x200: Add ACPI methods to set battery thresholds ...................................................................... mb/lenovo/x200: Add ACPI methods to set battery thresholds TESTED with acpi_call: install the acpi_call module, and run as root: ``echo "\_SB.PCI0.LPCB.EC.BAT0.SLT xx" > /proc/acpi/call`` and check with ``ectool -d`` that byte 24 holds the value in hex that you wanted to write. Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/lenovo/x200/acpi/bat_thresh.asl M src/mainboard/lenovo/x200/dsdt.asl 2 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/20913/2 -- To view, visit https://review.coreboot.org/20913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia049407cea7a60887ecba7b7c96e5000473865dd Gerrit-Change-Number: 20913 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add Kconfig option for fuses
by Nicola Corna (Code Review) 08 Aug '17

08 Aug '17

Nicola Corna has posted comments on this change. ( https://review.coreboot.org/20907 ) Change subject: nb/intel/sandybridge/raminit: Add Kconfig option for fuses ...................................................................... Patch Set 1: Code-Review+1 Working on my x220 with 1866 MHz memories. The memories correctly run at 1866 when the option is enabled, 1333 when not. -- To view, visit https://review.coreboot.org/20907 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Gerrit-Change-Number: 20907 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Aug 2017 19:18:46 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017