coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/cannonlake: Add missing _PCH_DEV definitions
by Furquan Shaikh (Code Review) 09 Aug '17

09 Aug '17

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/20932 ) Change subject: soc/intel/cannonlake: Add missing _PCH_DEV definitions ...................................................................... soc/intel/cannonlake: Add missing _PCH_DEV definitions Add all missing _PCH_DEV definitions to pci_devs.h Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/cannonlake/include/soc/pci_devs.h 1 file changed, 18 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/20932/2 -- To view, visit https://review.coreboot.org/20932 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3 Gerrit-Change-Number: 20932 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add missing _PCH_DEV definitions
by Furquan Shaikh (Code Review) 09 Aug '17

09 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20932 Change subject: soc/intel/cannonlake: Add missing _PCH_DEV definitions ...................................................................... soc/intel/cannonlake: Add missing _PCH_DEV definitions Add all missing _PCH_DEV definitions to pci_devs.h Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/cannonlake/include/soc/pci_devs.h 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/20932/1 diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index f687a33..d2f35af 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -53,9 +53,13 @@ #define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) #define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) #define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6) +#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, 0) +#define PCH_DEV_UFS _PCH_DEV(THERMAL, 5) +#define PCH_DEV_GSPI2 _PCH_DEV(THERMAL, 6) #define PCH_DEV_SLOT_ISH 0x13 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEV_ISH _PCH_DEV(ISH, 0) #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) @@ -102,8 +106,10 @@ #define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) #define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO2, 2) + #define PCH_DEV_SLOT_STORAGE 0x1A #define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) @@ -120,12 +126,18 @@ #define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3) #define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) #define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) +#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) +#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) #define PCH_DEV_SLOT_PCIE_1 0x1d #define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) #define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) #define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) #define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) +#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) +#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) +#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) #define PCH_DEV_SLOT_SIO3 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) @@ -134,6 +146,8 @@ #define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3) #define PCH_DEV_UART0 _PCH_DEV(SIO3, 0) #define PCH_DEV_UART1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) @@ -151,6 +165,7 @@ #define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define PCH_DEV_GBE _PCH_DEV(LPC, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7) static inline int spi_devfn_to_bus(unsigned int devfn) { -- To view, visit https://review.coreboot.org/20932 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3 Gerrit-Change-Number: 20932 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: libpayload/libpci: Add a constant for PCI class memory other
by Nico Huber (Code Review) 09 Aug '17

09 Aug '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/20930 Change subject: libpayload/libpci: Add a constant for PCI class memory other ...................................................................... libpayload/libpci: Add a constant for PCI class memory other Change-Id: I71e902c4ec843608c1518fe1e8b90fbcf98a13d1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/include/pci/pci.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/20930/1 diff --git a/payloads/libpayload/include/pci/pci.h b/payloads/libpayload/include/pci/pci.h index 6ce4dde..ee79d45 100644 --- a/payloads/libpayload/include/pci/pci.h +++ b/payloads/libpayload/include/pci/pci.h @@ -67,6 +67,8 @@ #define PCI_ROM_ADDRESS1 0x38 // on bridges #define PCI_ROM_ADDRESS_MASK ~0x7ff +#define PCI_CLASS_MEMORY_OTHER 0x0580 + #define PCI_VENDOR_ID_INTEL 0x8086 struct pci_dev { -- To view, visit https://review.coreboot.org/20930 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I71e902c4ec843608c1518fe1e8b90fbcf98a13d1 Gerrit-Change-Number: 20930 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: nb/intel/sandybridge/earlyinit: Add Kconfig for PCIe Gen3
by Patrick Rudolph (Code Review) 09 Aug '17

09 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20929 Change subject: nb/intel/sandybridge/earlyinit: Add Kconfig for PCIe Gen3 ...................................................................... nb/intel/sandybridge/earlyinit: Add Kconfig for PCIe Gen3 Add a Kconfig option to enable PCI Gen3. At the moment it's only supported by MRC as a special training sequence is required, that hasn't been implemented yet. Change-Id: I07b66cb353a3e572183ee00c79e8f240cf79107e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/20929/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 2d13f28..f033a5d 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -86,6 +86,13 @@ We can optimize the native case but the MRC blob requires it to be at 0xf0000000. +config ENABLE_PEG_GEN3 + def_bool n + depends on !USE_NATIVE_RAMINIT + help + PCIe Gen3 needs a special training sequence that increases boot time. + Native ram init doesn't support PCI Gen3 PEG ports. + if USE_NATIVE_RAMINIT config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index a5c6ce2..6b89219 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -285,9 +285,15 @@ if (pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B) & (1 << 20)) { printk(BIOS_DEBUG, "PEG: PCIe Gen3 disabled\n"); link_mask = (3 << 1); - } else + } else { printk(BIOS_DEBUG, "PEG: PCIe Gen3 supported\n"); + if (!IS_ENABLED(CONFIG_ENABLE_PEG_GEN3)) { + link_mask = (3 << 1); + printk(BIOS_DEBUG, "PEG: Limiting to PCIe Gen2\n"); + } + } + /* Configure PEG10/PEG11/PEG12 PHY */ ivybridge_peg_phy(); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 7145841..2d53c33 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -272,6 +272,9 @@ mainboard_fill_pei_data(&pei_data); + /* Init PCIe Gen3 if requested */ + pei_data.pcie_init = IS_ENABLED(CONFIG_ENABLE_PEG_GEN3); + post_code(0x3a); pei_data.boot_mode = s3resume ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); -- To view, visit https://review.coreboot.org/20929 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I07b66cb353a3e572183ee00c79e8f240cf79107e Gerrit-Change-Number: 20929 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/sandybridge/early_init: Read Gen3 feature disable fuse
by Patrick Rudolph (Code Review) 09 Aug '17

09 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20928 Change subject: nb/intel/sandybridge/early_init: Read Gen3 feature disable fuse ...................................................................... nb/intel/sandybridge/early_init: Read Gen3 feature disable fuse Read the PCIe Gen3 feature disable fuse and set PCIe target link speed accordingly. This feature is likely used on mobile platforms. Needs tests on all platforms. Change-Id: Id08f7e52064ae8b550a122b35d918d6d97193b13 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/early_init.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20928/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index f014e80..a5c6ce2 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -272,6 +272,7 @@ { u32 tmp; u32 deven; + u32 link_mask = (7 << 1); /* PEG on IvyBridge+ needs a special startup sequence. * As the MRC has its own initialization code skip it. */ @@ -280,22 +281,47 @@ IS_ENABLED(CONFIG_HAVE_MRC)) return; + /* Read PEG10 Gen3 feature disable fuse */ + if (pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B) & (1 << 20)) { + printk(BIOS_DEBUG, "PEG: PCIe Gen3 disabled\n"); + link_mask = (3 << 1); + } else + printk(BIOS_DEBUG, "PEG: PCIe Gen3 supported\n"); + /* Configure PEG10/PEG11/PEG12 PHY */ ivybridge_peg_phy(); deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); if (deven & DEVEN_PEG10) { + /* Update PEG10 target link speed */ + tmp = pci_read_config32(PCI_DEV(0, 1, 0), LCAP2); + tmp &= link_mask; + pci_write_config32(PCI_DEV(0, 1, 0), LCTL2, tmp); + + /* Start link training */ tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16); pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5)); } if (deven & DEVEN_PEG11) { + /* Update PEG11 target link speed */ + tmp = pci_read_config32(PCI_DEV(0, 1, 1), LCAP2); + tmp &= link_mask; + pci_write_config32(PCI_DEV(0, 1, 1), LCTL2, tmp); + + /* Start link training */ tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16); pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5)); } if (deven & DEVEN_PEG12) { + /* Update PEG12 target link speed */ + tmp = pci_read_config32(PCI_DEV(0, 1, 2), LCAP2); + tmp &= link_mask; + pci_write_config32(PCI_DEV(0, 1, 2), LCTL2, tmp); + + /* Start link training */ tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16); pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5)); } -- To view, visit https://review.coreboot.org/20928 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id08f7e52064ae8b550a122b35d918d6d97193b13 Gerrit-Change-Number: 20928 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/sandybridge/early_init: Read HWSTRAP
by Patrick Rudolph (Code Review) 09 Aug '17

09 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20927 Change subject: nb/intel/sandybridge/early_init: Read HWSTRAP ...................................................................... nb/intel/sandybridge/early_init: Read HWSTRAP Read HWSTRAP and split the PEG port into smaller chunks if neccessary. Limit the link width on each port and set DEVEN bits for each port. Needs test on all platforms. Change-Id: I61a886b20dc93384f5ea209c803a515fd06df178 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 66 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/20927/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index f1d9efe..f014e80 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -85,6 +85,10 @@ u8 reg8; u8 gfxsize; + /* Just make sure IGD is on ... */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); + reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID); switch (reg16) { case 0x0102: /* GT1 Desktop */ @@ -148,6 +152,61 @@ reg32 = MCHBAR32(0x5418); reg32 |= (1 << 4) | (1 << 5); MCHBAR32(0x5418) = reg32; +} + +/* PEG port split depending on HWSTRAP */ +static void peg1x_hwstrap_port_split(void) +{ + u32 deven; + u8 peg_lanes[3] = {16, 0, 0}; + + printk(BIOS_DEBUG, "PEG: lane configuration "); + switch ((pci_read_config32(PCI_DEV(0, 1, 0), HWSTRAP) >> 16) & 0x3) { + case 0: + printk(BIOS_DEBUG, "x8 x4 x4\n"); + peg_lanes[0] = 8; + peg_lanes[1] = 4; + peg_lanes[2] = 4; + break; + case 2: + printk(BIOS_DEBUG, "x8 x8\n"); + peg_lanes[0] = 8; + peg_lanes[1] = 8; + peg_lanes[2] = 0; + break; + default: + printk(BIOS_DEBUG, "x16\n"); + break; + } + + /* + * The HWSTRAP configures DEVEN and sets the link width on each + * PEG port. Note that the LCAP bit's are write-once ! + */ + deven = pci_read_config16(PCI_DEV(0, 0, 0), DEVEN); + deven &= ~(DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12); + if (peg_lanes[0] > 0) { + deven |= DEVEN_PEG10; + u32 tmp = pci_read_config32(PCI_DEV(0, 1, 0), LCAP); + tmp &= ~(0x1f << 4); + tmp |= (peg_lanes[0] << 4); + pci_write_config32(PCI_DEV(0, 1, 0), LCAP, tmp); + } + if (peg_lanes[1] > 0) { + deven |= DEVEN_PEG11; + u32 tmp = pci_read_config32(PCI_DEV(0, 1, 1), LCAP); + tmp &= ~(0x1f << 4); + tmp |= (peg_lanes[1] << 4); + pci_write_config32(PCI_DEV(0, 1, 1), LCAP, tmp); + } + if (peg_lanes[2] > 0) { + deven |= DEVEN_PEG12; + u32 tmp = pci_read_config32(PCI_DEV(0, 1, 2), LCAP); + tmp &= ~(0x1f << 4); + tmp |= (peg_lanes[2] << 4); + pci_write_config32(PCI_DEV(0, 1, 2), LCAP, tmp); + } + pci_write_config16(PCI_DEV(0, 0, 0), DEVEN, deven); } /* Static PHY configuration for IvyBridge */ @@ -250,7 +309,6 @@ void sandybridge_early_initialization(int chipset_type) { u32 capid0_a; - u32 deven; u8 reg8; /* Device ID Override Enable should be done very early */ @@ -271,12 +329,11 @@ /* Setup IOMMU BARs */ sandybridge_init_iommu(); - /* Device Enable, don't touch PEG bits */ - deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); - sandybridge_setup_graphics(); + /* Read PEG HWSTRAP and configure ports */ + peg1x_hwstrap_port_split(); + /* Write magic value to start PEG link training. * This should be done in PCI device enumeration, but * the PCIe specification requires to wait at least 100msec diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 9d88c70..039e760 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -109,7 +109,10 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ #define BCTRL1 0x3e /* 16bit */ - +#define LCAP 0xac /* 32bit */ +#define LCAP2 0xcc /* 32bit */ +#define LCTL2 0xd0 /* 16bit */ +#define HWSTRAP 0x504 /* 32bit */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ -- To view, visit https://review.coreboot.org/20927 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I61a886b20dc93384f5ea209c803a515fd06df178 Gerrit-Change-Number: 20927 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/sandybridge/early_init: Add static PHY init
by Patrick Rudolph (Code Review) 09 Aug '17

09 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20926 Change subject: nb/intel/sandybridge/early_init: Add static PHY init ...................................................................... nb/intel/sandybridge/early_init: Add static PHY init Write PEG PHY registers to improve PEG on IvyBridge. For PCIe Gen3 additional training sequence is required, but for PCIe Gen2 static PHY configuration should work fine. Needs test on all platforms. Change-Id: If66eba3d717c579228876467096bbada20732533 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/early_init.c 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/20926/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 3580f35..f1d9efe 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -150,6 +150,65 @@ MCHBAR32(0x5418) = reg32; } +/* Static PHY configuration for IvyBridge */ +static void ivybridge_peg_phy(void) +{ + u32 tmp; + + struct pcie_config { + u16 reg; + u32 and_mask; + u32 or_mask; + }; + + static const struct pcie_config lanes[] = { + {0x0a00, 0xf0d9ffc1, 0x0324001a}, + {0x0a04, 0xfff9e7ff, 0x00021800}, + }; + static const struct pcie_config bundles[] = { + {0x0700, 0x04177ff7, 0x09e88008}, + {0x0da0, 0x80F080F0, 0x27082708}, + {0x0900, 0xf3ffffff, 0x00000000}, + {0x0904, 0x8000f000, 0x2a1804a2}, + {0x0908, 0x27ffffff, 0x50000000}, + {0x090c, 0xc111f81f, 0x0ea00120}, + {0x0910, 0xffffc03f, 0x00000340}, + {0x0914, 0x77c21bff, 0x8815a400}, + }; + static const struct pcie_config single[] = { + {0x0308, 0xff80ff00, 0x0012006c}, + {0x0314, 0xff80ffff, 0x00130000}, + {0x0dd8, 0xffffbfff, 0x00004000}, + }; + + for (size_t j = 0; j < ARRAY_SIZE(lanes); j++) + for (size_t i = 0; i < 16; i++) { + const u16 reg = lanes[j].reg + i * 0x10; + + tmp = pci_read_config32(PCI_DEV(0, 1, 0), reg); + tmp &= lanes[j].and_mask; + tmp |= lanes[j].or_mask; + pci_write_config32(PCI_DEV(0, 1, 0), reg, tmp); + } + + for (size_t j = 0; j < ARRAY_SIZE(bundles); j++) + for (size_t i = 0; i < 8; i++) { + const u16 reg = bundles[j].reg + i * 0x20; + + tmp = pci_read_config32(PCI_DEV(0, 1, 0), reg); + tmp &= bundles[j].and_mask; + tmp |= bundles[j].or_mask; + pci_write_config32(PCI_DEV(0, 1, 0), reg, tmp); + } + + for (size_t j = 0; j < ARRAY_SIZE(single); j++) { + tmp = pci_read_config32(PCI_DEV(0, 1, 0), single[j].reg); + tmp &= single[j].and_mask; + tmp |= single[j].or_mask; + pci_write_config32(PCI_DEV(0, 1, 0), single[j].reg, tmp); + } +} + static void start_peg_link_training(void) { u32 tmp; @@ -162,6 +221,9 @@ IS_ENABLED(CONFIG_HAVE_MRC)) return; + /* Configure PEG10/PEG11/PEG12 PHY */ + ivybridge_peg_phy(); + deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); if (deven & DEVEN_PEG10) { -- To view, visit https://review.coreboot.org/20926 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If66eba3d717c579228876467096bbada20732533 Gerrit-Change-Number: 20926 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/sandybridge/gma: Fix platforms without NGI
by Patrick Rudolph (Code Review) 09 Aug '17

09 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20925 Change subject: nb/intel/sandybridge/gma: Fix platforms without NGI ...................................................................... nb/intel/sandybridge/gma: Fix platforms without NGI On platforms that do not have CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS add inline stubs to fix compilation on those systems. Change-Id: Ife9e7f6e61339b201bd3ff42c50f197605a56e00 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/gma.h 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/20925/1 diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 5b10920..8b537ad 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -18,9 +18,23 @@ struct i915_gpu_controller_info; +#if IS_ENABLED(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u8 *mmio, u32 lfb); int i915lightup_ivy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u8 *mmio, u32 lfb); - +#else +static inline int +i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 pio, u8 *mmio, u32 lfb) +{ + return 0; +} +static inline int +i915lightup_ivy(const struct i915_gpu_controller_info *info, + u32 physbase, u16 pio, u8 *mmio, u32 lfb) +{ + return 0; +} +#endif #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */ -- To view, visit https://review.coreboot.org/20925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife9e7f6e61339b201bd3ff42c50f197605a56e00 Gerrit-Change-Number: 20925 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: [RFC] Reinvent I2C ops
by Nico Huber (Code Review) 09 Aug '17

09 Aug '17

Nico Huber has uploaded a new patch set (#4). ( https://review.coreboot.org/20846 ) Change subject: [RFC] Reinvent I2C ops ...................................................................... [RFC] Reinvent I2C ops Do not use the global platform_i2c_transfer() function that can only be implemented by a single driver. Instead, make a `struct device` aware transfer() function the only interface function for I2C controller dri- vers to implement. To not force the slave device drivers to be implemented either above generic I2C or specialized SMBus operations, we support SMBus control- lers in the slave device interface too. We start with four simple slave functions: i2c_readb(), i2c_writeb(), i2c_readb_at() and i2c_writeb_at(). They are all compatible to respec- tive SMBus functions. But we keep aliases because it would be weird to force e.g. an I2C EEPROM driver to call smbus_read_byte(). Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/Makefile.inc M src/device/i2c.c A src/device/i2c_bus.c M src/include/device/i2c_bus.h M src/include/device/i2c_simple.h M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/i2c/lpss_i2c.c M src/soc/intel/common/block/i2c/lpss_i2c.h 8 files changed, 259 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/20846/4 -- To view, visit https://review.coreboot.org/20846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818 Gerrit-Change-Number: 20846 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: [RFC] device/smbus: Reuse I2C bus operations where applicable
by Nico Huber (Code Review) 09 Aug '17

09 Aug '17

Nico Huber has uploaded a new patch set (#2). ( https://review.coreboot.org/20855 ) Change subject: [RFC] device/smbus: Reuse I2C bus operations where applicable ...................................................................... [RFC] device/smbus: Reuse I2C bus operations where applicable Change-Id: I5a93f17b905de38752254891aa4347ba4ed3b205 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/smbus_ops.c M src/include/device/smbus.h 2 files changed, 28 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/20855/2 -- To view, visit https://review.coreboot.org/20855 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5a93f17b905de38752254891aa4347ba4ed3b205 Gerrit-Change-Number: 20855 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit August 2017