coreboot-gerrit July 2017

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Change in coreboot[master]: cpu/x86/name: Fix undefined behavior
by Ryan Salsamendi (Code Review) 02 Jul '17

02 Jul '17

Ryan Salsamendi has uploaded this change for review. ( https://review.coreboot.org/20452 Change subject: cpu/x86/name: Fix undefined behavior ...................................................................... cpu/x86/name: Fix undefined behavior Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that's not aligned to the size of access is undefined behavior. Change-Id: I1362a3eb8c97f5c7e848d75f8d1a219968a7ef9e Signed-off-by: Ryan Salsamendi <rsalsamendi(a)hotmail.com> --- M src/cpu/x86/name/name.c 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/20452/1 diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index b59fd8b..aa1ba7a 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -21,9 +21,8 @@ void fill_processor_name(char *processor_name) { struct cpuid_result regs; - char temp_processor_name[49]; char *processor_name_start; - unsigned int *name_as_ints = (unsigned int *)temp_processor_name; + unsigned int name_as_ints[13]; int i; for (i = 0; i < 3; i++) { @@ -34,10 +33,10 @@ name_as_ints[i * 4 + 3] = regs.edx; } - temp_processor_name[48] = 0; + name_as_ints[12] = 0; /* Skip leading spaces. */ - processor_name_start = temp_processor_name; + processor_name_start = (char *)name_as_ints; while (*processor_name_start == ' ') processor_name_start++; -- To view, visit https://review.coreboot.org/20452 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1362a3eb8c97f5c7e848d75f8d1a219968a7ef9e Gerrit-Change-Number: 20452 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com>

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Change in coreboot[master]: southbridge/intel/lynxpoint: Fix undefined behavior
by build bot (Jenkins) (Code Review) 02 Jul '17

02 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20443 ) Change subject: southbridge/intel/lynxpoint: Fix undefined behavior ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56533/ : SUCCESS -- To view, visit https://review.coreboot.org/20443 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266 Gerrit-Change-Number: 20443 Gerrit-PatchSet: 2 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Jul 2017 01:28:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: northbridge/intel/haswell: Fix undefined behavior
by build bot (Jenkins) (Code Review) 02 Jul '17

02 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20447 ) Change subject: northbridge/intel/haswell: Fix undefined behavior ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56532/ : SUCCESS -- To view, visit https://review.coreboot.org/20447 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56 Gerrit-Change-Number: 20447 Gerrit-PatchSet: 3 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Jul 2017 01:17:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/slippy: Fix misspelled ifdef guard
by build bot (Jenkins) (Code Review) 02 Jul '17

02 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20442 ) Change subject: mainboard/google/slippy: Fix misspelled ifdef guard ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56531/ : SUCCESS -- To view, visit https://review.coreboot.org/20442 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie8347a3eccce51de3e938d0c3c170e59a9f74716 Gerrit-Change-Number: 20442 Gerrit-PatchSet: 2 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 02 Jul 2017 01:15:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/*/cmos: Port USB Always On
by Philipp Deppenwiese (Code Review) 01 Jul '17

01 Jul '17

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/20106 ) Change subject: mb/lenovo/*/cmos: Port USB Always On ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/20106 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281 Gerrit-Change-Number: 20106 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Jul 2017 20:50:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8/smm: Support USB always on AC only
by Philipp Deppenwiese (Code Review) 01 Jul '17

01 Jul '17

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/20450 ) Change subject: ec/lenovo/h8/smm: Support USB always on AC only ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/20450 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib52aab427ff687b00129024cde65b78060d21e32 Gerrit-Change-Number: 20450 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Jul 2017 20:50:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/t400/dock: Control LEDs
by build bot (Jenkins) (Code Review) 01 Jul '17

01 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20327 ) Change subject: mb/lenovo/t400/dock: Control LEDs ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56530/ : SUCCESS -- To view, visit https://review.coreboot.org/20327 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5851f4abcedf4041faae6b3b810102012f488cd Gerrit-Change-Number: 20327 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Jul 2017 19:37:02 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: vendorcode/amd/pi/Lib/amdlib.c: remove StdHeader references
by build bot (Jenkins) (Code Review) 01 Jul '17

01 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20451 ) Change subject: vendorcode/amd/pi/Lib/amdlib.c: remove StdHeader references ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56529/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12112/ : SUCCESS -- To view, visit https://review.coreboot.org/20451 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib13e9209c8119fdcc3720470aaa9dcdbde6ac388 Gerrit-Change-Number: 20451 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Jul 2017 18:30:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: vendorcode/amd/pi/Lib/amdlib.c: remove StdHeader references
by Martin Roth (Code Review) 01 Jul '17

01 Jul '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20451 Change subject: vendorcode/amd/pi/Lib/amdlib.c: remove StdHeader references ...................................................................... vendorcode/amd/pi/Lib/amdlib.c: remove StdHeader references Nothing in the amdlib.c file actually uses the StdHeader structure, so remove the asserts verifying that it's not null, and remove references to it from calls. For now, I've left it in the parameters for the functions for compatibility, but we might want to remove these at some point as well. Change-Id: Ib13e9209c8119fdcc3720470aaa9dcdbde6ac388 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/vendorcode/amd/pi/Lib/amdlib.c 1 file changed, 38 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/20451/1 diff --git a/src/vendorcode/amd/pi/Lib/amdlib.c b/src/vendorcode/amd/pi/Lib/amdlib.c index 03ca207..a5f6898 100644 --- a/src/vendorcode/amd/pi/Lib/amdlib.c +++ b/src/vendorcode/amd/pi/Lib/amdlib.c @@ -605,9 +605,9 @@ UINT32 TempMask; UINT32 Value; LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + LibAmdIoRead (AccessWidth, IoAddress, &Value, NULL); Value = (Value & (~TempMask)) | TempData; - LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader); + LibAmdIoWrite (AccessWidth, IoAddress, &Value, NULL); } /*---------------------------------------------------------------------------------------*/ @@ -639,7 +639,7 @@ UINT32 Value; LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); do { - LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader); + LibAmdIoRead (AccessWidth, IoAddress, &Value, NULL); } while (TempData != (Value & TempMask)); } @@ -744,9 +744,9 @@ UINT32 TempMask; UINT32 Value; LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + LibAmdMemRead (AccessWidth, MemAddress, &Value, NULL); Value = (Value & (~TempMask)) | TempData; - LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader); + LibAmdMemWrite (AccessWidth, MemAddress, &Value, NULL); } /*---------------------------------------------------------------------------------------*/ @@ -778,7 +778,7 @@ UINT32 Value; LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); do { - LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader); + LibAmdMemRead (AccessWidth, MemAddress, &Value, NULL); } while (TempData != (Value & TempMask)); } @@ -807,28 +807,28 @@ UINT64 RMWritePrevious; UINT64 MMIOAddress; - ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); - if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, NULL)) { // We need to convert our "portable" PCI address into a "real" PCI access LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); if (PciAddress.Address.Register <= 0xFF) { - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); - LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL); } else { - LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + LibAmdMsrRead (NB_CFG, &RMWritePrevious, NULL); RMWrite = RMWritePrevious | 0x0000400000000000; - LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); - LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); - LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWrite, NULL); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL); + LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, NULL); } //IDS_HDT_CONSOLE (LIB_PCI_RD, "~PCI RD %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); } else { // Setup the MMIO address ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); - LibAmdMemRead (AccessWidth, MMIOAddress, Value, StdHeader); + LibAmdMemRead (AccessWidth, MMIOAddress, Value, NULL); //IDS_HDT_CONSOLE (LIB_PCI_RD, "~MMIO RD %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); } } @@ -858,21 +858,21 @@ UINT64 RMWritePrevious; UINT64 MMIOAddress; - ASSERT (StdHeader != NULL); + ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO); - if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) { + if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, NULL)) { // We need to convert our "portable" PCI address into a "real" PCI access LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); if (PciAddress.Address.Register <= 0xFF) { - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); - LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL); } else { - LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader); + LibAmdMsrRead (NB_CFG, &RMWritePrevious, NULL); RMWrite = RMWritePrevious | 0x0000400000000000; - LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader); - LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); - LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader); - LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader); + LibAmdMsrWrite (NB_CFG, &RMWrite, NULL); + LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, NULL); + LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, NULL); + LibAmdMsrWrite (NB_CFG, &RMWritePrevious, NULL); } //IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); //printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value); @@ -881,7 +881,7 @@ // Setup the MMIO address ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF))); MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF); - LibAmdMemWrite (AccessWidth, MMIOAddress, Value, StdHeader); + LibAmdMemWrite (AccessWidth, MMIOAddress, Value, NULL); //IDS_HDT_CONSOLE (LIB_PCI_WR, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); //printk(BIOS_DEBUG, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value); //printk(BIOS_DEBUG, "LibAmdPciWrite mmio\n"); @@ -913,9 +913,9 @@ UINT32 TempMask = 0; UINT32 Value; LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); - LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + LibAmdPciRead (AccessWidth, PciAddress, &Value, NULL); Value = (Value & (~TempMask)) | TempData; - LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader); + LibAmdPciWrite (AccessWidth, PciAddress, &Value, NULL); } /*---------------------------------------------------------------------------------------*/ @@ -947,7 +947,7 @@ UINT32 Value; LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask); do { - LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader); + LibAmdPciRead (AccessWidth, PciAddress, &Value, NULL); } while (TempData != (Value & TempMask)); } @@ -973,10 +973,8 @@ UINT32 EncodedSize; UINT64 LocalMsrRegister; - ASSERT (StdHeader != NULL); - MmioIsEnabled = FALSE; - LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader); + LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, NULL); if ((LocalMsrRegister & BIT0) != 0) { *MmioAddress = LocalMsrRegister & 0xFFFFFFFFFFF00000; EncodedSize = (UINT32) ((LocalMsrRegister & 0x3C) >> 2); @@ -1009,7 +1007,7 @@ { ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0); - LibAmdPciRead (AccessWidth32, Address, Value, StdHeader); + LibAmdPciRead (AccessWidth32, Address, Value, NULL); *Value >>= Lowbit; // Shift // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case @@ -1053,10 +1051,10 @@ Mask = (UINT32) 0xFFFFFFFF; } - LibAmdPciRead (AccessWidth32, Address, &Temp, StdHeader); + LibAmdPciRead (AccessWidth32, Address, &Temp, NULL); Temp &= ~(Mask << Lowbit); Temp |= (*Value & Mask) << Lowbit; - LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader); + LibAmdPciWrite (AccessWidth32, Address, &Temp, NULL); } /*---------------------------------------------------------------------------------------*/ @@ -1093,7 +1091,7 @@ Address->AddressValue = (UINT32) ILLEGAL_SBDFO; // Verify that the SBDFO points to a valid PCI device SANITY CHECK - LibAmdPciRead (AccessWidth32, Base, &Temp, StdHeader); + LibAmdPciRead (AccessWidth32, Base, &Temp, NULL); if (Temp == 0xFFFFFFFF) { ASSERT (FALSE); return; // There is no device at this address @@ -1101,7 +1099,7 @@ // Verify that the device supports a capability list TempAddress.AddressValue = Base.AddressValue + 0x04; - LibAmdPciReadBits (TempAddress, 20, 20, &Temp, StdHeader); + LibAmdPciReadBits (TempAddress, 20, 20, &Temp, NULL); if (Temp == 0) { return; // This PCI device does not support capability lists } @@ -1109,11 +1107,11 @@ if (Offset != 0) { // If we are continuing on an existing list TempAddress.AddressValue = Base.AddressValue + Offset; - LibAmdPciReadBits (TempAddress, 15, 8, &Temp, StdHeader); + LibAmdPciReadBits (TempAddress, 15, 8, &Temp, NULL); } else { // We are starting on a new list TempAddress.AddressValue = Base.AddressValue + 0x34; - LibAmdPciReadBits (TempAddress, 7, 0, &Temp, StdHeader); + LibAmdPciReadBits (TempAddress, 7, 0, &Temp, NULL); } if (Temp == 0) { @@ -1152,7 +1150,6 @@ ) { UINT8 *Dest; - ASSERT (StdHeader != NULL); Dest = Destination; while ((FillLength--) != 0) { *Dest++ = Value; @@ -1179,7 +1176,6 @@ { UINT8 *Dest; CONST UINT8 *SourcePtr; - ASSERT (StdHeader != NULL); Dest = Destination; SourcePtr = Source; while ((CopyLength--) != 0) { @@ -1287,7 +1283,7 @@ UINT32 ProcessorPackageType; CPUID_DATA CpuId; - LibAmdCpuidRead (0x80000001, &CpuId, StdHeader); + LibAmdCpuidRead (0x80000001, &CpuId, NULL); ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 return (UINT32) (1 << ProcessorPackageType); } -- To view, visit https://review.coreboot.org/20451 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib13e9209c8119fdcc3720470aaa9dcdbde6ac388 Gerrit-Change-Number: 20451 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mb/lenovo/*/cmos: Port USB Always On
by build bot (Jenkins) (Code Review) 01 Jul '17

01 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20106 ) Change subject: mb/lenovo/*/cmos: Port USB Always On ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56528/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12111/ : SUCCESS -- To view, visit https://review.coreboot.org/20106 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281 Gerrit-Change-Number: 20106 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Jul 2017 17:46:16 +0000 Gerrit-HasComments: No

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coreboot-gerrit July 2017