coreboot-gerrit July 2017

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Change in coreboot[master]: southbridge/intel/lynxpoint: Fix undefined behavior
by Ryan Salsamendi (Code Review) 01 Jul '17

01 Jul '17

Ryan Salsamendi has uploaded this change for review. ( https://review.coreboot.org/20446 Change subject: southbridge/intel/lynxpoint: Fix undefined behavior ...................................................................... southbridge/intel/lynxpoint: Fix undefined behavior Fixes report found by undefined behavior sanitizer. Dereferencing a pointer that is not aligned to the size of access is undefined behavior. Change-Id: Ia3c95e36e8b7f88ed69d5339e299c40934cb87da Signed-off-by: Ryan Salsamendi <rsalsamendi(a)hotmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/20446/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6c4acd8..37cd94b 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -277,9 +277,9 @@ reg32 |= (1 << 4)|(1 << 5)|(1 << 0); RCBA32(0x3310) = reg32; - reg32 = RCBA32(0x3f02); - reg32 &= ~0xf; - RCBA32(0x3f02) = reg32; + reg16 = RCBA16(0x3f02); + reg16 &= ~0xf; + RCBA16(0x3f02) = reg16; } static void pch_rtc_init(struct device *dev) -- To view, visit https://review.coreboot.org/20446 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia3c95e36e8b7f88ed69d5339e299c40934cb87da Gerrit-Change-Number: 20446 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com>

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Change in coreboot[master]: northbridge/intel/haswell: Fix copy paste error
by build bot (Jenkins) (Code Review) 01 Jul '17

01 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20445 ) Change subject: northbridge/intel/haswell: Fix copy paste error ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56511/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/12096/ : SUCCESS -- To view, visit https://review.coreboot.org/20445 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48866d9243c2a576a02519724429801ae47c5644 Gerrit-Change-Number: 20445 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Jul 2017 00:48:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: northbridge/intel/haswell: Fix copy paste error
by Ryan Salsamendi (Code Review) 01 Jul '17

01 Jul '17

Ryan Salsamendi has uploaded this change for review. ( https://review.coreboot.org/20445 Change subject: northbridge/intel/haswell: Fix copy paste error ...................................................................... northbridge/intel/haswell: Fix copy paste error DIMMB's DDR width is in bit 20, not bit 19. Change-Id: I48866d9243c2a576a02519724429801ae47c5644 Signed-off-by: Ryan Salsamendi <rsalsamendi(a)hotmail.com> --- M src/northbridge/intel/haswell/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/20445/1 diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index aa07f16..e48cca9 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -104,7 +104,7 @@ ((ch_conf >> 16) & 1) ? "" : ", selected"); printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", + ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", ((ch_conf >> 18) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? ", selected" : ""); } -- To view, visit https://review.coreboot.org/20445 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I48866d9243c2a576a02519724429801ae47c5644 Gerrit-Change-Number: 20445 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com>

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Change in coreboot[master]: northbridge/intel/haswell: Fix undefined behavior.
by Ryan Salsamendi (Code Review) 01 Jul '17

01 Jul '17

Ryan Salsamendi has uploaded this change for review. ( https://review.coreboot.org/20444 Change subject: northbridge/intel/haswell: Fix undefined behavior. ...................................................................... northbridge/intel/haswell: Fix undefined behavior. Fix reports found by undefined behavior sanitizer. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56 Signed-off-by: Ryan Salsamendi <rsalsamendi(a)hotmail.com> --- M src/drivers/intel/gma/i915_reg.h M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/northbridge.c 3 files changed, 12 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/20444/1 diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index dee6865..e88ecfb 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -2979,7 +2979,7 @@ /* Ironlake */ #define CPU_VGACNTRL 0x41000 -#define CPU_VGA_DISABLE (1<<31) +#define CPU_VGA_DISABLE (1UL<<31) #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) @@ -4177,7 +4177,7 @@ #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ -#define HSW_PWR_WELL_ENABLE (1<<31) +#define HSW_PWR_WELL_ENABLE (1UL<<31) #define HSW_PWR_WELL_STATE (1<<30) #define HSW_PWR_WELL_CTL5 0x45410 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f22ff48..75f3b7a 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -252,13 +252,13 @@ gtt_write_regs(haswell_gt_setup); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1 << 31), (0 << 31)); + gtt_poll(0x138124, (1UL << 31), (0UL << 31)); /* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); /* Mailbox Command */ gtt_write(0x138124, 0x80000004); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1 << 31), (0 << 31)); + gtt_poll(0x138124, (1UL << 31), (0UL << 31)); /* Enable PM Interrupts */ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a8c8015..df3916b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -36,6 +36,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; + u32 mask; *base = 0; *len = 0; @@ -47,15 +48,19 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + mask = ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + mask = ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + mask = ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27); + mask |= (1 << 26)); + *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024; return 1; } -- To view, visit https://review.coreboot.org/20444 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56 Gerrit-Change-Number: 20444 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com>

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Change in coreboot[master]: southbridge/intel/lynxpoint: Fix undefined behavior.
by build bot (Jenkins) (Code Review) 01 Jul '17

01 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20443 ) Change subject: southbridge/intel/lynxpoint: Fix undefined behavior. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56509/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12094/ : SUCCESS -- To view, visit https://review.coreboot.org/20443 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266 Gerrit-Change-Number: 20443 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Jul 2017 00:23:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: southbridge/intel/lynxpoint: Fix undefined behavior.
by Ryan Salsamendi (Code Review) 01 Jul '17

01 Jul '17

Ryan Salsamendi has uploaded this change for review. ( https://review.coreboot.org/20443 Change subject: southbridge/intel/lynxpoint: Fix undefined behavior. ...................................................................... southbridge/intel/lynxpoint: Fix undefined behavior. Fix reports found by undefined behavior sanitizer. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266 Signed-off-by: Ryan Salsamendi <rsalsamendi(a)hotmail.com> --- M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/usb_xhci.c 7 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20443/1 diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 35dc63c..0b1acdd 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -48,7 +48,7 @@ u16 reg16; u32 reg32; - if (RCBA32(0x2030) & (1 << 31)) { + if (RCBA32(0x2030) & (1UL << 31)) { reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 25); @@ -72,9 +72,9 @@ (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); if (pch_is_lp()) - reg32 &= ~(1 << 31); + reg32 &= ~(1UL << 31); else - reg32 |= (1 << 31); + reg32 |= (1UL << 31); pci_write_config32(dev, 0x120, reg32); } @@ -101,7 +101,7 @@ if (!pch_is_lp()) { reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1 << 31); + reg32 &= ~(1UL << 31); pci_write_config32(dev, 0xd0, reg32); } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d295c88..6c4acd8 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -429,7 +429,7 @@ reg32 = RCBA32(CG); reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1 << 31); // LPC Dynamic + reg32 |= (1UL << 31); // LPC Dynamic reg32 |= (1 << 16); // PCIe Dynamic reg32 |= (1 << 27); // HPET Dynamic reg32 |= (1 << 28); // GPIO Dynamic diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8cae50a..d76faf7 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -547,7 +547,7 @@ #define RPFN 0x0404 /* 32bit */ /* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) +#define RPFN_HIDE(port) (1UL << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) /* Set the function number for a Root Port */ diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 3fd8d1e..3d01cd6 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -608,7 +608,7 @@ pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11)); pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); + pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 90045d1..d895c56 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -45,7 +45,7 @@ return; for (i=31; i>=0; i--) { - if (status & (1 << i)) { + if (status & (1UL << i)) { if (bit_names[i]) printk(BIOS_DEBUG, "%s ", bit_names[i]); else diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 98cd0bc..31081d7 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -297,7 +297,7 @@ reg32 = pci_read_config32(dev, 0x300); reg32 |= (1 << 17) | (1 << 16); - reg32 |= (1 << 31) | (1 << 30) | (1 << 29); + reg32 |= (1UL << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); } diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 0acf35f..28e6521 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -342,13 +342,13 @@ /* D20:F0:44h[31] = 1 (Access Control Bit) */ reg32 = pci_read_config32(dev, 0x44); - reg32 |= (1 << 31); + reg32 |= (1UL << 31); pci_write_config32(dev, 0x44, reg32); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ - reg32 |= (1 << 31); + reg32 |= (1UL << 31); pci_write_config32(dev, 0x40, reg32); if (acpi_is_wakeup_s3()) { -- To view, visit https://review.coreboot.org/20443 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266 Gerrit-Change-Number: 20443 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com>

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Change in coreboot[master]: mainboard/google/slippy: Fix misspelled ifdef guard.
by build bot (Jenkins) (Code Review) 01 Jul '17

01 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20442 ) Change subject: mainboard/google/slippy: Fix misspelled ifdef guard. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56508/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12093/ : SUCCESS -- To view, visit https://review.coreboot.org/20442 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie8347a3eccce51de3e938d0c3c170e59a9f74716 Gerrit-Change-Number: 20442 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 01 Jul 2017 00:04:31 +0000 Gerrit-HasComments: No

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coreboot-gerrit July 2017