Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19900 )
Change subject: purism/librem13: Disable L1 sub states support
......................................................................
purism/librem13: Disable L1 sub states support
Some NVMe devices (Intel 600p series for example) seem to lock up
in D3 drive power state (L1.2 PCIe power state).
Disabling L1 substates fixes it.
Change-Id: I00a327dc91d443beb565fe4e72aaf816e40a007c
Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm>
---
M src/mainboard/purism/librem13/Kconfig
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/19900/1
diff --git a/src/mainboard/purism/librem13/Kconfig b/src/mainboard/purism/librem13/Kconfig
index 747e5ad..e63a7a1 100644
--- a/src/mainboard/purism/librem13/Kconfig
+++ b/src/mainboard/purism/librem13/Kconfig
@@ -21,6 +21,9 @@
This platform does not have any way to get standard
serial output so disable it by default.
+config PCIEXP_L1_SUB_STATE
+ def_bool n
+
config HAVE_IFD_BIN
bool
default n
--
To view, visit https://review.coreboot.org/19900
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: I00a327dc91d443beb565fe4e72aaf816e40a007c
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>
Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19899 )
Change subject: soc/broadwell: Allow disabling of PCIe ASPM options
......................................................................
soc/broadwell: Allow disabling of PCIe ASPM options
The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM)
are hardcoded for broadwell chips, but some boards may not support
these ASPM options even if the SoC does support it (non-wired CLKREQ
pin for example).
This is required to disable L1 substates on the Purism/Librem 13 which
seems to have issues with NVMe drives falling into L1.2 state and not
being able to exit that state.
Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34
Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm>
---
M src/soc/intel/broadwell/Kconfig
1 file changed, 16 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/19899/1
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 34f515f..5132201 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -27,10 +27,6 @@
select RELOCATABLE_RAMSTAGE
select REG_SCRIPT
select PARALLEL_MP
- select PCIEXP_ASPM
- select PCIEXP_COMMON_CLOCK
- select PCIEXP_CLK_PM
- select PCIEXP_L1_SUB_STATE
select RTC
select SMM_TSEG
select SMP
@@ -46,6 +42,22 @@
select HAVE_SPI_CONSOLE_SUPPORT
select CPU_INTEL_COMMON
+config PCIEXP_ASPM
+ bool
+ default y
+
+config PCIEXP_COMMON_CLOCK
+ bool
+ default y
+
+config PCIEXP_CLK_PM
+ bool
+ default y
+
+config PCIEXP_L1_SUB_STATE
+ bool
+ default y
+
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
--
To view, visit https://review.coreboot.org/19899
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>