coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: pciexp_device: Remove useless write on a read-only register
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19901 ) Change subject: pciexp_device: Remove useless write on a read-only register ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54324/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/10053/ : SUCCESS -- To view, visit https://review.coreboot.org/19901 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: pciexp_device: Prevent race condition with retrain link
by Youness Alaoui (Code Review) 25 May '17

25 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19556 to look at the new patch set (#3). Change subject: pciexp_device: Prevent race condition with retrain link ...................................................................... pciexp_device: Prevent race condition with retrain link The PCIe specification[1] describes a race condition that can occur when using the Retrain Link bit in the Link Control Register. The race condition is avoided by checking the retrain link bit in the link status register and waiting until it is set to 0, before initiating a new link retraining. [1] PCI Express Base Specification Revision 3.0 Page 633 Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/device/pciexp_device.c 1 file changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/19556/3 -- To view, visit https://review.coreboot.org/19556 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/x4x: DDR3 JEDEC init
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19877 ) Change subject: nb/intel/x4x: DDR3 JEDEC init ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10047/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54318/ : SUCCESS -- To view, visit https://review.coreboot.org/19877 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3b5eeb0aff6764292bbcbed7274274f615066c14 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS t...
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19879 ) Change subject: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS training ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10049/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54320/ : SUCCESS -- To view, visit https://review.coreboot.org/19879 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I806840445b5e768d079910fb9870a2cee7b9f1ca Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Add write leveling
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19878 ) Change subject: [WIP]nb/intel/x4x/raminit: Add write leveling ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10048/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54319/ : SUCCESS -- To view, visit https://review.coreboot.org/19878 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibfbaa235bc4eb08e9345321b851e880390a624e8 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: DDR3 specific ODT
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19876 ) Change subject: nb/intel/x4x/raminit: DDR3 specific ODT ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10046/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54316/ : SUCCESS -- To view, visit https://review.coreboot.org/19876 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x: Add DDR3 rcomp
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19875 ) Change subject: nb/intel/x4x: Add DDR3 rcomp ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10045/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54317/ : SUCCESS -- To view, visit https://review.coreboot.org/19875 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: console/flashsconsole: Add spi flash console for debugging
by build bot (Jenkins) (Code Review) 25 May '17

25 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19849 ) Change subject: console/flashsconsole: Add spi flash console for debugging ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10043/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54314/ : SUCCESS -- To view, visit https://review.coreboot.org/19849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 25 May '17

25 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19759 to look at the new patch set (#10). Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio ...................................................................... soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- A src/soc/intel/common/block/gpio/Kconfig A src/soc/intel/common/block/gpio/Makefile.inc A src/soc/intel/common/block/gpio/gpio.c A src/soc/intel/common/block/include/intelblocks/gpio.h A src/soc/intel/common/block/include/intelblocks/gpio_defs.h 5 files changed, 801 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/19759/10 -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: pciexp_device: Remove useless write on a read-only register
by Youness Alaoui (Code Review) 25 May '17

25 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19901 ) Change subject: pciexp_device: Remove useless write on a read-only register ...................................................................... pciexp_device: Remove useless write on a read-only register The Role-Based Error Reporting is not a configurable field, it's a read only field in the Device Capability register. This code was old and comes from commit f6eb88ad but evidently is not useful in any way. The PCIe Specification [1] states that it's read-only and must always be set to 1. I have also done tests on purism/librem13 hardware, trying to change that value, without any success. [1]: PCI Express Base Specification Revision 3.0 Page 612 Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/device/pciexp_device.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/19901/1 diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index fb2a284..bb9f9e3 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -362,11 +362,6 @@ lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); lnkctl |= apmc; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); - - /* Enable ASPM role based error reporting. */ - devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); - devcap |= PCI_EXP_DEVCAP_RBER; - pci_write_config32(endp, endp_cap + PCI_EXP_DEVCAP, devcap); } printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); -- To view, visit https://review.coreboot.org/19901 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I729617a5c6f4f52dfc4c422df78379b309066399 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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coreboot-gerrit May 2017