coreboot-gerrit May 2017

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Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Add write leveling
by Arthur Heymans (Code Review) 24 May '17

24 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19878 to look at the new patch set (#3). Change subject: [WIP]nb/intel/x4x/raminit: Add write leveling ...................................................................... [WIP]nb/intel/x4x/raminit: Add write leveling Does not work!! Change-Id: Ibfbaa235bc4eb08e9345321b851e880390a624e8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Makefile.inc A src/northbridge/intel/x4x/dq_dqs_dll.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/spd_ddr3_decode.c M src/northbridge/intel/x4x/x4x.h 6 files changed, 496 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/19878/3 -- To view, visit https://review.coreboot.org/19878 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ibfbaa235bc4eb08e9345321b851e880390a624e8 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS t...
by Arthur Heymans (Code Review) 24 May '17

24 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19879 to look at the new patch set (#3). Change subject: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS training ...................................................................... [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS training This is not DDR3 specific. Change-Id: I806840445b5e768d079910fb9870a2cee7b9f1ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/dq_dqs_dll.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/x4x.h 3 files changed, 456 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/19879/3 -- To view, visit https://review.coreboot.org/19879 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I806840445b5e768d079910fb9870a2cee7b9f1ca Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/x4x/raminit: Support programming initials DD3 DLL s...
by Arthur Heymans (Code Review) 24 May '17

24 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19874 to look at the new patch set (#3). Change subject: nb/intel/x4x/raminit: Support programming initials DD3 DLL setting ...................................................................... nb/intel/x4x/raminit: Support programming initials DD3 DLL setting Due to shear amount of tables for default DLL settings used, they are mostly pushed to a new file to avoid cluttering up the raminit. Also saves these default DQ and DQS dll settings in sysinfo stuct for later use. Change-Id: Ia79b216ad69a02d4706ffc74f867a85db3eb2d6c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Makefile.inc M src/northbridge/intel/x4x/raminit_ddr23.c A src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/x4x.h 4 files changed, 475 insertions(+), 136 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/19874/3 -- To view, visit https://review.coreboot.org/19874 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia79b216ad69a02d4706ffc74f867a85db3eb2d6c Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: console/flashsconsole: Add spi flash console for debugging
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/19849 ) Change subject: console/flashsconsole: Add spi flash console for debugging ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/19849/8/src/drivers/spi/flashconsole.c File src/drivers/spi/flashconsole.c: Line 79: if (rdev_readat(rdev, buffer, offset, len)) > rdev_readat() and rdev_writeat() return the length on success, < 0 on error :facepalm: I guess it's time to call it a day. Fixed. -- To view, visit https://review.coreboot.org/19849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: console/flashsconsole: Add spi flash console for debugging
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19849 to look at the new patch set (#9). Change subject: console/flashsconsole: Add spi flash console for debugging ...................................................................... console/flashsconsole: Add spi flash console for debugging If CONSOLE_SPI_FLASH config is enabled, we can write the cbmem messages to the 'CONSOLE' area in FMAP if the area is defined or to the 'console' fil in CBFS which allows us to grab the log when we read the flash. This is useful when you don't have usb debugging, and UART lines are hard to find. Since a failure to boot would require a hardware flasher anyways, we can get the log at the same time. This feature should only be used when no alternative is found and only when we can't boot the system, because excessive writes to the flash is not recommended. This has been tested on purism/librem13 v2 and librem 15 v3 which run Intel Skylake hardware. It has not been tested on other archs or with a driver other than the fast_spi. Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/console/Kconfig M src/console/console.c M src/drivers/spi/Makefile.inc A src/drivers/spi/flashconsole.c A src/include/console/flash.h 5 files changed, 278 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19849/9 -- To view, visit https://review.coreboot.org/19849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: purism/librem13v2: ec: fix EC_SCI_GPI value
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19898 to review the following change. Change subject: purism/librem13v2: ec: fix EC_SCI_GPI value ...................................................................... purism/librem13v2: ec: fix EC_SCI_GPI value current value was copied from v1 board, use value obtained from AMI firmware. Observe Windows boots correctly, function keys work in both Windows and Linux Change-Id: Iaadc9005d8f0131ed7476853e7f87052d43032b0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/19898/1 diff --git a/src/mainboard/purism/librem13v2/acpi/ec.asl b/src/mainboard/purism/librem13v2/acpi/ec.asl index cf8b9a9..4215213 100644 --- a/src/mainboard/purism/librem13v2/acpi/ec.asl +++ b/src/mainboard/purism/librem13v2/acpi/ec.asl @@ -13,6 +13,6 @@ * GNU General Public License for more details. */ -#define EC_SCI_GPI 10 +#define EC_SCI_GPI 0x50 #include <ec/purism/librem/acpi/ec.asl> -- To view, visit https://review.coreboot.org/19898 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iaadc9005d8f0131ed7476853e7f87052d43032b0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: ec/librem/ec: fix offset for Bluetooth enable (BTLE)
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19897 to review the following change. Change subject: ec/librem/ec: fix offset for Bluetooth enable (BTLE) ...................................................................... ec/librem/ec: fix offset for Bluetooth enable (BTLE) Verify BT function key toggle works correctly Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/purism/librem/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/19897/1 diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index c87a4f7..e95f126 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -59,7 +59,7 @@ Offset (0x1D), TPAD, 1, /* Touchpad Enable/Disable */ WIFI, 1, /* WiFi Enable/Disable */ - , 2, + , 3, BTLE, 1, /* Bluetooth Enable/Disable */ Offset (0x25), , 5, -- To view, visit https://review.coreboot.org/19897 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I68dc99e72a09f7affbcd691d03dd4607a898313e Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: devicetree cleanup
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19896 to review the following change. Change subject: purism/librem13v2: devicetree cleanup ...................................................................... purism/librem13v2: devicetree cleanup disable DSP - not needed/used set InternalGfx to default (1) since doesn't seem to matter Disable PCI CLKREQ - fix hang on suspend due to wifi remove TCC offset for -Y SoCs set VrMbxCmd for U-series SoCs (Sentry, Kunimitsu) Change-Id: If65fb0f23f71bea5d7c5f69b1cffe3a0a90c7f72 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/devicetree.cb 1 file changed, 4 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19896/1 diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index 5024cd1..f656fa8 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -34,7 +34,7 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" register "EnableAzalia" = "1" - register "DspEnable" = "1" + register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" register "XdciEnable" = "0" @@ -46,7 +46,7 @@ register "ScsSdCardEnabled" = "0" register "IshEnable" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "0" + register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" @@ -150,12 +150,6 @@ # Enable Root port 5 and 9 register "PcieRpEnable[4]" = "1" register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - #register "PcieRpClkReqSupport[8]" = "1" - # Default value from FSP programming guide - register "PcieRpClkReqNumber[4]" = "3" - #register "PcieRpClkReqNumber[8]" = "5" register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) @@ -170,10 +164,8 @@ # PL2 override 25W register "tdp_pl2_override" = "25" - register "tcc_offset" = "10" # TCC of 90C - - # Send an extra VR mailbox command for the supported MPS IMVP8 model - register "SendVrMbxCmd" = "1" + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" device cpu_cluster 0 on device lapic 0 on end -- To view, visit https://review.coreboot.org/19896 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If65fb0f23f71bea5d7c5f69b1cffe3a0a90c7f72 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: fix HDA verb values, use azalia macros
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19895 to review the following change. Change subject: purism/librem13v2: fix HDA verb values, use azalia macros ...................................................................... purism/librem13v2: fix HDA verb values, use azalia macros use values from AMI firmware, other coreboot boards with Realtek ALC269 as reference. Fixes headphone jack detection. Change-Id: I500e7bcad0a5eba5676e9e1afbef3914ee450e9e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/hda_verb.h 1 file changed, 17 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/19895/1 diff --git a/src/mainboard/purism/librem13v2/hda_verb.h b/src/mainboard/purism/librem13v2/hda_verb.h index d76cc17..323ee9a 100644 --- a/src/mainboard/purism/librem13v2/hda_verb.h +++ b/src/mainboard/purism/librem13v2/hda_verb.h @@ -25,10 +25,10 @@ 0x19910269, /* Subsystem ID */ 0x0000000c, /* Number of jacks (NID entries) */ - 0x0017ff00, /* Function Reset */ - 0x0017ff00, /* Double Function Reset */ - 0x0017ff00, - 0x0017ff00, + 0x0017ff00, // Function Reset + 0x0017ff00, // Double Function Reset + 0x000F0000, // Pad - get vendor id + 0x000F0002, // Pad - get revision id /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ @@ -36,72 +36,39 @@ /* Bits 7:0 - Payload */ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ - 0x00172069, - 0x00172102, - 0x00172291, - 0x00172319, + AZALIA_SUBVENDOR(0x0, 0x19910269), /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) */ - 0x01271c00, - 0x01271d00, - 0x01271e00, - 0x01271f40, + AZALIA_PIN_CFG(0x0, 0x12, 0x40000000), /* Pin Complex (NID 0x14) */ - 0x01471c10, - 0x01471d01, - 0x01471e17, - 0x01471f90, + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* Pin Complex (NID 0x15) */ + AZALIA_PIN_CFG(0x0, 0x15, 0x04214020), /* Pin Complex (NID 0x17) */ - 0x01771cf0, - 0x01771d11, - 0x01771e11, - 0x01771f41, + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), /* Pin Complex (NID 0x18) */ - 0x01871c20, - 0x01871d10, - 0x01871ea1, - 0x01871f04, + AZALIA_PIN_CFG(0x0, 0x18, 0x04a19040), /* Pin Complex (NID 0x19) */ - 0x01971c30, - 0x01971d01, - 0x01971ea7, - 0x01971f90, + AZALIA_PIN_CFG(0x0, 0x19, 0x90a70130), /* Pin Complex (NID 0x1A) */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), /* Pin Complex (NID 0x1B) */ - 0x01b71cf0, - 0x01b71d11, - 0x01b71e11, - 0x01b71f41, + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), /* Pin Complex (NID 0x1D) */ - 0x01d71c05, - 0x01d71d9d, - 0x01d71e56, - 0x01d71f40, + AZALIA_PIN_CFG(0x0, 0x1D, 0x40548505), /* Pin Complex (NID 0x1E) */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, - - /* Pin Complex (NID 0x21) */ - 0x02171c1f, - 0x02171d10, - 0x02171e21, - 0x02171f04, + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), }; const u32 pc_beep_verbs[] = { -- To view, visit https://review.coreboot.org/19895 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I500e7bcad0a5eba5676e9e1afbef3914ee450e9e Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: devicetree: set pl2 value
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19894 to review the following change. Change subject: purism/librem13v2: devicetree: set pl2 value ...................................................................... purism/librem13v2: devicetree: set pl2 value use 25W value from other U-series SKL SoCs Change-Id: Icfd5657f2bf04f7fae267226ee922bf635134828 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/19894/1 diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index 7f0424c..5024cd1 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -167,8 +167,8 @@ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - # PL2 override 15W - register "tdp_pl2_override" = "15" + # PL2 override 25W + register "tdp_pl2_override" = "25" register "tcc_offset" = "10" # TCC of 90C -- To view, visit https://review.coreboot.org/19894 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Icfd5657f2bf04f7fae267226ee922bf635134828 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit May 2017