coreboot-gerrit May 2017

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Change in coreboot[master]: purism/librem13v2: Fix GPIO settings and enable P2SB device
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19892 ) Change subject: purism/librem13v2: Fix GPIO settings and enable P2SB device ...................................................................... purism/librem13v2: Fix GPIO settings and enable P2SB device Some GPIOs were not matching exactly with the GPIO settings from the factory BIOS and the P2SB device being disabled (which I was confusing with hidden) was causing all sorts of problems. Change-Id: I2622ce81250dacdc06b1e64f2970eaef901d0bf3 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem13v2/devicetree.cb M src/mainboard/purism/librem13v2/gpio.h 2 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/19892/1 diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index f37882a..7f6bcae 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -207,7 +207,7 @@ device pnp 0c09.0 on end end end # LPC Interface - device pci 1f.1 off end # P2SB + device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus diff --git a/src/mainboard/purism/librem13v2/gpio.h b/src/mainboard/purism/librem13v2/gpio.h index 01540b5..1f2c943 100644 --- a/src/mainboard/purism/librem13v2/gpio.h +++ b/src/mainboard/purism/librem13v2/gpio.h @@ -26,7 +26,7 @@ #define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \ _PAD_CFG_ATTRS(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, \ - NO, NO, NO, NO, func_, NO, NO), PAD_FIELD(PAD_TOL, 1V8)) + NO, NO, NO, NO, func_, YES, YES), PAD_FIELD(PAD_TOL, 1V8)) /* Redefine PAD_CFG_GPI using DRIVE0 RXEVCFG value */ #undef PAD_CFG_GPI @@ -205,7 +205,7 @@ /* USB2_OC3# */ PAD_CFG_NC(GPP_E12), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_NC_EVCFG(GPP_E15, EDGE, 0), +/* DDPD_HPD2 */ PAD_CFG_NC_RXINV(GPP_E15, EDGE), /* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NO), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), @@ -247,19 +247,19 @@ /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PU, DEEP, NF1), /* BATLOW# */ PAD_CFG_NC(GPD0), -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, RSMRST, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DSW_PWROK, NF1), /* LAN_WAKE# */ PAD_CFG_NC_EVCFG(GPD2, LEVEL, 0), -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, RSMRST, NF1), -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), -/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), -/* RSVD */ PAD_CFG_NC(GPD7), -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), -/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), -/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), +/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DSW_PWROK, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DSW_PWROK, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DSW_PWROK, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DSW_PWROK, NF1), +/* RSVD */ PAD_CFG_NC_1(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DSW_PWROK, NF1), +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DSW_PWROK, NF1), +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DSW_PWROK, NF1), /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; -- To view, visit https://review.coreboot.org/19892 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I2622ce81250dacdc06b1e64f2970eaef901d0bf3 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: Fix NVMe and enable USB OTG
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19893 ) Change subject: purism/librem13v2: Fix NVMe and enable USB OTG ...................................................................... purism/librem13v2: Fix NVMe and enable USB OTG NVMe device doesn't work if the ClkReq value is set Change-Id: I7f12c297fd789762e6e2cb7eb12b835109e2ed0c Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem13v2/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/19893/1 diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index 7f6bcae..7f0424c 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -152,10 +152,10 @@ register "PcieRpEnable[8]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqSupport[8]" = "1" + #register "PcieRpClkReqSupport[8]" = "1" # Default value from FSP programming guide register "PcieRpClkReqNumber[4]" = "3" - register "PcieRpClkReqNumber[8]" = "5" + #register "PcieRpClkReqNumber[8]" = "5" register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) @@ -182,7 +182,7 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) + device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 -- To view, visit https://review.coreboot.org/19893 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I7f12c297fd789762e6e2cb7eb12b835109e2ed0c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: Add support for NVMe devices
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19891 ) Change subject: purism/librem13v2: Add support for NVMe devices ...................................................................... purism/librem13v2: Add support for NVMe devices NVMe devices on the M.2 connector appear on the PCIe port #9 Change-Id: Icdc7f372c761001ae39143474b3c8c10a173ba67 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem13v2/Kconfig M src/mainboard/purism/librem13v2/devicetree.cb 2 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/19891/1 diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig index 7a69104..8f74e8d 100644 --- a/src/mainboard/purism/librem13v2/Kconfig +++ b/src/mainboard/purism/librem13v2/Kconfig @@ -2,6 +2,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index ece7a4e..f37882a 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -29,10 +29,10 @@ register "ProbelessTrace" = "0" register "EnableLan" = "0" register "EnableSata" = "1" - register "SataSalpSupport" = "0" + register "SataSalpSupport" = "1" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "0" @@ -147,12 +147,15 @@ .voltage_limit = 1520, }" - # Enable Root port 5 + # Enable Root port 5 and 9 register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" # Enable CLKREQ# - register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[8]" = "1" # Default value from FSP programming guide register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkReqNumber[8]" = "5" register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) @@ -195,7 +198,7 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 -- To view, visit https://review.coreboot.org/19891 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Icdc7f372c761001ae39143474b3c8c10a173ba67 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: various devicetree fixes
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19887 to review the following change. Change subject: purism/librem13v2: various devicetree fixes ...................................................................... purism/librem13v2: various devicetree fixes Also remove a couple of useless uart config options and only configure SPD data for the first DIMM channel. Change-Id: Id03b1b6abcc8bb326ee7c2484c273422325b34ab Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/Kconfig M src/mainboard/purism/librem13v2/devicetree.cb M src/mainboard/purism/librem13v2/romstage.c 3 files changed, 20 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/19887/1 diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig index a61cea1..68e7aa4 100644 --- a/src/mainboard/purism/librem13v2/Kconfig +++ b/src/mainboard/purism/librem13v2/Kconfig @@ -3,8 +3,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ROMSIZE_KB_16384 - select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_NAU8825 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MONOTONIC_TIMER_MSR diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index e51713b..3956a15 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -46,7 +46,7 @@ register "ScsSdCardEnabled" = "0" register "IshEnable" = "0" register "PttSwitch" = "0" - register "InternalGfx" = "1" + register "InternalGfx" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" @@ -57,7 +57,7 @@ register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "PmTimerDisabled" = "1" + register "PmTimerDisabled" = "0" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" @@ -147,44 +147,24 @@ .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 and 5. register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[4]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# - register "PcieRpClkReqNumber[0]" = "1" + # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# + # register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkReqNumber[4]" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2 + register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # SD + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD - - register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, - [PchSerialIoIndexUart1] = PchSerialIoDisabled, - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, - }" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port # PL2 override 15W register "tdp_pl2_override" = "15" @@ -209,16 +189,11 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA - device pci 1c.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW0_16" - device pci 00.0 on end - end - end # PCI Express Port 1 + device pci 1c.0 off end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.4 on end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 diff --git a/src/mainboard/purism/librem13v2/romstage.c b/src/mainboard/purism/librem13v2/romstage.c index 3505467..0860770 100644 --- a/src/mainboard/purism/librem13v2/romstage.c +++ b/src/mainboard/purism/librem13v2/romstage.c @@ -41,14 +41,11 @@ get_spd_smbus(&blk); dump_spd_info(&blk); memory_params->MemorySpdDataLen = blk.len; - if (blk.spd_array[0][0] != 0) + if (blk.spd_array[0] != 0) memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0]; - if (blk.spd_array[1][0] != 0) - memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1]; - if (blk.spd_array[2][0] != 0) - memory_params->MemorySpdPtr01 = (u32)blk.spd_array[2]; - if (blk.spd_array[3][0] != 0) - memory_params->MemorySpdPtr11 = (u32)blk.spd_array[3]; + memory_params->MemorySpdPtr01 = 0; + memory_params->MemorySpdPtr10 = 0; + memory_params->MemorySpdPtr11 = 0; memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], sizeof(params->pei_data->dq_map[0])); -- To view, visit https://review.coreboot.org/19887 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Id03b1b6abcc8bb326ee7c2484c273422325b34ab Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: devicetree - fix wifi
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19888 to review the following change. Change subject: purism/librem13v2: devicetree - fix wifi ...................................................................... purism/librem13v2: devicetree - fix wifi The PCIe wifi adapter is attached to PCIe root port 5 at 1c.0. coreboot labels this as root port 1, may be board specific? Set RP5 CLKREQ value to default from FSP programming guide. Change-Id: If665caa19cfdd01b1241b548c9062a2417eae238 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/devicetree.cb 1 file changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/19888/1 diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index 3956a15..39333a2 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -147,14 +147,12 @@ .voltage_limit = 1520, }" - # Enable Root port 1 and 5. - register "PcieRpEnable[0]" = "1" + # Enable Root port 5 register "PcieRpEnable[4]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# - # register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "1" + # Default value from FSP programming guide + register "PcieRpClkReqNumber[4]" = "3" register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right) @@ -189,11 +187,11 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA - device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 -- To view, visit https://review.coreboot.org/19888 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If665caa19cfdd01b1241b548c9062a2417eae238 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: Add audio support
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19890 ) Change subject: purism/librem13v2: Add audio support ...................................................................... purism/librem13v2: Add audio support Initialize the audio codec without depending on DSP binary blobs. The hda_verb.c was copied from the intel/kblrvp rvp7 variant, and the hda_verb.h file was copied from the purism/librem13. The IoBufferOwnership FSP option in devicetree has to be 0 for the azalia driver to work. Change-Id: I619a6bdd0bc01b9c99291b77b0ef52d3be3b79c0 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem13v2/Makefile.inc M src/mainboard/purism/librem13v2/devicetree.cb A src/mainboard/purism/librem13v2/hda_verb.c A src/mainboard/purism/librem13v2/hda_verb.h D src/mainboard/purism/librem13v2/mainboard.c 5 files changed, 195 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/19890/1 diff --git a/src/mainboard/purism/librem13v2/Makefile.inc b/src/mainboard/purism/librem13v2/Makefile.inc index 4e2997e..d5b5137 100644 --- a/src/mainboard/purism/librem13v2/Makefile.inc +++ b/src/mainboard/purism/librem13v2/Makefile.inc @@ -17,7 +17,7 @@ romstage-y += pei_data.c -ramstage-y += mainboard.c ramstage-y += pei_data.c ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index 39333a2..ece7a4e 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -35,7 +35,7 @@ register "SataPortsEnable[1]" = "1" register "EnableAzalia" = "1" register "DspEnable" = "1" - register "IoBufferOwnership" = "3" + register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" register "XdciEnable" = "0" register "SsicPortEnable" = "0" diff --git a/src/mainboard/purism/librem13v2/hda_verb.c b/src/mainboard/purism/librem13v2/hda_verb.c new file mode 100644 index 0000000..e8eecdf --- /dev/null +++ b/src/mainboard/purism/librem13v2/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <chip.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <soc/intel/common/hda_verb.h> +#include <soc/pci_devs.h> + +#include "hda_verb.h" + +static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void mb_hda_codec_init(void *unused) +{ + static struct soc_intel_skylake_config *config; + u8 *base; + struct resource *res; + u32 codec_mask; + struct device *dev; + + dev = SA_DEV_ROOT; + /* Check if HDA is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* + * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, + * 3:I2S Ports. In HDA mode where codec need to be programmed with + * verb table + */ + if (config->IoBufferOwnership == 3) + return; + + /* Find base address */ + dev = dev_find_slot(0, PCH_DEVFN_HDA); + if (dev == NULL) + return; + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); diff --git a/src/mainboard/purism/librem13v2/hda_verb.h b/src/mainboard/purism/librem13v2/hda_verb.h new file mode 100644 index 0000000..d76cc17 --- /dev/null +++ b/src/mainboard/purism/librem13v2/hda_verb.h @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x19910269, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ + + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, + + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ + 0x00172069, + 0x00172102, + 0x00172291, + 0x00172319, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + 0x01271c00, + 0x01271d00, + 0x01271e00, + 0x01271f40, + + /* Pin Complex (NID 0x14) */ + 0x01471c10, + 0x01471d01, + 0x01471e17, + 0x01471f90, + + /* Pin Complex (NID 0x17) */ + 0x01771cf0, + 0x01771d11, + 0x01771e11, + 0x01771f41, + + /* Pin Complex (NID 0x18) */ + 0x01871c20, + 0x01871d10, + 0x01871ea1, + 0x01871f04, + + /* Pin Complex (NID 0x19) */ + 0x01971c30, + 0x01971d01, + 0x01971ea7, + 0x01971f90, + + /* Pin Complex (NID 0x1A) */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1B) */ + 0x01b71cf0, + 0x01b71d11, + 0x01b71e11, + 0x01b71f41, + + /* Pin Complex (NID 0x1D) */ + 0x01d71c05, + 0x01d71d9d, + 0x01d71e56, + 0x01d71f40, + + /* Pin Complex (NID 0x1E) */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + + /* Pin Complex (NID 0x21) */ + 0x02171c1f, + 0x02171d10, + 0x02171e21, + 0x02171f04, +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/purism/librem13v2/mainboard.c b/src/mainboard/purism/librem13v2/mainboard.c deleted file mode 100644 index fae2889..0000000 --- a/src/mainboard/purism/librem13v2/mainboard.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <console/console.h> -#include <device/device.h> -#include <stdlib.h> -#include <soc/nhlt.h> - -static unsigned long mainboard_write_acpi_tables( - device_t device, unsigned long current, acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - uintptr_t end_addr; - struct nhlt *nhlt; - - start_addr = current; - - nhlt = nhlt_init(); - - if (nhlt == NULL) - return start_addr; - - /* 2 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); - - /* ADI Smart Amps for left and right. */ - if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) - printk(BIOS_ERR, "Couldn't add ssm4567.\n"); - - /* NAU88l25 Headset codec. */ - if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Couldn't add headset codec.\n"); - - end_addr = nhlt_soc_serialize(nhlt, start_addr); - - if (end_addr != start_addr) - acpi_add_table(rsdp, (void *)start_addr); - - return end_addr; -} - -/* - * mainboard_enable is executed as first thing after - * enumerate_buses(). - */ -static void mainboard_enable(device_t dev) -{ - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; -- To view, visit https://review.coreboot.org/19890 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I619a6bdd0bc01b9c99291b77b0ef52d3be3b79c0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: select SERIRQ_CONTINUOUS_MODE
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19889 to review the following change. Change subject: purism/librem13v2: select SERIRQ_CONTINUOUS_MODE ...................................................................... purism/librem13v2: select SERIRQ_CONTINUOUS_MODE Like other devices using ENE EC's, this setting is required for the PS2 keyboard and mouse (trackpad) to function Change-Id: Ied20555c92540dbc9cf4e30d596d4432ce26994b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/19889/1 diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig index 68e7aa4..7a69104 100644 --- a/src/mainboard/purism/librem13v2/Kconfig +++ b/src/mainboard/purism/librem13v2/Kconfig @@ -7,6 +7,7 @@ select HAVE_ACPI_TABLES select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE + select SERIRQ_CONTINUOUS_MODE config IRQ_SLOT_COUNT int -- To view, visit https://review.coreboot.org/19889 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ied20555c92540dbc9cf4e30d596d4432ce26994b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: add microcode values in kconfig
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19885 ) Change subject: purism/librem13v2: add microcode values in kconfig ...................................................................... purism/librem13v2: add microcode values in kconfig The FSP Temp RAM init will fail if the mircocode values are set to 0. A valid microcode update needs to be included and its size and offset need to be set in the config. Change-Id: Ibb563489359ec697a00e9209f858edf8f9e6775b Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem13v2/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/19885/1 diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig index ce772fb..a61cea1 100644 --- a/src/mainboard/purism/librem13v2/Kconfig +++ b/src/mainboard/purism/librem13v2/Kconfig @@ -52,5 +52,13 @@ int default 512 +config CPU_MICROCODE_CBFS_LEN + hex + default 0x17800 + +config CPU_MICROCODE_CBFS_LOC + hex + default 0xFFE115A0 + endif -- To view, visit https://review.coreboot.org/19885 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ibb563489359ec697a00e9209f858edf8f9e6775b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: update devicetree
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/19886 to review the following change. Change subject: purism/librem13v2: update devicetree ...................................................................... purism/librem13v2: update devicetree Change-Id: Idd553c59da433c1ebfdae9f9057f0c2200a50f22 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem13v2/devicetree.cb 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/19886/1 diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index f306e7b..e51713b 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -28,10 +28,11 @@ # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" - register "EnableSata" = "0" + register "EnableSata" = "1" register "SataSalpSupport" = "0" register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" @@ -40,8 +41,8 @@ register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "IshEnable" = "0" register "PttSwitch" = "0" -- To view, visit https://review.coreboot.org/19886 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Idd553c59da433c1ebfdae9f9057f0c2200a50f22 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: Add memory init code
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19884 ) Change subject: purism/librem13v2: Add memory init code ...................................................................... purism/librem13v2: Add memory init code Adding code to setup the spd information from sodimm Change-Id: I7869252710fafef8e207fd99ed0767e709045bd5 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem13v2/Kconfig M src/mainboard/purism/librem13v2/Makefile.inc A src/mainboard/purism/librem13v2/bootblock_mainboard.c M src/mainboard/purism/librem13v2/devicetree.cb M src/mainboard/purism/librem13v2/gpio.h M src/mainboard/purism/librem13v2/romstage.c 6 files changed, 102 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/19884/1 diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig index 2828398..ce772fb 100644 --- a/src/mainboard/purism/librem13v2/Kconfig +++ b/src/mainboard/purism/librem13v2/Kconfig @@ -44,4 +44,13 @@ string default "8086,1916" +config DIMM_MAX + int + default 1 + +config DIMM_SPD_SIZE + int + default 512 + + endif diff --git a/src/mainboard/purism/librem13v2/Makefile.inc b/src/mainboard/purism/librem13v2/Makefile.inc index cbb4ee2..4e2997e 100644 --- a/src/mainboard/purism/librem13v2/Makefile.inc +++ b/src/mainboard/purism/librem13v2/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock_mainboard.c romstage-y += pei_data.c diff --git a/src/mainboard/purism/librem13v2/bootblock_mainboard.c b/src/mainboard/purism/librem13v2/bootblock_mainboard.c new file mode 100644 index 0000000..627b4e8 --- /dev/null +++ b/src/mainboard/purism/librem13v2/bootblock_mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb index c8569d9b..f306e7b 100644 --- a/src/mainboard/purism/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -11,7 +11,7 @@ # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" + register "gpe0_dw0" = "GPP_C" register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" @@ -165,7 +165,10 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ diff --git a/src/mainboard/purism/librem13v2/gpio.h b/src/mainboard/purism/librem13v2/gpio.h index bb3098b..01540b5 100644 --- a/src/mainboard/purism/librem13v2/gpio.h +++ b/src/mainboard/purism/librem13v2/gpio.h @@ -132,7 +132,8 @@ /* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), /* GSPI0_CLK */ PAD_CFG_NC_RXINV(GPP_B16, LEVEL), /* GSPI0_MISO */ PAD_CFG_NC_RXINV(GPP_B17, EDGE), -/* GSPI0_MOSI */ PAD_CFG_GPI_ACPI_SCI_LEVEL(GPP_B18, 20K_PU, PLTRST, YES), +/* GSPI0_MOSI */ PAD_CFG_GPI_ACPI_SCI_LEVEL(GPP_B18, 20K_PU, + PLTRST, YES), /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), /* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), @@ -223,9 +224,7 @@ /* I2C3_SDA */ PAD_CFG_NC_1V8(GPP_F6), /* I2C3_SCL */ PAD_CFG_NC_1V8(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), -/* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO1V8_SCL */ /* I2C5_SDA */ PAD_CFG_NC_1V8(GPP_F10), /* I2C5_SCL */ PAD_CFG_NC_1V8(GPP_F11), /* EMMC_CMD */ PAD_CFG_NC(GPP_F12), @@ -264,6 +263,25 @@ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* SRCCLKREQ0# */ PAD_CFG_NF_EVCFG(GPP_B5, NONE, DEEP, NF1, LEVEL), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +}; + #endif #endif diff --git a/src/mainboard/purism/librem13v2/romstage.c b/src/mainboard/purism/librem13v2/romstage.c index da1c4c3..3505467 100644 --- a/src/mainboard/purism/librem13v2/romstage.c +++ b/src/mainboard/purism/librem13v2/romstage.c @@ -16,10 +16,12 @@ */ #include <string.h> +#include <assert.h> #include <arch/acpi.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> +#include <spd_bin.h> void mainboard_romstage_entry(struct romstage_params *params) { @@ -28,3 +30,37 @@ /* Initliaze memory */ romstage_common(params); } + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + struct spd_block blk; + + memory_params->DqPinsInterleaved = 1; + printk(BIOS_INFO, "In mainboard_memory_init_params\n"); + get_spd_smbus(&blk); + dump_spd_info(&blk); + memory_params->MemorySpdDataLen = blk.len; + if (blk.spd_array[0][0] != 0) + memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0]; + if (blk.spd_array[1][0] != 0) + memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1]; + if (blk.spd_array[2][0] != 0) + memory_params->MemorySpdPtr01 = (u32)blk.spd_array[2]; + if (blk.spd_array[3][0] != 0) + memory_params->MemorySpdPtr11 = (u32)blk.spd_array[3]; + + memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], + sizeof(params->pei_data->dq_map[0])); + memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], + sizeof(params->pei_data->dq_map[1])); + memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], + sizeof(params->pei_data->dqs_map[0])); + memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], + sizeof(params->pei_data->dqs_map[1])); + memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, + sizeof(params->pei_data->RcompResistor)); + memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, + sizeof(params->pei_data->RcompTarget)); + +} -- To view, visit https://review.coreboot.org/19884 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I7869252710fafef8e207fd99ed0767e709045bd5 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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coreboot-gerrit May 2017