coreboot-gerrit May 2017

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Change in coreboot[master]: purism/librem13v2: Add GPIO pad configuration
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19883 ) Change subject: purism/librem13v2: Add GPIO pad configuration ...................................................................... purism/librem13v2: Add GPIO pad configuration The GPIO configuration matches the one from the original BIOS. Some configs don't make much sense, but I kept it as is so it would match (such as a NC pin with TX set to 1, or RXINV enabled). Change-Id: I00eef28a71c15893a766b3d178a98dc17b90431c Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/mainboard/purism/librem13v2/Makefile.inc D src/mainboard/purism/librem13v2/bootblock_mainboard.c M src/mainboard/purism/librem13v2/gpio.h 3 files changed, 207 insertions(+), 222 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/19883/1 diff --git a/src/mainboard/purism/librem13v2/Makefile.inc b/src/mainboard/purism/librem13v2/Makefile.inc index 4e2997e..cbb4ee2 100644 --- a/src/mainboard/purism/librem13v2/Makefile.inc +++ b/src/mainboard/purism/librem13v2/Makefile.inc @@ -13,7 +13,6 @@ ## GNU General Public License for more details. ## -bootblock-y += bootblock_mainboard.c romstage-y += pei_data.c diff --git a/src/mainboard/purism/librem13v2/bootblock_mainboard.c b/src/mainboard/purism/librem13v2/bootblock_mainboard.c deleted file mode 100644 index 627b4e8..0000000 --- a/src/mainboard/purism/librem13v2/bootblock_mainboard.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> -#include <soc/gpio.h> -#include "gpio.h" - -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't do. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - -void bootblock_mainboard_init(void) -{ - early_config_gpio(); -} diff --git a/src/mainboard/purism/librem13v2/gpio.h b/src/mainboard/purism/librem13v2/gpio.h index 614cfc0..bb3098b 100644 --- a/src/mainboard/purism/librem13v2/gpio.h +++ b/src/mainboard/purism/librem13v2/gpio.h @@ -19,232 +19,249 @@ #include <soc/gpe.h> #include <soc/gpio.h> -/* EC in RW */ -#define GPIO_EC_IN_RW GPP_C6 - -/* BIOS Flash Write Protect */ -#define GPIO_PCH_WP GPP_C23 - -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C13 -#define GPIO_MEM_CONFIG_2 GPP_C14 -#define GPIO_MEM_CONFIG_3 GPP_C15 - -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ -#define GPE_WLAN_WAKE GPE0_DW0_16 - -/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */ -#define GPE_TOUCHPAD_WAKE GPE0_DW0_05 - -/* Input device interrupt configuration */ -#define TOUCHPAD_INT_L GPP_B3_IRQ -#define TOUCHSCREEN_INT_L GPP_E7_IRQ -#define MIC_INT_L GPP_F10_IRQ - -/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ -#define EC_SCI_GPI GPE0_DW2_16 -#define EC_SMI_GPI GPP_E15 - -/* Power rail control signals. */ -#define EN_PP3300_KEPLER GPP_C11 -#define EN_PP3300_DX_TOUCH GPP_C22 -#define EN_PP3300_DX_EMMC GPP_D5 -#define EN_PP1800_DX_EMMC GPP_D6 -#define EN_PP3300_DX_CAM GPP_D12 - #ifndef __ACPI__ + +/* Redefine PAD_CFG_NF_1V8 using DRIVE0 RXEVCFG value */ +#undef PAD_CFG_NF_1V8 +#define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \ + _PAD_CFG_ATTRS(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, \ + NO, NO, NO, NO, func_, NO, NO), PAD_FIELD(PAD_TOL, 1V8)) + +/* Redefine PAD_CFG_GPI using DRIVE0 RXEVCFG value */ +#undef PAD_CFG_GPI +#define PAD_CFG_GPI(pad_, term_, rst_) \ + _PAD_CFG_ATTRS(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, NO, NO, NO, NO, \ + GPIO, NO, YES), PAD_FIELD(HOSTSW, GPIO)) + +/* Redefine PAD_CFG_GPO using DRIVE0 RXEVCFG value */ +#undef PAD_CFG_TERM_GPO +#define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, DRIVE0, NO, NO, NO, NO, NO, NO, \ + GPIO, YES, NO) | PAD_FIELD_VAL(GPIOTXSTATE, val_)) + +/* Create new macro PAD_CFG_NF_EVCFG to allow specifying the RXEVCFG value */ +#define PAD_CFG_NF_EVCFG(pad_, term_, rst_, func_, evcfg_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, evcfg_, NO, NO, NO, NO, NO, NO, \ + func_, YES, YES)) + +/* Redefine PAD_CFG_NF using DRIVE0 RXEVCFG value */ +#undef PAD_CFG_NF +#define PAD_CFG_NF(pad_, term_, rst_, func_) \ + PAD_CFG_NF_EVCFG(pad_, term_, rst_, func_, DRIVE0) + +/* Define new PAD_CFG_NC_EVCFG macro which sets NC pad with custom RXEVCFG */ +#define PAD_CFG_NC_EVCFG(pad_, evcfg_, val_) \ + _PAD_CFG(pad_, NONE, \ + _DW0_VALS(DEEP, RAW, NO, evcfg_, NO, NO, NO, NO, NO, NO, \ + GPIO, YES, YES) | PAD_FIELD_VAL(GPIOTXSTATE, val_)) + +/* Define new PAD_CFG_NC_RXINV macro which enables the RXINV value */ +#define PAD_CFG_NC_RXINV(pad_, evcfg_) \ + _PAD_CFG(pad_, NONE, \ + _DW0_VALS(DEEP, RAW, NO, evcfg_, NO, YES, NO, NO, NO, NO, \ + GPIO, YES, YES)) + +/* Redefine PAD_CFG_NC using DRIVE0 RXEVCFG value */ +#undef PAD_CFG_NC +#define PAD_CFG_NC(pad_) \ + PAD_CFG_NC_EVCFG(pad_, DRIVE0, 0) + +/* Define new PAD_CFG_NC_1 macro which sets GPIOTXSTATE to 1*/ +#define PAD_CFG_NC_1(pad_) \ + PAD_CFG_NC_EVCFG(pad_, DRIVE0, 1) + +/* Define new NC pad with 1v8 pad voltage tolerance */ +#define PAD_CFG_NC_1V8(pad_) \ + _PAD_CFG_ATTRS(pad_, NONE, \ + _DW0_VALS(DEEP, RAW, NO, DRIVE0, NO, NO, NO, NO, NO, NO, \ + GPIO, YES, YES), PAD_FIELD(PAD_TOL, 1V8)) + +/* Define new PAD_CFG_GPIO_APIC macro which enables both RX and TX */ +#define PAD_CFG_GPIO_APIC(pad_, val_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, \ + GPIO, NO, NO) | PAD_FIELD_VAL(GPIOTXSTATE, val_)) + + /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_CFG_NC_1(GPP_A7), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +/* PME# */ PAD_CFG_NC_EVCFG(GPP_A11, LEVEL, 0), +/* BM_BUSY# */ PAD_CFG_NC_1(GPP_A12), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP), -/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* SUSACK# */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_NC(GPP_A18), /* ISH_GP1 */ PAD_CFG_NC(GPP_A19), /* ISH_GP2 */ PAD_CFG_NC(GPP_A20), /* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), -/* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), +/* ISH_GP4 */ PAD_CFG_NC_1(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC_EVCFG(GPP_A23, LEVEL, 0), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* TRACKPAD_INT_L */ -/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), -/* TRACKPAD WAKE */ -/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* CPU_GP2 */ PAD_CFG_NC_EVCFG(GPP_B3, LEVEL, 0), +/* CPU_GP3 */ PAD_CFG_NC_1(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NF_EVCFG(GPP_B5, NONE, DEEP, NF1, LEVEL), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP), +/* SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), /* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP), +/* GSPI0_CLK */ PAD_CFG_NC_RXINV(GPP_B16, LEVEL), +/* GSPI0_MISO */ PAD_CFG_NC_RXINV(GPP_B17, EDGE), +/* GSPI0_MOSI */ PAD_CFG_GPI_ACPI_SCI_LEVEL(GPP_B18, 20K_PU, PLTRST, YES), /* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), /* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP), -/* SM1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */ -/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ -/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */ -/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */ -/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */ -/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */ -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ -/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ -/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ -/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */ -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */ -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */ -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TRACKPAD */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), -/* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP), -/* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP), -/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), -/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ -/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), -/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */ -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), -/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), +/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */ +/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NC(GPP_C12), +/* UART1_TXD */ PAD_CFG_NC(GPP_C13), +/* UART1_RTS# */ PAD_CFG_NC(GPP_C14), +/* UART1_CTS# */ PAD_CFG_NC(GPP_C15), +/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP), +/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP), +/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* UART2_RXD */ PAD_CFG_NC(GPP_C20), +/* UART2_TXD */ PAD_CFG_NC(GPP_C21), +/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), +/* UART2_CTS# */ PAD_CFG_NC(GPP_C23), + +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), +/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), +/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_NC_EVCFG(GPP_D9, LEVEL, 0), +/* ISH_SPI_CLK */ PAD_CFG_NC_EVCFG(GPP_D10, LEVEL, 0), +/* ISH_SPI_MISO */ PAD_CFG_NC_EVCFG(GPP_D11, LEVEL, 0), +/* ISH_SPI_MOSI */ PAD_CFG_NC_EVCFG(GPP_D12, LEVEL, 0), +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), /* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), -/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ -/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), +/* I2S_MCLK */ PAD_CFG_NC(GPP_D23), + +/* SATAXPCI0 */ PAD_CFG_NC_EVCFG(GPP_E0, EDGE, 0), /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_NC_1(GPP_E3), /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* TOUCHSCREEN_INT_L */ +/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), /* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), -/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ -/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -/* USB_C0_DP_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* USB_C1_DP_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), -/* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_NC_EVCFG(GPP_E15, EDGE, 0), +/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NO), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */ -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), -/* - * The next 4 pads are for bit banging the amplifiers. They are connected - * together with i2s0 signals. For default behavior of i2s make these - * gpio inupts. - */ -/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), -/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), -/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), -/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_GPIO_APIC(GPP_E22, 0, NONE, DEEP), +/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), + +/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), +/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), +/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), +/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), +/* I2C2_SDA */ PAD_CFG_NC_1V8(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC_1V8(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NC_1V8(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC_1V8(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), -/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), -/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), -/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), -/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), -/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), -/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), -/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), -/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), -/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), -/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), -/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), -/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), -/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), -/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), -/* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP), -/* RSVD */ PAD_CFG_NC(GPD7), -/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP), -/* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP), -/* LANPHYC */ PAD_CFG_NC(GPD11), -}; +/* I2C5_SDA */ PAD_CFG_NC_1V8(GPP_F10), +/* I2C5_SCL */ PAD_CFG_NC_1V8(GPP_F11), +/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), +/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), +/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), +/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), +/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), +/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), +/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), +/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), +/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), +/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), +/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), +/* RSVD */ PAD_CFG_NC_EVCFG(GPP_F23, LEVEL, 0), -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), + +/* BATLOW# */ PAD_CFG_NC(GPD0), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, RSMRST, NF1), +/* LAN_WAKE# */ PAD_CFG_NC_EVCFG(GPD2, LEVEL, 0), +/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, RSMRST, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; #endif -- To view, visit https://review.coreboot.org/19883 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I00eef28a71c15893a766b3d178a98dc17b90431c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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Change in coreboot[master]: purism/librem13v2: Adding initial directory for librem13 v2
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19882 ) Change subject: purism/librem13v2: Adding initial directory for librem13 v2 ...................................................................... purism/librem13v2: Adding initial directory for librem13 v2 Add the initial directory for the port of the Librem 13 v2. The base implementation was copied from the google/chell directory and the chell references were replaced. spd directory was removed since the RAM is not soldered on the MB. The Kconfig, board_info.txt and devicetree.cb files were modified to match the Librem 13 v2 hardware information. The romstage.c, mainboard.c, Makefile.in and dsdt.asl were modified to remove chromeos specific code. The boardid.c, chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c files were removed from the tree, and the acpi directory was replaced with the acpi directory from the purism/librem13 board. These changes allow us to remove the references to chromeos specific code and allow coreboot to compile when the librem13v2 board is selected. Change-Id: Ibf26b7f55f3de04950077f02eb0350374abf3549 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- A src/mainboard/purism/librem13v2/Kconfig A src/mainboard/purism/librem13v2/Kconfig.name A src/mainboard/purism/librem13v2/Makefile.inc A src/mainboard/purism/librem13v2/acpi/ec.asl A src/mainboard/purism/librem13v2/acpi/mainboard.asl A src/mainboard/purism/librem13v2/acpi/superio.asl A src/mainboard/purism/librem13v2/acpi_tables.c A src/mainboard/purism/librem13v2/board_info.txt A src/mainboard/purism/librem13v2/bootblock_mainboard.c A src/mainboard/purism/librem13v2/devicetree.cb A src/mainboard/purism/librem13v2/dsdt.asl A src/mainboard/purism/librem13v2/gpio.h A src/mainboard/purism/librem13v2/mainboard.c A src/mainboard/purism/librem13v2/pei_data.c A src/mainboard/purism/librem13v2/ramstage.c A src/mainboard/purism/librem13v2/romstage.c 16 files changed, 910 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/19882/1 diff --git a/src/mainboard/purism/librem13v2/Kconfig b/src/mainboard/purism/librem13v2/Kconfig new file mode 100644 index 0000000..2828398 --- /dev/null +++ b/src/mainboard/purism/librem13v2/Kconfig @@ -0,0 +1,47 @@ +if BOARD_PURISM_LIBREM13_V2 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_NAU8825 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MONOTONIC_TIMER_MSR + select SOC_INTEL_SKYLAKE + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "Purism" + +config MAINBOARD_FAMILY + string + default "Librem 13" + +config MAINBOARD_PART_NUMBER + string + default "Librem 13 v2" + +config MAINBOARD_DIR + string + default "purism/librem13v2" + +config MAX_CPUS + int + default 8 + +config NO_POST + def_bool y + help + This platform does not have any way to see POST codes + so disable them by default. + +config VGA_BIOS_ID + string + default "8086,1916" + +endif diff --git a/src/mainboard/purism/librem13v2/Kconfig.name b/src/mainboard/purism/librem13v2/Kconfig.name new file mode 100644 index 0000000..838f2b2 --- /dev/null +++ b/src/mainboard/purism/librem13v2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_PURISM_LIBREM13_V2 + bool "Librem 13 v2" diff --git a/src/mainboard/purism/librem13v2/Makefile.inc b/src/mainboard/purism/librem13v2/Makefile.inc new file mode 100644 index 0000000..4e2997e --- /dev/null +++ b/src/mainboard/purism/librem13v2/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock_mainboard.c + +romstage-y += pei_data.c + +ramstage-y += mainboard.c +ramstage-y += pei_data.c +ramstage-y += ramstage.c + diff --git a/src/mainboard/purism/librem13v2/acpi/ec.asl b/src/mainboard/purism/librem13v2/acpi/ec.asl new file mode 100644 index 0000000..cf8b9a9 --- /dev/null +++ b/src/mainboard/purism/librem13v2/acpi/ec.asl @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define EC_SCI_GPI 10 + +#include <ec/purism/librem/acpi/ec.asl> diff --git a/src/mainboard/purism/librem13v2/acpi/mainboard.asl b/src/mainboard/purism/librem13v2/acpi/mainboard.asl new file mode 100644 index 0000000..f0b2c1d --- /dev/null +++ b/src/mainboard/purism/librem13v2/acpi/mainboard.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + + Method (_STA) + { + Return (0xF) + } + + Method (_LID) + { + Return (\_SB.PCI0.LPCB.EC.LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + + Method (_STA) + { + Return (0xF) + } + + Name (_PRW, Package () { 27, 4 }) + } + + Device (SLPB) + { + Name (_HID, EisaId ("PNP0C0E")) + + Method (_STA) + { + Return (0xF) + } + } +} diff --git a/src/mainboard/purism/librem13v2/acpi/superio.asl b/src/mainboard/purism/librem13v2/acpi/superio.asl new file mode 100644 index 0000000..92c272e --- /dev/null +++ b/src/mainboard/purism/librem13v2/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/purism/librem13v2/acpi_tables.c b/src/mainboard/purism/librem13v2/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/purism/librem13v2/acpi_tables.c diff --git a/src/mainboard/purism/librem13v2/board_info.txt b/src/mainboard/purism/librem13v2/board_info.txt new file mode 100644 index 0000000..fb0dd0b --- /dev/null +++ b/src/mainboard/purism/librem13v2/board_info.txt @@ -0,0 +1,9 @@ +Vendor name: Purism +Board name: Librem 13 v2 +Board URL: https://puri.sm/librem-13/ +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/purism/librem13v2/bootblock_mainboard.c b/src/mainboard/purism/librem13v2/bootblock_mainboard.c new file mode 100644 index 0000000..627b4e8 --- /dev/null +++ b/src/mainboard/purism/librem13v2/bootblock_mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include "gpio.h" + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb new file mode 100644 index 0000000..c8569d9b --- /dev/null +++ b/src/mainboard/purism/librem13v2/devicetree.cb @@ -0,0 +1,237 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "EnableTraceHub" = "0" + register "XdciEnable" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "0" + register "IshEnable" = "0" + register "PttSwitch" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "FspSkipMpInit" = "1" + register "SaGv" = "3" + register "SerialIrqConfigSirqEnable" = "1" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "1" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }" + + # Enable Root port 1. + register "PcieRpEnable[0]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[0]" = "1" + # RP 1 uses SRCCLKREQ1# + register "PcieRpClkReqNumber[0]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # SD + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, + [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart1] = PchSerialIoDisabled, + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, + }" + + # PL2 override 15W + register "tdp_pl2_override" = "15" + + register "tcc_offset" = "10" # TCC of 90C + + # Send an extra VR mailbox command for the supported MPS IMVP8 model + register "SendVrMbxCmd" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW0_16" + device pci 00.0 on end + end + end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip ec/purism/librem + device pnp 0c09.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/purism/librem13v2/dsdt.asl b/src/mainboard/purism/librem13v2/dsdt.asl new file mode 100644 index 0000000..b1f6a54 --- /dev/null +++ b/src/mainboard/purism/librem13v2/dsdt.asl @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/purism/librem13v2/gpio.h b/src/mainboard/purism/librem13v2/gpio.h new file mode 100644 index 0000000..614cfc0 --- /dev/null +++ b/src/mainboard/purism/librem13v2/gpio.h @@ -0,0 +1,252 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_WLAN_WAKE GPE0_DW0_16 + +/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_TOUCHPAD_WAKE GPE0_DW0_05 + +/* Input device interrupt configuration */ +#define TOUCHPAD_INT_L GPP_B3_IRQ +#define TOUCHSCREEN_INT_L GPP_E7_IRQ +#define MIC_INT_L GPP_F10_IRQ + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +/* Power rail control signals. */ +#define EN_PP3300_KEPLER GPP_C11 +#define EN_PP3300_DX_TOUCH GPP_C22 +#define EN_PP3300_DX_EMMC GPP_D5 +#define EN_PP1800_DX_EMMC GPP_D6 +#define EN_PP3300_DX_CAM GPP_D12 + +#ifndef __ACPI__ +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP), +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP), +/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), +/* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), +/* VRALERT# */ PAD_CFG_NC(GPP_B2), +/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* TRACKPAD_INT_L */ +/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ +/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* TRACKPAD WAKE */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ +/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), +/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), +/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP), +/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), +/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), +/* WLAN WAKE */ +/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP), +/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), +/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), +/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP), +/* SM1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */ +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), +/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */ +/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */ +/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */ +/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */ +/* UART0_RXD */ PAD_CFG_NC(GPP_C8), +/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ +/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ +/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ +/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TRACKPAD */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), +/* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP), +/* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP), +/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ +/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), +/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */ +/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), +/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ +/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), +/* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ +/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* USB_C0_DP_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* USB_C1_DP_HPD */ +/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), +/* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SCI_L */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP), +/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */ +/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */ +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* + * The next 4 pads are for bit banging the amplifiers. They are connected + * together with i2s0 signals. For default behavior of i2s make these + * gpio inupts. + */ +/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), +/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* AUDIO1V8_SDA */ +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), +/* AUDIO1V8_SCL */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* RSVD */ PAD_CFG_NC(GPP_F23), +/* SD_CMD */ PAD_CFG_NC(GPP_G0), +/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), +/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), +/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), +/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), +/* SD_CD# */ PAD_CFG_NC(GPP_G5), +/* SD_CLK */ PAD_CFG_NC(GPP_G6), +/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP), +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP), +/* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP), +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +}; + +#endif + +#endif diff --git a/src/mainboard/purism/librem13v2/mainboard.c b/src/mainboard/purism/librem13v2/mainboard.c new file mode 100644 index 0000000..fae2889 --- /dev/null +++ b/src/mainboard/purism/librem13v2/mainboard.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <stdlib.h> +#include <soc/nhlt.h> + +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* ADI Smart Amps for left and right. */ + if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add ssm4567.\n"); + + /* NAU88l25 Headset codec. */ + if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/purism/librem13v2/pei_data.c b/src/mainboard/purism/librem13v2/pei_data.c new file mode 100644 index 0000000..84f38d9 --- /dev/null +++ b/src/mainboard/purism/librem13v2/pei_data.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 3, 1, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; + + memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); + memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); + memcpy(pei_data->RcompResistor, RcompResistor, + sizeof(RcompResistor)); + memcpy(pei_data->RcompTarget, RcompTarget, + sizeof(RcompTarget)); +} diff --git a/src/mainboard/purism/librem13v2/ramstage.c b/src/mainboard/purism/librem13v2/ramstage.c new file mode 100644 index 0000000..d22e145 --- /dev/null +++ b/src/mainboard/purism/librem13v2/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/purism/librem13v2/romstage.c b/src/mainboard/purism/librem13v2/romstage.c new file mode 100644 index 0000000..da1c4c3 --- /dev/null +++ b/src/mainboard/purism/librem13v2/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/acpi.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> + +void mainboard_romstage_entry(struct romstage_params *params) +{ + /* Fill out PEI DATA */ + mainboard_fill_pei_data(params->pei_data); + /* Initliaze memory */ + romstage_common(params); +} -- To view, visit https://review.coreboot.org/19882 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ibf26b7f55f3de04950077f02eb0350374abf3549 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>

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Change in coreboot[master]: console/flashsconsole: Add spi flash console for debugging
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19849 ) Change subject: console/flashsconsole: Add spi flash console for debugging ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10025/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54296/ : SUCCESS -- To view, visit https://review.coreboot.org/19849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 24 May '17

24 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/19759/8/src/soc/intel/common/block/gpio/gpi… File src/soc/intel/common/block/gpio/gpio.c: Line 121: soc_gpio_configure_itss(cfg, comm->port, config_offset); > Having an empty ITSS function seems bad? Thoughts on providing a Kconfig to Yes I can pull in the implementation in here to common area and add a CONFIG flag -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: console/flashsconsole: Add spi flash console for debugging
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/19849 ) Change subject: console/flashsconsole: Add spi flash console for debugging ...................................................................... Patch Set 7: I've set READ_BUFFER_SIZE to 0x100, and made it return if there's any error reading or writing to the flash. I think it's safer that way. Limiting the I/O is nice, but ultimately, this feature is only for debugging purposes, so it doesn't need to be as optimized as that. It will do 10 reads instead of 1 before stopping, it's not the end of the world. -- To view, visit https://review.coreboot.org/19849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: console/flashsconsole: Add spi flash console for debugging
by Youness Alaoui (Code Review) 24 May '17

24 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19849 to look at the new patch set (#8). Change subject: console/flashsconsole: Add spi flash console for debugging ...................................................................... console/flashsconsole: Add spi flash console for debugging If CONSOLE_SPI_FLASH config is enabled, we can write the cbmem messages to the 'CONSOLE' area in FMAP if the area is defined or to the 'console' fil in CBFS which allows us to grab the log when we read the flash. This is useful when you don't have usb debugging, and UART lines are hard to find. Since a failure to boot would require a hardware flasher anyways, we can get the log at the same time. This feature should only be used when no alternative is found and only when we can't boot the system, because excessive writes to the flash is not recommended. This has been tested on purism/librem13 v2 and librem 15 v3 which run Intel Skylake hardware. It has not been tested on other archs or with a driver other than the fast_spi. Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- M src/console/Kconfig M src/console/console.c M src/drivers/spi/Makefile.inc A src/drivers/spi/flashconsole.c A src/include/console/flash.h 5 files changed, 278 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19849/8 -- To view, visit https://review.coreboot.org/19849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/lint: ignore some more binary file types
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19880 ) Change subject: util/lint: ignore some more binary file types ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10023/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54294/ : SUCCESS -- To view, visit https://review.coreboot.org/19880 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I41e773c0adab796876a3b1e91e089ae89cbb04df Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: util/hugo: Add framework to build www.coreboot.org/Documenta...
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19881 ) Change subject: util/hugo: Add framework to build www.coreboot.org/Documentation ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10024/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54295/ : SUCCESS -- To view, visit https://review.coreboot.org/19881 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I000e15b29a182bb88b40de3d0178bf8cc54ba8af Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Add write leveling
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19878 ) Change subject: [WIP]nb/intel/x4x/raminit: Add write leveling ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54292/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10021/ : SUCCESS -- To view, visit https://review.coreboot.org/19878 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibfbaa235bc4eb08e9345321b851e880390a624e8 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS t...
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19879 ) Change subject: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS training ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10022/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54293/ : SUCCESS -- To view, visit https://review.coreboot.org/19879 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I806840445b5e768d079910fb9870a2cee7b9f1ca Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017