coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

1 participants
3888 discussions

Change in coreboot[master]: nb/x4x/raminit: Split of DDR2 specific functions to its own ...
by Arthur Heymans (Code Review) 24 May '17

24 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19868 to look at the new patch set (#2). Change subject: nb/x4x/raminit: Split of DDR2 specific functions to its own file ...................................................................... nb/x4x/raminit: Split of DDR2 specific functions to its own file Headers for device/dram/ddr2 and ddr3 conflict so the easy solution is have separate files for functions that use those. Change-Id: I3ab281f4d8fcce3ef3cf8e355e7ea7286c73e4ff Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Makefile.inc M src/northbridge/intel/x4x/raminit.c A src/northbridge/intel/x4x/spd_ddr2_decode.c M src/northbridge/intel/x4x/x4x.h 4 files changed, 161 insertions(+), 137 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/19868/2 -- To view, visit https://review.coreboot.org/19868 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3ab281f4d8fcce3ef3cf8e355e7ea7286c73e4ff Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: nb/x4x/raminit: Rewrite SPD decode and timing selection
by Arthur Heymans (Code Review) 24 May '17

24 May '17

Hello build bot (Jenkins), coreboot org, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19143 to look at the new patch set (#18). Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection ...................................................................... nb/x4x/raminit: Rewrite SPD decode and timing selection This is mostly written from scratch and uses common spd ddr2 decode functions. This improves the following: * This fixes incorrect CAS/Freq detection on DDR2; * Fixes tRFC computation; tRFC == 78 is a valid timing which is excluded and 0 ends up being used. (TESTED) * Timings selection does not use loops; * Removes ddr3 spd decode, since there is no DDR3 raminit. For this it would be nice to use similar common functions for DDR3; * Raminit would bail out if dimm was unsupported, now in some cases it just marks the dimm slot as empty; * It dramatically reduces stack usage since it does not allocate 4 times 256 bytes to store full SPDs, amongs other unused things that were stored in sysinfo. * Reports when no dimms are present. * Uses i2c block read to read SPD which is about 5 times faster than bytewise read, with a fallback to smbus mode in case of failure. TESTED: on ga-g41m-es2l. Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit.c M src/northbridge/intel/x4x/raminit_ddr2.c M src/northbridge/intel/x4x/x4x.h 3 files changed, 277 insertions(+), 383 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19143/18 -- To view, visit https://review.coreboot.org/19143 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Gerrit-PatchSet: 18 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

1 0

Change in coreboot[master]: nb/x4x/raminit: Split of DDR2 specific functions to its own ...
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19868 ) Change subject: nb/x4x/raminit: Split of DDR2 specific functions to its own file ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9997/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54267/ : SUCCESS -- To view, visit https://review.coreboot.org/19868 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3ab281f4d8fcce3ef3cf8e355e7ea7286c73e4ff Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Add write leveling
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19878 ) Change subject: [WIP]nb/intel/x4x/raminit: Add write leveling ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54278/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10007/ : SUCCESS -- To view, visit https://review.coreboot.org/19878 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibfbaa235bc4eb08e9345321b851e880390a624e8 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/intel/x4x: DDR3 JEDEC init
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19877 ) Change subject: nb/intel/x4x: DDR3 JEDEC init ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10006/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54277/ : SUCCESS -- To view, visit https://review.coreboot.org/19877 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3b5eeb0aff6764292bbcbed7274274f615066c14 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS t...
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19879 ) Change subject: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS training ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54279/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10008/ : SUCCESS -- To view, visit https://review.coreboot.org/19879 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I806840445b5e768d079910fb9870a2cee7b9f1ca Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/intel/x4x: Add DDR3 rcomp
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19875 ) Change subject: nb/intel/x4x: Add DDR3 rcomp ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10004/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54276/ : SUCCESS -- To view, visit https://review.coreboot.org/19875 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/intel/x4x/raminit: DDR3 specific ODT
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19876 ) Change subject: nb/intel/x4x/raminit: DDR3 specific ODT ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10005/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54275/ : SUCCESS -- To view, visit https://review.coreboot.org/19876 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: device/dram/ddr2: Add functions to select common CAS en freq
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18320 ) Change subject: device/dram/ddr2: Add functions to select common CAS en freq ...................................................................... Patch Set 27: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9995/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54266/ : SUCCESS -- To view, visit https://review.coreboot.org/18320 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Gerrit-PatchSet: 27 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 24 May '17

24 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/19759/9/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/gpio.h: PS9, Line 89: soc_gpe_route_to_gpio > I am thinking of removing this function - caller passes the config values f Ignore my comment, we need the mapping for PMC to GPIO translation -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2017