coreboot-gerrit May 2017

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Change in coreboot[master]: nb/intel/x4x: Rename a things that are not ddr2 specific
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19870 ) Change subject: nb/intel/x4x: Rename a things that are not ddr2 specific ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9999/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54269/ : SUCCESS -- To view, visit https://review.coreboot.org/19870 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: Support programming initials DD3 DLL s...
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19874 ) Change subject: nb/intel/x4x/raminit: Support programming initials DD3 DLL setting ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10003/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54274/ : SUCCESS -- To view, visit https://review.coreboot.org/19874 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia79b216ad69a02d4706ffc74f867a85db3eb2d6c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: Support programming DDR3 timings
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19873 ) Change subject: nb/intel/x4x/raminit: Support programming DDR3 timings ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10002/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54273/ : SUCCESS -- To view, visit https://review.coreboot.org/19873 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: Make programming launch ddr3 specific
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19872 ) Change subject: nb/intel/x4x/raminit: Make programming launch ddr3 specific ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10001/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54272/ : SUCCESS -- To view, visit https://review.coreboot.org/19872 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/x4x/raminit: Rewrite SPD decode and timing selection
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19143 ) Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection ...................................................................... Patch Set 17: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9996/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54268/ : SUCCESS -- To view, visit https://review.coreboot.org/19143 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: nb/x4x/raminit: Decode ddr3 dimms
by build bot (Jenkins) (Code Review) 24 May '17

24 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19869 ) Change subject: nb/x4x/raminit: Decode ddr3 dimms ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9998/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54270/ : SUCCESS -- To view, visit https://review.coreboot.org/19869 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/x4x/raminit: Rewrite SPD decode and timing selection
by Arthur Heymans (Code Review) 24 May '17

24 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19143 ) Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection ...................................................................... Patch Set 17: aw I accidentally push a previous version... -- To view, visit https://review.coreboot.org/19143 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071 Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Add write leveling
by Arthur Heymans (Code Review) 24 May '17

24 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19878 ) Change subject: [WIP]nb/intel/x4x/raminit: Add write leveling ...................................................................... [WIP]nb/intel/x4x/raminit: Add write leveling Does not work!! Change-Id: Ibfbaa235bc4eb08e9345321b851e880390a624e8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Makefile.inc A src/northbridge/intel/x4x/dq_dqsl_dll.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/spd_ddr3_decode.c 5 files changed, 507 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/19878/1 diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 8b59dbf..72f2c0e 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += ram_calc.c romstage-y += spd_ddr2_decode.c romstage-y += spd_ddr3_decode.c +romstage-y += write_level.c romstage-y += raminit_tables.c ramstage-y += acpi.c diff --git a/src/northbridge/intel/x4x/dq_dqsl_dll.c b/src/northbridge/intel/x4x/dq_dqsl_dll.c new file mode 100644 index 0000000..a1dea68 --- /dev/null +++ b/src/northbridge/intel/x4x/dq_dqsl_dll.c @@ -0,0 +1,439 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <halt.h> +#include <delay.h> +#include "x4x.h" +#include "iomap.h" + +static void do_write_level(struct sysinfo *s, u8 channel, u8 config, u8 rank1, + u8 rank0, int wl_enable) +{ + u32 emrs1; + + /* Is shifted by bits 2 later so u8 can be used to reduce size */ + const static u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ + { /* Config 0: 2R2R */ + {0x11, 0x00, 0x91, 0x00}, + {0x00, 0x11, 0x91, 0x00}, + {0x91, 0x00, 0x11, 0x00}, + {0x91, 0x00, 0x00, 0x11} + }, + { // Config 1: 2R1R + {0x11, 0x00, 0x91, 0x00}, + {0x00, 0x11, 0x91, 0x00}, + {0x91, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x00, 0x00} + }, + { // Config 2: 1R2R + {0x11, 0x00, 0x91, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x91, 0x00, 0x11, 0x00}, + {0x91, 0x00, 0x00, 0x11} + }, + { // Config 3: 1R1R + {0x11, 0x00, 0x91, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x91, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x00, 0x00} + }, + { // Config 4: 2R0R + {0x11, 0x00, 0x00, 0x00}, + {0x00, 0x11, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00} + }, + { // Config 5: 0R2R + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x00, 0x11} + }, + { // Config 6: 1R0R + {0x11, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00} + }, + { // Config 7: 0R1R + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x00, 0x00} + } + }; + + if (wl_enable) { + printk(RAM_DEBUG, "Entering WL mode\n"); + printk(RAM_DEBUG, "Using WL ODT values\n"); + emrs1 = emrs1_lut[config][rank0][rank1]; + } else { + printk(RAM_DEBUG, "Exiting WL mode\n"); + emrs1 = ddr3_emrs1_config[s->dimm_config[channel]][rank1]; + } + printk(RAM_DEBUG, "Setting ODT for rank%d to ", rank1); + switch (emrs1) { + case 0: + printk(RAM_DEBUG, "0 Ohm\n"); + break; + case 0x11: + printk(RAM_DEBUG, "40 Ohm\n"); + break; + case 0x81: + printk(RAM_DEBUG, "30 Ohm\n"); + break; + case 0x80: + printk(RAM_DEBUG, "20 Ohm\n"); + break; + case 0x10: + printk(RAM_DEBUG, "120 Ohm\n"); + break; + case 0x01: + printk(RAM_DEBUG, "60 Ohm\n"); + break; + default: + printk(BIOS_WARNING, "ODT value Undefined!\n"); + break; + } + + emrs1 <<= 2; + emrs1 |= (1 << 1); + + if (wl_enable && (rank0 != rank1)) + printk(RAM_DEBUG, "Disabling output for rank%d\n", rank1); + emrs1 |= (1 << 12); + if (wl_enable && (rank0 == rank1)) { + printk(RAM_DEBUG, "Enabling WL for rank%d\n", rank1); + emrs1 |= (1 << 7); + } + send_jedec_cmd(s, rank1, channel, EMRS1_CMD, emrs1); +} + +static void set_db(struct sysinfo *s, struct dll_setting *dqs_setting) +{ + u8 db_tap, db_pi; + + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_800MHz: + db_tap = 0xa3; + db_pi = 0x32; + break; + case MEM_CLOCK_1066MHz: + db_tap = 0x82; + db_pi = 0x76; + break; + case MEM_CLOCK_1333MHz: + db_tap = 0xb3; + db_pi = 0x46; + break; + } + + if (dqs_setting->tap < (db_tap & 0xf)) { + dqs_setting->db_en = 1; + dqs_setting->db_sel = 1; + } else if ((dqs_setting->tap == (db_tap & 0xf)) + && (dqs_setting->pi < (db_pi & 0xf))) { + dqs_setting->db_en = 1; + dqs_setting->db_sel = 1; + } else if (dqs_setting->tap < (db_tap >> 4)) { + dqs_setting->db_en = 0; + dqs_setting->db_sel = 0; + } else if ((dqs_setting->tap == (db_tap >> 4)) + && (dqs_setting->pi < (db_pi >> 4))) { + dqs_setting->db_en = 0; + dqs_setting->db_sel = 0; + } else { + dqs_setting->db_en = 1; + dqs_setting->db_sel = 0; + } +} + +const static u8 max_tap[3] = {12, 10, 13}; + +static int increment_dqs(struct sysinfo *s, struct dll_setting *dqs_setting) +{ + u8 max_tap_val = max_tap[s->selected_timings.mem_clk + - MEM_CLOCK_800MHz]; + /* PI */ + if (dqs_setting->pi < 6) { + dqs_setting->pi += 1; + } else if (dqs_setting->tap < max_tap_val) { + dqs_setting->pi = 0; + dqs_setting->tap += 1; + } else if (dqs_setting->clk_delay < 2) { + dqs_setting->pi = 0; + dqs_setting->tap = 0; + dqs_setting->clk_delay += 1; + } else if (dqs_setting->coarse < 1) { + dqs_setting->pi = 0; + dqs_setting->tap = 0; + dqs_setting->clk_delay = 0; + dqs_setting->coarse += 1; + } else { + return 1; + } + set_db(s, dqs_setting); + return 0; +} + +static int decrement_dqs(struct sysinfo *s, struct dll_setting *dqs_setting) +{ + u8 max_tap_val = max_tap[s->selected_timings.mem_clk + - MEM_CLOCK_800MHz]; + if (dqs_setting->pi > 0) { + dqs_setting->pi -= 1; + } else if (dqs_setting->tap > 0) { + dqs_setting->pi = 6; + dqs_setting->tap -= 1; + } else if (dqs_setting->clk_delay > 0) { + dqs_setting->pi = 6; + dqs_setting->tap = max_tap_val; + dqs_setting->clk_delay -= 1; + } else if (dqs_setting->coarse > 0) { + dqs_setting->pi = 6; + dqs_setting->tap = max_tap_val; + dqs_setting->clk_delay += 1; + dqs_setting->coarse -= 1; + } else { + return 1; + } + set_db(s, dqs_setting); + return 0; +} + +#define N_LOOPS 2 /* Most likely needs to be even */ +#define N_SAMPLES 5 + +static u8 sample_dq(struct sysinfo *s, u8 channel, u8 rank, u8 pass) { + u32 address = (channel << 29) | rank * 128 * MiB; + u8 all_found = 0xff; + int samples, lane; + + for (samples = 0; samples < N_SAMPLES; samples++) { + write32((u32 *)address, 0x12341234); + write32((u32 *)address + 4, 0x12341234); + udelay(10); + for (lane = 0; lane < 8; lane++) { + if (((MCHBAR8(0x561 + 0x400 * channel + (lane * 4)) + & 0x80) >> 7) != (pass % 2)) + all_found &= ~(1 << lane); + } + } + return all_found; +} + +static void increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank) +{ + int loop, lane, status, temp0, temp1 = 0; + u8 saved_24d; + struct dll_setting dqs_setting[8]; + u8 all_found; + u8 bytelane = 0xff; + + for (lane = 0; lane < 8; lane++) { + dqs_setting[lane].pi = 0; + dqs_setting[lane].tap = 0; + dqs_setting[lane].clk_delay = 0; + dqs_setting[lane].db_en = 0; + dqs_setting[lane].db_sel = 0; + dqs_setting[lane].coarse = 0; + } + + for (lane = 0; lane < 8; lane++) { + printk(RAM_DEBUG, "Lane %d\n", lane); + while (!increment_dqs(s, &dqs_setting[lane])) { + temp0 = (sample_dq(s, 0, 0, 1) >> lane) & 1 ; + if (temp0 != temp1) { + temp1 = temp0; + printk(RAM_DEBUG, "Found EDGE for lane %d at: ", + lane); + print_dll_setting(&dqs_setting[lane], 1); + } + + printk(RAM_DEBUG,"\tDQ: %s ", (temp0 ? + "LOW" : "HIGH")); + dqsset(channel, lane, &dqs_setting[lane]); + } + } + + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_800MHz: + for (lane = 0; lane < 8; lane++) + dqs_setting[lane] = ddr3_dll_setting_800[s->nmode - 1][DQS1 + lane]; + break; + case MEM_CLOCK_1066MHz: + for (lane = 0; lane < 8; lane++) + dqs_setting[lane] = ddr3_dll_setting_1066[s->nmode - 1][DQS1 + lane]; + break; + case MEM_CLOCK_1333MHz: + for (lane = 0; lane < 8; lane++) + dqs_setting[lane] = ddr3_dll_setting_1333[s->nmode - 1][DQS1 + lane]; + break; + } + + saved_24d = MCHBAR8(0x24d + 0x400 * channel); + + for (loop = 0; loop < N_LOOPS; loop++) { + bytelane = 0xff; + do { + all_found = sample_dq(s, channel, rank, loop); + for (lane = 0; lane < 8; lane++) { + if (!(bytelane & (1 << lane))) + continue; + if (all_found & (1 << lane)) { + bytelane &= ~(1 << lane); + continue; + } else { + if ((loop % 2) == 0) { + status = decrement_dqs(s, &dqs_setting[lane]); + } else { + status = increment_dqs(s, &dqs_setting[lane]); + if (status) + printk(BIOS_WARNING, + " DQS DLL at MAX at lane %d," + " we might have a problem here...\n" + , lane); + } + if (status) { + /* limits are not an invalid settings */ + printk(RAM_SPEW, " lane %d reached limit. Continuing\n", lane); + bytelane &= ~(1 << lane); + status = 0; + } + } + dqsset(channel, lane, &dqs_setting[lane]); + } + } while (bytelane); + printk(BIOS_DEBUG, "DQS settings on PAS #%d:\n", loop); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, "lane %d: ", lane); + print_dll_setting(&dqs_setting[lane], 1); + } + } + + for (lane = 0; lane < 8; lane++) + s->dqs_settings[channel][lane] = dqs_setting[lane]; + + MCHBAR8(0x24d + 0x400 * channel) = saved_24d; +} + +void search_write_leveling(struct sysinfo *s) +{ + int ch, count; + u8 config, rank0, rank1, lane; + u16 saved_x5c4; + struct dll_setting dqs_setting; + + return; /* Sampling DQ does not work :( */ + + u8 chanconfig_lut[16]={ 0, 6, 4, 6, 7, 3, 1, 3, 5, 2, 0, 2, 7, 3, 1, 3 + }; + + u8 odt_force[8][4] = { /* [Config][leveling rank] */ + {0x5, 0x6, 0x5, 0x9}, + {0x5, 0x6, 0x5, 0x0}, + {0x5, 0x0, 0x5, 0x9}, + {0x5, 0x0, 0x5, 0x0}, + {0x1, 0x2, 0x0, 0x0}, + {0x0, 0x0, 0x4, 0x8}, + {0x1, 0x0, 0x0, 0x0}, + {0x0, 0x0, 0x4, 0x0} + }; + + printk(BIOS_DEBUG, "Starting write levelling.\n"); + + MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; + MCHBAR16(0x127) = (MCHBAR16(0x127) & ~0x7ff) | 0x540; + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + printk(BIOS_DEBUG, "\tCH%d\n", ch); + config = chanconfig_lut[s->dimm_config[ch]]; + saved_x5c4 = MCHBAR16(0x5c4 + ch * 0x400); + + MCHBAR8(0x5d8 + 0x400 * ch) = MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e; + MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) & + ~0x3fff) | 0x3fff; + MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f; + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0) { + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank1) { + do_write_level(s, ch, config, rank1, rank0, 1); + } + + MCHBAR8(0x298 + 2 + 0x400 * ch) = (MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f) + | odt_force[config][rank0]; + MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) + | 0x4e; + MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) + | 0x04; + MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00014000; + + increment_to_dqs_edge(s, ch, rank0); + + MCHBAR8(0x298 + 2 + 0x400 * ch) = MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f; + MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) + | 0x0e; + MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04); + MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00555801; + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank1) { + if (rank0 == rank1) { + do_write_level(s, ch, config, rank1, rank0, 0); + send_jedec_cmd(s, rank1 + 4 * ch, ch, NORMALOP_CMD, 1 << 12); + } + } + break; /* Break on first populated rank */ + } + MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e) | 0x0e; + MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) & + ~0x3fff) | 0x1807; + MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f; + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0) { + do_write_level(s, ch, config, rank0, rank0, 0); + } + + } + MCHBAR8(0x5dc) = (MCHBAR8(0x5dc) & ~0x80) | 0x80; + MCHBAR16(0x127) = (MCHBAR16(0x127) & ~0x7ff) | 0x2bf; + + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_800MHz: + count = 39; + break; + case MEM_CLOCK_1066MHz: + count = 32; + break; + case MEM_CLOCK_1333MHz: + count = 42; + break; + } + /* TODO: restore on S3 */ + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + for (lane = 0; lane < 8; lane++) { + dqs_setting = s->dqs_settings[ch][lane]; + dqsset(ch, lane, &dqs_setting); + while (count--) + increment_dqs(s, &dqs_setting); + dqset(ch, lane, &dqs_setting); + } + } + + printk(BIOS_DEBUG, "Done write levelling.\n"); +} diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index a289788..9e7583c 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -369,6 +369,8 @@ void dqsset(u8 ch, u8 lane, const struct dll_setting *setting) { + printk(RAM_SPEW, "DQS setting: ch%d, l%d ", ch, lane); + print_dll_setting(setting, 0); MCHBAR32(0x400*ch + 0x5fc) = (MCHBAR32(0x400*ch + 0x5fc) & ~(2 << (lane*4))) | (setting->coarse << ((lane * 4) + 1)); @@ -414,6 +416,10 @@ void dqset(u8 ch, u8 lane, const struct dll_setting *setting) { + + printk(RAM_SPEW, "DQ setting: ch%d, l%d ", ch, lane); + print_dll_setting(setting, 0); + MCHBAR32(0x400*ch + 0x5fc) = (MCHBAR32(0x400*ch + 0x5fc) & ~(1 << (lane*4))) | (setting->coarse << (lane * 4)); MCHBAR32(0x400*ch + 0x5a4) = (MCHBAR32(0x400*ch + 0x5a4) & ~(0x201 << lane)) | @@ -765,6 +771,20 @@ for (lane = 0; lane < 8; lane++) { dqset(channel, lane, &dll_setting[DQ1 + lane]); } +} + +void print_dll_setting(const struct dll_setting *dll_setting, u8 default_verbose) +{ + u8 debug_level; + if (default_verbose) + debug_level = BIOS_DEBUG; + else + debug_level = RAM_DEBUG; + + printk(debug_level, "%d.%d.%d.%d:%d.%d\n", dll_setting->coarse, + dll_setting->clk_delay, dll_setting->tap, + dll_setting->pi, dll_setting->db_en, + dll_setting->db_sel); } static void program_dll(struct sysinfo *s) @@ -1411,6 +1431,33 @@ } printk(BIOS_DEBUG, "MRS done\n"); } + +static void write_leveling(struct sysinfo *s) +{ + if (s->boot_path == BOOT_PATH_NORMAL) { + search_write_leveling(s); + } else { + /* TODO restore write leveling */ + } +} + +static void software_ddr3_reset(struct sysinfo *s) +{ + printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n"); + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x02; + MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80; + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x02; + MCHBAR8(0x5da) = (MCHBAR8(0x5da) & ~0x03) | 1; + udelay(200); + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x02; + MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x80; + MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80; + udelay(500); + MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x03; + MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x03; + jedec_ddr3(s); +} + static u8 sampledqs(u16 mchloc, u32 addr, u8 hilow, u8 repeat) { u8 dqsmatch = 1; @@ -2216,6 +2263,17 @@ MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x7; } + /* DDR3 reset */ + if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) { + printk(BIOS_DEBUG, "DDR3 Reset.\n"); + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x2; + MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x80; + udelay(500); + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x2; + MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80; + udelay(500); + } + // Pre jedec MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { @@ -2232,6 +2290,12 @@ jedec_ddr3(s); } + if (s->spd_type == DDR3) { + write_leveling(s); + if (s->boot_path == BOOT_PATH_NORMAL) + software_ddr3_reset(s); + } + printk(BIOS_DEBUG, "Done jedec steps\n"); // After JEDEC reset diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index 3349f62..e3001f2 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -134,7 +134,7 @@ {7, 6, 0, 0, 0, 0}, {9, 2, 1, 0, 0, 0}, {9, 2, 1, 0, 0, 0}, - {2, 5, 1, 1, 1, 0}, + {2, 5, 1, 1, 1, 0}, /* DQS1 */ {5, 1, 0, 0, 1, 0}, {6, 6, 0, 0, 1, 0}, {8, 0, 0, 0, 1, 0}, @@ -158,7 +158,7 @@ {0, 6, 1, 1, 0, 0}, {2, 2, 1, 1, 0, 0}, {2, 2, 1, 1, 0, 0}, - {6, 4, 0, 0, 0, 0}, + {6, 4, 0, 0, 0, 0}, /* DQS1 */ {9, 1, 1, 0, 0, 0}, {10, 6, 1, 0, 0, 0}, {1, 0, 1, 1, 1, 0}, diff --git a/src/northbridge/intel/x4x/spd_ddr3_decode.c b/src/northbridge/intel/x4x/spd_ddr3_decode.c index eab0548..857f6e7 100644 --- a/src/northbridge/intel/x4x/spd_ddr3_decode.c +++ b/src/northbridge/intel/x4x/spd_ddr3_decode.c @@ -82,6 +82,7 @@ } min_tCLK = MAX(min_tCLK, saved_timings->min_tclk); + min_tCLK = TCK_400MHZ; /* Hardcode since write leveling does not work */ normalize_tCLK(&min_tCLK); if (min_tCLK == 0) { printk(BIOS_ERR, "DRAM frequency is under lowest supported " -- To view, visit https://review.coreboot.org/19878 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ibfbaa235bc4eb08e9345321b851e880390a624e8 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS t...
by Arthur Heymans (Code Review) 24 May '17

24 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19879 ) Change subject: [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS training ...................................................................... [WIP]nb/intel/x4x/raminit: Implement read and write DQ DQS training This is not DDR3 specific. Change-Id: I806840445b5e768d079910fb9870a2cee7b9f1ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/dq_dqsl_dll.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/x4x.h 3 files changed, 462 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/19879/1 diff --git a/src/northbridge/intel/x4x/dq_dqsl_dll.c b/src/northbridge/intel/x4x/dq_dqsl_dll.c index a1dea68..b7697d4 100644 --- a/src/northbridge/intel/x4x/dq_dqsl_dll.c +++ b/src/northbridge/intel/x4x/dq_dqsl_dll.c @@ -437,3 +437,447 @@ printk(BIOS_DEBUG, "Done write levelling.\n"); } + +static const u32 write_training_schedule[] = { + 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, + 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, + 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, + 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, + 0xefefefef, 0x10101010, 0xefefefef, 0x10101010, + 0xefefefef, 0x10101010, 0xefefefef, 0x10101010, + 0xefefefef, 0x10101010, 0xefefefef, 0x10101010, + 0xefefefef, 0x10101010, 0xefefefef, 0x10101010, + 0xefefefef, 0xeeeeeeee, 0x11111111, 0x10101010, + 0xefefefef, 0xeeeeeeee, 0x11111111, 0x10101010, + 0xefefefef, 0xeeeeeeee, 0x11111111, 0x10101010, + 0xefefefef, 0xeeeeeeee, 0x11111111, 0x10101010, + 0x03030303, 0x04040404, 0x09090909, 0x10101010, + 0x21212121, 0x40404040, 0x81818181, 0x00000000, + 0x03030303, 0x04040404, 0x09090909, 0x10101010, + 0x21212121, 0x40404040, 0x81818181, 0x00000000, + 0xfdfdfdfd, 0xfafafafa, 0xf7f7f7f7, 0xeeeeeeee, + 0xdfdfdfdf, 0xbebebebe, 0x7f7f7f7f, 0xfefefefe, + 0xfdfdfdfd, 0xfafafafa, 0xf7f7f7f7, 0xeeeeeeee, + 0xdfdfdfdf, 0xbebebebe, 0x7f7f7f7f, 0xfefefefe, +}; + +#define PATTERN_SIZE 80 + +static int test_dq_aligned(struct sysinfo *s, u8 channel, u32 address) +{ + u8 error_found = 0, lane, count; + u8 data[8]; + u16 i; + u32 content; + + for (i = 0; i < PATTERN_SIZE; i++) { + for (count = 0; count < PATTERN_SIZE; count++) { + if ((count % 16) == 0) + MCHBAR32(0xf90) = 1; + content = write_training_schedule[count]; + write32((u32 *)address + 8 * count, content); + write32((u32 *)address + 8 * count + 4, content); + } + + write32(&data[0], read32((u32 *)address + 8 * i)); + write32(&data[4], read32((u32 *)address + 8 * i + 4)); + for (lane = 0; lane < 8; lane++) { + if (data[lane] != (write_training_schedule[i] & 0xff)) + error_found |= (1 << lane); + } + /* No need to continue now */ + if (error_found == 0xff) + return 0xff; + } + return error_found; +} + +#define SUCCEEDING 0 +#define FAILING 1 +#define CONSISTENCY 10 + +/* + * This function finds either failing or succeeding writes by increasing DQ. + * When it has found a failing or succeeding setting it will increase DQ + * another 10 times to make sure the result is consistent. + * This means that the middle between failing and succeeding writes is shifted + * by 9 steps, which need to be substracted later. + */ +static int find_dq_limit(struct sysinfo *s, u8 channel, u32 address, + struct dll_setting *dq_setting, u8 *dq_lim, + u8 direction) +{ + int status; + u8 lane_passes[8] = { }; + u8 sample = 0xff; + u8 lane; + u8 lane_err; + + for (lane = 0; lane < 8; lane++) + dqset(channel, lane, &dq_setting[lane]); + + while(sample) { + status = 0; + /* TODO: This is probably more readable if done one lane at the time */ + lane_err = test_dq_aligned(s, channel, address); + lane_err ^= 0xff * direction; + for (lane = 0; lane < 8; lane++) { + if (lane_err & (1 << lane)) { + /* reuse function for DQ DLL settings */ + status = increment_dqs(s, &dq_setting[lane]); + dqset(channel, lane, &dq_setting[lane]); + dq_lim[lane]++; + } else if (lane_passes[lane] < CONSISTENCY) { + status = increment_dqs(s, &dq_setting[lane]); + dqset(channel, lane, &dq_setting[lane]); + dq_lim[lane]++; + lane_passes[lane]++; + } else if (lane_passes[lane] == CONSISTENCY) { + sample &= ~(1 << lane); + } + } + if (status) { + if (direction == 0) { + printk(BIOS_ERR, "Could not find good Write training settings\n"); + return 1; + } else { + break; + } + } + } + return 0; +} + +/* + * Increase DQ until writes succeed, then further increase DQ until it fails. + * Use the middle between this working lower limit and this failing upper + * limit. + */ +int do_write_training(struct sysinfo *s) +{ + int i; + u8 channel, lane; + u32 address; + u8 dq_lower_r0[8]; + u8 dq_upper_r0[8]; + u8 dq_lower_r2[8]; + u8 dq_upper_r2[8]; + u8 dq_center[8]; + struct dll_setting dq_setting[8]; + u8 dq_average; + u32 dq_absolute; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { + printk(BIOS_DEBUG, "Doing DQ write training on CH%d\n", channel); + address = 0x20000000 * channel; + for (i = 0; (i < RANKS_PER_CHANNEL) && !RANK_IS_POPULATED(s->dimms, channel, i); i++) + address += 128 * MiB; + + dq_average = 0; + dq_absolute = 0; + memset(dq_lower_r0, 0, sizeof(dq_lower_r0)); + memset(dq_lower_r2, 0, sizeof(dq_lower_r2)); + + memset(dq_center, 0, sizeof(dq_center)); + for (lane = 0; lane < 8; lane++) { + /* Start from DQS settings */ + s->dq_settings[channel][lane] = ddr3_dll_setting_800[s->nmode - 1][DQS1 + lane]; + dq_setting[lane] = ddr3_dll_setting_800[s->nmode - 1][DQS1 + lane]; /* TODO per freq */ + /* dq_setting[lane] = s->dqs_settings[channel][lane]; */ + } + + if (find_dq_limit(s, channel, address, dq_setting, dq_lower_r0, + SUCCEEDING)) { + printk(BIOS_CRIT, "Could not find working lower limit DQ setting\n"); + return -1; + } + printk(BIOS_DEBUG, "Lower Limit for DQ on rank 0:\n"); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, " ch%d, lane %d, #steps %d\n", + channel, lane, dq_lower_r0[lane]); + } + + memcpy(dq_upper_r0, dq_lower_r0, sizeof(dq_upper_r0)); + if (find_dq_limit(s, channel, address, dq_setting, dq_upper_r0, + FAILING)) { + printk(BIOS_CRIT, "Could not find failing upper limit DQ setting\n"); + return -1; + } + + printk(BIOS_DEBUG, "Upper Limit for DQ on rank 0:\n"); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, " ch%d, lane %d, #steps %d\n", + channel, lane, dq_upper_r0[lane]); + } + + if (RANK_IS_POPULATED(s->dimms, channel, 0) + && RANK_IS_POPULATED(s->dimms, channel, 2)) { + address += 256 * MiB; + + for (lane = 0; lane < 8; lane++) + dq_setting[lane] = s->dqs_settings[channel][lane]; /* TODO */ + + if (find_dq_limit(s, channel, address, dq_setting, dq_lower_r2, + SUCCEEDING)) { + printk(BIOS_CRIT, "Could not find working lower limit DQ setting\n"); + return -1; + } + printk(BIOS_DEBUG, "Lower Limit for DQ on rank 2:\n"); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, " ch%d, lane %d, #steps %d\n", + channel, lane, dq_lower_r2[lane]); + } + + memcpy(dq_upper_r2, dq_lower_r2, sizeof(dq_upper_r2)); + if (find_dq_limit(s, channel, address, dq_setting, dq_upper_r2, + FAILING)) { + printk(BIOS_CRIT, "Could not find failing upper limit DQ setting\n"); + return -1; + } + printk(BIOS_DEBUG, "Upper Limit for DQ on rank 2:\n"); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, " ch%d, lane %d, #steps %d\n", + channel, lane, dq_upper_r2[lane]); + } + + for (lane = 0; lane < 8; lane++) { + dq_upper_r0[lane] = MIN(dq_upper_r0[lane], dq_upper_r2[lane]); + dq_lower_r0[lane] = MAX(dq_lower_r0[lane], dq_lower_r2[lane]); + } + } /* If Rank 2 is present */ + + for (lane = 0; lane < 8; lane++) { + dq_lower_r0[lane] -= 9; + dq_upper_r0[lane] -= 9; + } + + for (lane = 0; lane < 8; lane++) + dq_center[lane] = (dq_upper_r0[lane] + dq_lower_r0[lane]) / 2; + + printk(BIOS_DEBUG, "Centered values for DQ DLL:\n"); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, " ch%d, lane %d, #steps %d\n", + channel, lane, dq_center[lane]); + } + + /* Reset DQ DLL settings and increment with centered value*/ + for (lane = 0; lane < 8; lane++) { + dq_setting[lane] = ddr3_dll_setting_800[s->nmode - 1][DQS1 + lane]; + for (i = 0; i < dq_center[lane]; i++) + increment_dqs(s, &s->dq_settings[channel][lane]); + dqset(channel, lane, &s->dq_settings[channel][lane]); + } + } + return 0; +} + + +static void rt_set_dqs(u8 channel, u8 lane, struct rt_dqs_setting *dqs_setting) +{ + u8 saved_tap = MCHBAR8(0x540 + 0x400 * channel + lane * 4); + u8 saved_pi = MCHBAR8(0x542 + 0x400 * channel + lane * 4); + printk(RAM_SPEW, "RT DQS: ch%d, L%d, %d.%d, ", channel, lane, + dqs_setting->tap, + dqs_setting->pi); + + saved_tap &= ~0xf; + saved_tap |= dqs_setting->tap; + MCHBAR8(0x540 + 0x400 * channel + lane * 4) = saved_tap; + + saved_pi &= ~0x7; + saved_pi |= dqs_setting->pi; + MCHBAR8(0x542 + 0x400 * channel + lane * 4) = saved_pi; + printk(RAM_SPEW, " %d.%d\n", + MCHBAR8(0x540 + 0x400 * channel + lane * 4) & 0xf, + MCHBAR8(0x542 + 0x400 * channel + lane * 4) & 0x7); +} + +static int rt_increment_dqs(struct rt_dqs_setting *setting) +{ + if (setting->pi < 7) { + setting->pi++; + } else if (setting->tap < 14) { + setting->pi = 0; + setting->tap++; + } else { + return -1; + } + return 0; +} + +static u8 test_dqs_aligned(struct sysinfo *s, u8 channel, u32 address) +{ + u8 error_lane = 0; + u8 data8[8]; + int i, lane; + + for (i = 0; i < PATTERN_SIZE; i++) { + write32(&data8[0], read32((u32 *)address + i * 8)); + write32(&data8[4], read32((u32 *)address + i * 8 + 4)); + for (lane = 0; lane < 8; lane++) { + if (data8[lane] != (write_training_schedule[i] & 0xff)) + error_lane |= (1 << lane); + } + /* No need to continue now */ + if (error_lane == 0xff) + break; + + } + return error_lane; +} + +static int rt_find_dqs_limit(struct sysinfo *s, u8 channel, u32 address, + struct rt_dqs_setting *dqs_setting, u8 *dqs_lim, + u8 direction) +{ + int lane; + u8 sample = 0xff, lane_err; + + for (lane = 0; lane < 8; lane++) + rt_set_dqs(channel, lane, &dqs_setting[lane]); + + while(sample) { + /* TODO: This is probably more readable if done one lane at the time */ + lane_err = test_dqs_aligned(s, channel, address); + lane_err ^= 0xff * direction; + for (lane = 0; lane < 8; lane++) { + /* Checking lanes that have already been done is a good idea */ + /* since those can be found bad again. */ + if (lane_err & (1 << lane)) { + if (rt_increment_dqs(&dqs_setting[lane])) { + if (direction == SUCCEEDING) { + printk(BIOS_CRIT, "Could not find RT DQS setting\n"); + return -1; + } else { + sample &= ~(1 << lane); + continue; + } + } + dqs_lim[lane]++; + rt_set_dqs(channel, lane, &dqs_setting[lane]); + } else { + sample &= ~(1 << lane); + } + } + } + return 0; +} + +#define RT_LOOPS 3 + +/* + * Increase DQS until read succeed, then further increase DQS until it fails. + * Use the middle between this working lower limit and this failing upper + * limit. + * To improve statistics this is done RT_LOOPS amount of timings, while additioning + * the centered values to some saved values. At the end the saved values are divided + * by RT_LOOPS. + */ +int do_read_training(struct sysinfo *s) +{ + int loop, channel, i, lane; + u32 address, content; + u8 dqs_lower_r0[8]; + u8 dqs_upper_r0[8]; + u8 dqs_lower_r2[8]; + u8 dqs_upper_r2[8]; + u8 dqs_center[8]; + u16 saved_dqs[2][8] = { }; + + struct rt_dqs_setting dqs_setting[8]; + + for (loop = 0; loop < RT_LOOPS; loop++) { + FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { + printk(BIOS_DEBUG, "Doing DQS write training on CH%d\n", channel); + address = 0x20000000 * channel; + for (i = 0; !RANK_IS_POPULATED(s->dimms, channel, i) + && i < RANKS_PER_CHANNEL; i++) + address += 128 * MiB; + + /* Write pattern to strobe address*/ + for (i = 0; i < PATTERN_SIZE; i++) { + content = write_training_schedule[i]; + write32((u32 *)address + 8 * i, content); + write32((u32 *)address + 8 * i + 4, content); + } + + memset(dqs_lower_r0, 0, sizeof(dqs_lower_r0)); + memset(dqs_lower_r2, 0, sizeof(dqs_lower_r2)); + memset(dqs_setting, 0, sizeof(dqs_setting)); + + if (rt_find_dqs_limit(s, channel, address, dqs_setting, dqs_lower_r0, + SUCCEEDING)) { + printk(BIOS_CRIT, "Could not find working lower limit DQS setting\n"); + return -1; + } + printk(BIOS_DEBUG, "Lower Limit for DQS on rank 0:\n"); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, " ch%d, lane %d, #steps %d\n", + channel, lane, dqs_lower_r0[lane]); + } + + memcpy(dqs_upper_r0, dqs_lower_r0, sizeof(dqs_upper_r0)); + if (rt_find_dqs_limit(s, channel, address, dqs_setting, dqs_upper_r0, + FAILING)) { + printk(BIOS_CRIT, "Could not find failing upper limit DQ setting\n"); + return -1; + } + + printk(BIOS_DEBUG, "Upper Limit for DQS on rank 0:\n"); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, " ch%d, lane %d, #steps %d\n", + channel, lane, dqs_upper_r0[lane]); + } + + if (RANK_IS_POPULATED(s->dimms, channel, 0) + && RANK_IS_POPULATED(s->dimms, channel, 2)) { + address += 256 * MiB; + + memset(dqs_setting, 0 , sizeof(dqs_setting)); + + if (rt_find_dqs_limit(s, channel, address, dqs_setting, dqs_lower_r2, + SUCCEEDING)) { + printk(BIOS_CRIT, "Could not find working lower limit DQS setting\n"); + return -1; + } + printk(BIOS_DEBUG, "Lower Limit for DQS on rank 2:\n"); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, " ch%d, lane %d, #steps %d\n", + channel, lane, dqs_lower_r2[lane]); + } + + memcpy(dqs_upper_r2, dqs_lower_r2, sizeof(dqs_upper_r2)); + if (rt_find_dqs_limit(s, channel, address, dqs_setting, dqs_upper_r2, + FAILING)) { + printk(BIOS_CRIT, "Could not find failing upper limit DQS setting\n"); + return -1; + } + printk(BIOS_DEBUG, "Upper Limit for DQS on rank 2:\n"); + for (lane = 0; lane < 8; lane++) { + printk(BIOS_DEBUG, " ch%d, lane %d, #steps %d\n", + channel, lane, dqs_upper_r2[lane]); + } + + for (lane = 0; lane < 8; lane++) { + dqs_upper_r0[lane] = MIN(dqs_upper_r0[lane], dqs_upper_r2[lane]); + dqs_lower_r0[lane] = MAX(dqs_lower_r0[lane], dqs_lower_r2[lane]); + } + } /* end If Rank 2 is present */ + + for (lane = 0; lane < 8; lane++) { + dqs_center[lane] = (dqs_upper_r0[lane] + dqs_lower_r0[lane]) / 2; + saved_dqs[channel][lane] += dqs_center[lane]; + } + } /* END FOR_EACH_POPULATED_CHANNEL */ + } /* end RT_LOOPS */ + + FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { + for (lane = 0; lane < 8; lane++) { + saved_dqs[channel][lane] /= RT_LOOPS; + while (saved_dqs[channel][lane]--) /* check for overflow ? */ + rt_increment_dqs(&s->rt_dqs_setting[channel][lane]); + rt_set_dqs(channel, lane, &s->rt_dqs_setting[channel][lane]); + } + } + return 0; +} diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 9e7583c..ded519e 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -2363,9 +2363,14 @@ // XXX tRD - // XXX Write training + // Write training + if (do_write_training(s) && (s->selected_timings.mem_clk > MEM_CLOCK_667MHz)) + die("Write training Failed!\n"); // XXX Read training + if (do_read_training(s) && (s->selected_timings.mem_clk > MEM_CLOCK_667MHz)) + die("Read training Failed!\n"); + // DRADRB dradrb_ddr2(s); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index c2eea38..188654b 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -250,6 +250,11 @@ u8 coarse; }; +struct rt_dqs_setting { + u8 tap; + u8 pi; +}; + struct timings { unsigned int CAS; unsigned int tclk; @@ -292,6 +297,9 @@ struct dimminfo dimms[4]; u8 spd_map[4]; u8 nmode; + struct dll_setting dqs_settings[2][8]; + struct dll_setting dq_settings[2][8]; + struct rt_dqs_setting rt_dqs_setting[2][8]; }; #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_WARM_RESET 1 @@ -357,8 +365,12 @@ int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd, struct abs_timings *saved_timings, struct sysinfo *s); void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); +void search_write_leveling(struct sysinfo *s); void dqsset(u8 ch, u8 lane, const struct dll_setting *setting); void dqset(u8 ch, u8 lane, const struct dll_setting *setting); +void print_dll_setting(const struct dll_setting *dll_setting, u8 default_verbose); +int do_write_training(struct sysinfo *s); +int do_read_training(struct sysinfo *s); /* Look up tables Tables */ extern const struct dll_setting ddr2_dll_setting_667[23]; -- To view, visit https://review.coreboot.org/19879 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I806840445b5e768d079910fb9870a2cee7b9f1ca Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x/raminit: DDR3 specific ODT
by Arthur Heymans (Code Review) 24 May '17

24 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19876 ) Change subject: nb/intel/x4x/raminit: DDR3 specific ODT ...................................................................... nb/intel/x4x/raminit: DDR3 specific ODT Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 29 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/19876/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 28e242c..0d09c05 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1217,7 +1217,7 @@ static void program_odt(struct sysinfo *s) { u8 i; - u16 odt[16][2] = { + u16 ddr2_odt[16][2] = { { 0x0000, 0x0000 }, // NC_NC { 0x0000, 0x0001 }, // x8SS_NC { 0x0000, 0x0011 }, // x8DS_NC @@ -1236,10 +1236,35 @@ { 0x0101, 0x0404 }, // x16SS_x16SS }; + u16 ddr3_odt[16][2] = { + { 0x0000, 0x0000 }, // NC_NC + { 0x0000, 0x0001 }, // x8SS_NC + { 0x0000, 0x0021 }, // x8DS_NC + { 0x0000, 0x0001 }, // x16SS_NC + { 0x0004, 0x0000 }, // NC_x8SS + { 0x0105, 0x0405 }, // x8SS_x8SS + { 0x0105, 0x4465 }, // x8DS_x8SS + { 0x0105, 0x0405 }, // x16SS_x8SS + { 0x0084, 0x0000 }, // NC_x8DS + { 0x1195, 0x0405 }, // x8SS_x8DS + { 0x1195, 0x4465 }, // x8DS_x8DS + { 0x1195, 0x0405 }, // x16SS_x8DS + { 0x0004, 0x0000 }, // NC_x16SS + { 0x0105, 0x0405 }, // x8SS_x16SS + { 0x0105, 0x4465 }, // x8DS_x16SS + { 0x0105, 0x0405 }, // x16SS_x16SS + }; + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - MCHBAR16(0x400*i + 0x298) = odt[s->dimm_config[i]][1]; - MCHBAR16(0x400*i + 0x294) = odt[s->dimm_config[i]][0]; - MCHBAR16(0x400*i + 0x29c) = (MCHBAR16(0x400*i + 0x29c) & ~0xfff) | 0x66b; + if (s->spd_type == DDR2) { + MCHBAR16(0x400*i + 0x298) = ddr2_odt[s->dimm_config[i]][1]; + MCHBAR16(0x400*i + 0x294) = ddr2_odt[s->dimm_config[i]][0]; + } else { + MCHBAR16(0x400*i + 0x298) = ddr3_odt[s->dimm_config[i]][1]; + MCHBAR16(0x400*i + 0x294) = ddr3_odt[s->dimm_config[i]][0]; + } + MCHBAR16(0x400*i + 0x29c) = (MCHBAR16(0x400*i + 0x29c) & ~0xfff) | + (s->spd_type == DDR2 ? 0x66b : 0x778); MCHBAR32(0x400*i + 0x260) = (MCHBAR32(0x400*i + 0x260) & ~0x70e3c00) | 0x3063c00; } } -- To view, visit https://review.coreboot.org/19876 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit May 2017