Hello build bot (Jenkins), coreboot org,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19143
to look at the new patch set (#17).
Change subject: nb/x4x/raminit: Rewrite SPD decode and timing selection
......................................................................
nb/x4x/raminit: Rewrite SPD decode and timing selection
This is mostly written from scratch and uses common spd ddr2 decode
functions.
This improves the following:
* This fixes incorrect CAS/Freq detection on DDR2;
* Timings selection does not use loops;
* Removes ddr3 spd decode, since there is no DDR3 raminit. For this it
would be nice to use similar common functions for DDR3;
* Raminit would bail out if dimm was unsupported, now in some cases it
just marks the dimm slot as empty;
* It dramatically reduces stack usage since it does not allocate 4
times 256 bytes to store full SPDs, amongs other unused things that
were stored in sysinfo.
* Reports when no dimms are present.
* Uses i2c block read to read SPD which is about 5 times faster than
bytewise read.
TESTED: on ga-g41m-es2l.
Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr2.c
M src/northbridge/intel/x4x/x4x.h
3 files changed, 277 insertions(+), 382 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19143/17
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I760eeaa3bd4f2bc25a517ddb1b9533c971454071
Gerrit-PatchSet: 17
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Hello Aaron Durbin, Duncan Laurie, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19829
to look at the new patch set (#3).
Change subject: mainboard/google/poppy: Add PowerResource for touchscreen device
......................................................................
mainboard/google/poppy: Add PowerResource for touchscreen device
1. Do not enable touchscreen device by default in gpio configuration.
2. Select use of PowerResource for touchscreen device in devicetree so
that the ACPI subsystem can take care of powering on/off the
device. When system enters suspend, touchscreen device is powered off
and on resume, it is powered back on.
BUG=b:62028489
TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on
poppy.
Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/gpio.c
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
3 files changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/19829/3
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/19849 )
Change subject: console/flashsconsole: Add spi flash console for debugging
......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/#/c/19849/5/src/drivers/spi/flashconsole.c
File src/drivers/spi/flashconsole.c:
PS5, Line 18: #include <boot_device.h>
> This isn't needed.
boot_device_rw() is defined there.
PS5, Line 24: #include <spi_flash.h>
> This isn't needed.
Done
PS5, Line 26: 0x1000
> This is pretty big, fwiw. Some people might run out of CAR space. You prob
yeah, it was 0x100, then I changed it to 0x1000 when I started using that buffer to read the sectors to find 0xff. I should probably dial it down back down to 0x100 (or 128? biggest line I found in my log is 113 bytes), and use a local buffer in the init for the sectors.
PS5, Line 149: ||
> This should just remove the -1 as we'll flush when we reach full capacity.
Yeah, leftover from when I was using a '\0' to find the size of the line.
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Gerrit-MessageType: comment
Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3
Gerrit-PatchSet: 6
Gerrit-Project: coreboot
Gerrit-Branch: master
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Gerrit-HasComments: Yes
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19849
to look at the new patch set (#7).
Change subject: console/flashsconsole: Add spi flash console for debugging
......................................................................
console/flashsconsole: Add spi flash console for debugging
If CONSOLE_SPI_FLASH config is enabled, we can write the cbmem
messages to the 'CONSOLE' area in FMAP if the area is defined
or to the 'console' fil in CBFS which allows us to grab the
log when we read the flash.
This is useful when you don't have usb debugging, and
UART lines are hard to find. Since a failure to boot would
require a hardware flasher anyways, we can get the log
at the same time.
This feature should only be used when no alternative is
found and only when we can't boot the system, because
excessive writes to the flash is not recommended.
This has been tested on purism/librem13 v2 and librem 15 v3 which
run Intel Skylake hardware. It has not been tested on other archs
or with a driver other than the fast_spi.
Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3
Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm>
---
M src/console/Kconfig
M src/console/console.c
M src/drivers/spi/Makefile.inc
A src/drivers/spi/flashconsole.c
A src/include/console/flash.h
5 files changed, 276 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19849/7
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 )
Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/#/c/19759/9/src/soc/intel/common/block/include/…
File src/soc/intel/common/block/include/intelblocks/gpio.h:
PS9, Line 89: soc_gpe_route_to_gpio
I am thinking of removing this function - caller passes the config values for gpe0_dwx (from devicetree entry) into gpio_route_gpe. The only reason I had added this function was to handle the case where not all gpe0_dw1, 2 and 3 are available in devicetree
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19849
to look at the new patch set (#6).
Change subject: console/flashsconsole: Add spi flash console for debugging
......................................................................
console/flashsconsole: Add spi flash console for debugging
If CONSOLE_SPI_FLASH config is enabled, we can write the cbmem
messages to the 'CONSOLE' area in FMAP if the area is defined
or to the 'console' fil in CBFS which allows us to grab the
log when we read the flash.
This is useful when you don't have usb debugging, and
UART lines are hard to find. Since a failure to boot would
require a hardware flasher anyways, we can get the log
at the same time.
This feature should only be used when no alternative is
found and only when we can't boot the system, because
excessive writes to the flash is not recommended.
This has been tested on purism/librem13 v2 and librem 15 v3 which
run Intel Skylake hardware. It has not been tested on other archs
or with a driver other than the fast_spi.
Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3
Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm>
---
M src/console/Kconfig
M src/console/console.c
M src/drivers/spi/Makefile.inc
A src/drivers/spi/flashconsole.c
A src/include/console/flash.h
5 files changed, 276 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19849/6
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Gerrit-Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3
Gerrit-PatchSet: 6
Gerrit-Project: coreboot
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Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com>
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