coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block: Add Intel common UART code
by Aamir Bohra (Code Review) 30 Mar '17

30 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18952 to look at the new patch set (#6). Change subject: soc/intel/common/block: Add Intel common UART code ...................................................................... soc/intel/common/block: Add Intel common UART code Create Intel Common UART driver code. This code does below UART configuration for bootblock phase. * Program BAR * Configure reset register * Configure clock register Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/uart.h A src/soc/intel/common/block/uart/Kconfig A src/soc/intel/common/block/uart/Makefile.inc A src/soc/intel/common/block/uart/uart.c 4 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/18952/6 -- To view, visit https://review.coreboot.org/18952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/skylake: Use intel/common/uart driver
by Aamir Bohra (Code Review) 30 Mar '17

30 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19003 to look at the new patch set (#3). Change subject: soc/intel/skylake: Use intel/common/uart driver ...................................................................... soc/intel/skylake: Use intel/common/uart driver Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/uart.c M src/soc/intel/skylake/include/soc/bootblock.h 4 files changed, 11 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/19003/3 -- To view, visit https://review.coreboot.org/19003 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by build bot (Jenkins) (Code Review) 30 Mar '17

30 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18557 ) Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... Patch Set 16: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50972/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6943/ : SUCCESS -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 16 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Set sdcard card detect (CD) host owner...
by Venkateswarlu V Vinjamuri (Code Review) 30 Mar '17

30 Mar '17

Venkateswarlu V Vinjamuri has posted comments on this change. ( https://review.coreboot.org/18947 ) Change subject: soc/intel/apollolake: Set sdcard card detect (CD) host ownership ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/18947/6/src/soc/intel/apollolake/gpio.c File src/soc/intel/apollolake/gpio.c: PS6, Line 215: hostsw_reg_addr; > Yes, but that's with internal knowledge of HOSTSW_OWN_REG_BASE's value. Jus will change it -- To view, visit https://review.coreboot.org/18947 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I042a8762dc1f9cb73e6a24c1e7169c9746b2ee14 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/apollolake: Set sdcard card detect (CD) host owner...
by Venkateswarlu V Vinjamuri (Code Review) 30 Mar '17

30 Mar '17

Venkateswarlu V Vinjamuri has posted comments on this change. ( https://review.coreboot.org/18947 ) Change subject: soc/intel/apollolake: Set sdcard card detect (CD) host ownership ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/18947/6/src/soc/intel/apollolake/include/so… File src/soc/intel/apollolake/include/soc/nvs.h: Line 44: uint8_t hsad; /* 0x2F - HOSTSW_REG address */ > But you can calculate out the dw0 by knowing the community offset and multi It's possible to do that way as well. But we've already implemented generic functions in gpiolib.asl to extract port address and offset to work across all gpio communities. This logic is fully validated. Do we really need to remove that and add suggested logic? please let me know. -- To view, visit https://review.coreboot.org/18947 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I042a8762dc1f9cb73e6a24c1e7169c9746b2ee14 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/intel: Deduplicate vbt header
by build bot (Jenkins) (Code Review) 30 Mar '17

30 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18903 ) Change subject: nb/intel: Deduplicate vbt header ...................................................................... Patch Set 8: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/50971/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/6942/ : SUCCESS -- To view, visit https://review.coreboot.org/18903 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Reviewer: lava.coreboot.org <lavacoreboot(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common RTC code support
by Subrata Banik (Code Review) 30 Mar '17

30 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18558 ) Change subject: soc/intel/common/block: Add Intel common RTC code support ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/18558/3/src/soc/intel/common/block/rtc/rtc.c File src/soc/intel/common/block/rtc/rtc.c: PS3, Line 24: B_PCH_PCR_RTC_CONF_UCMOS_EN > Actually these are in pcr_ids.h from the SoC. What is the purpose of this c >>Either the IP is the same or its not IP is same, so we are good to keep the code inside common block. >> If it is the same then provide the registers in this compilation unit and use it if you see soc/pcr_id.h header between big core and small core, its majorly different because of Port ID (which make sense) but register wise RTC and ITSS are same, hence i thought of keeping those common registers into intelblocks/ but just 4-5 line common register set makes no value for a separate header. Hence i have decided to kept those common pieces also into respective soc/ directory. if you want i may pull those registers into this rtc.c file itself and remove from pcr_id.h alone in SKL and APL. -- To view, visit https://review.coreboot.org/18558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Use Ivybridge specific values
by build bot (Jenkins) (Code Review) 30 Mar '17

30 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/17606 ) Change subject: nb/intel/sandybridge/raminit: Use Ivybridge specific values ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50970/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6941/ : SUCCESS -- To view, visit https://review.coreboot.org/17606 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I49fdfe5ae3e65704d22e083e8446e3f1069869bc Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: libpayload: Fill reg_base for debugging purposes
by build bot (Jenkins) (Code Review) 30 Mar '17

30 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18600 ) Change subject: libpayload: Fill reg_base for debugging purposes ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50967/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6938/ : SUCCESS -- To view, visit https://review.coreboot.org/18600 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If42135c8e10b70d5ac9626521abd9cca3cf40053 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by Barnali Sarkar (Code Review) 30 Mar '17

30 Mar '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/18557 ) Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/#/c/18557/14/src/soc/intel/common/block/include… File src/soc/intel/common/block/include/intelblocks/fast_spi.h: Line 157: void enable_spibar(uintptr_t spi_base_address, device_t dev); > Why is get_fast_spi_bar() and fast_spi_flash_ctlr_reg_read() there? If you Okay, will check and fix these functions. >>>>> the other piece missing to this fast spi is the actually spi_flash interface. This is only providing one half of what is required when one is assuming fast spi is the boot medium. >>>>> I think you meant the flash_controller part of it. Right now, we have pushed the bootblock part of it. The Romstage flash_controller part implementation has been already started which will require these definitions of SPI PCI config space offset and MMIO Space offset. We will push that next. -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 14 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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coreboot-gerrit March 2017