coreboot-gerrit February 2017

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New patch to review for coreboot: mainboard/intel: common code for Intel boards
by Hannah Williams 23 Feb '17

23 Feb '17

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18468 -gerrit commit 0fdb249006394c5384ca729a56b4f9e62478c7c7 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Feb 14 09:32:28 2017 -0800 mainboard/intel: common code for Intel boards Change-Id: I704951c82ba09b7d8c606f4086ee2404169b3673 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/common/Kconfig | 49 +++++ src/mainboard/intel/common/Makefile.inc | 21 ++ src/mainboard/intel/common/boardid.c | 35 +++ src/mainboard/intel/common/bootblock.c | 32 +++ src/mainboard/intel/common/chromeos.c | 86 ++++++++ src/mainboard/intel/common/ec.c | 46 ++++ src/mainboard/intel/common/include/ec.h | 59 +++++ src/mainboard/intel/common/include/meminit.h | 99 +++++++++ src/mainboard/intel/common/include/variants.h | 48 +++++ src/mainboard/intel/common/mainboard.c | 79 +++++++ src/mainboard/intel/common/meminit_fsp2_atom.c | 284 +++++++++++++++++++++++++ src/mainboard/intel/common/meminit_fsp2_core.c | 64 ++++++ src/mainboard/intel/common/ramstage.c | 40 ++++ src/mainboard/intel/common/smihandler.c | 54 +++++ 14 files changed, 996 insertions(+) diff --git a/src/mainboard/intel/common/Kconfig b/src/mainboard/intel/common/Kconfig new file mode 100644 index 0000000..2eca9f4 --- /dev/null +++ b/src/mainboard/intel/common/Kconfig @@ -0,0 +1,49 @@ +config INTEL_MAINBOARD_COMMON + bool "Using Intel mainboard common" + default n + help + Common code for Intel mainboards + + +config MAINBOARD_COMMON_LPC_CONFIG + bool "Configure LPC from mainboard common" + default n + help + Configure LPC from mainboard common + + +config MAINBOARD_COMMON_GPIO_CONFIG + bool "Configure GPIO from mainboard common" + default n + help + Configure GPIO from mainboard common + +config HAVE_SPD + bool "Read data from SPD on SMBUS" + default n + help + Read data from SPD on SMBUS + +config HAVE_SPD_BIN + bool "Read data from spd.bin" + default n + help + Read data from spd.bin + +config MAINBOARD_COMMON_WRITE_ACPI_TABLES + bool "update acpi tables from mainboard common" + default n + help + update acpi tables from mainboard common + +config MAINBOARD_COMMON_FSP2_CORE + bool "Is this platform using FSP2.0 for CORE SOCs" + default n + help + Is this platform using FSP2.0 for CORE SOCs + +config MAINBOARD_COMMON_FSP2_ATOM + bool "Is this platform using FSP2.0 for ATOM SOCs" + default n + help + Is this platform using FSP2.0 for ATOM SOCs diff --git a/src/mainboard/intel/common/Makefile.inc b/src/mainboard/intel/common/Makefile.inc new file mode 100644 index 0000000..346fe7b --- /dev/null +++ b/src/mainboard/intel/common/Makefile.inc @@ -0,0 +1,21 @@ +#ifeq ($(CONFIG_INTEL_MAINBOARD_COMMON),y) + +bootblock-y += bootblock.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c +romstage-$(CONFIG_MAINBOARD_COMMON_FSP2_CORE) += meminit_fsp2_core.c +romstage-$(CONFIG_MAINBOARD_COMMON_FSP2_ATOM) += meminit_fsp2_atom.c + + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-y += mainboard.c +ramstage-y += boardid.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +CPPFLAGS_common += -I$(src)/mainboard/intel/common/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants +#endif diff --git a/src/mainboard/intel/common/boardid.c b/src/mainboard/intel/common/boardid.c new file mode 100644 index 0000000..25e1b17 --- /dev/null +++ b/src/mainboard/intel/common/boardid.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variants.h> +#include <ec/google/chromeec/ec.h> + +uint8_t __attribute__((weak)) variant_board_id(void) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + return google_chromeec_get_board_version(); + else + return 0; +} + +uint8_t __attribute__((weak)) variant_get_spd_index(void) +{ + return 0; +} + +size_t __attribute__((weak)) variant_memory_sku(void ) +{ + return 0; +} diff --git a/src/mainboard/intel/common/bootblock.c b/src/mainboard/intel/common/bootblock.c new file mode 100644 index 0000000..7001220 --- /dev/null +++ b/src/mainboard/intel/common/bootblock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variants.h> +#include <bootblock_common.h> +#include <soc/lpc.h> +#include <soc/gpio.h> +#include <variant/ec.h> + +void mainboard_ec_init(void); + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + if (IS_ENABLED(CONFIG_MAINBOARD_LPC_CONFIG)) + lpc_configure_pads();/* TODO Add bootblock_ec_init into soc folder as lpc_configure_ioport)*/ + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/common/chromeos.c b/src/mainboard/intel/common/chromeos.c new file mode 100644 index 0000000..5b6bd3a --- /dev/null +++ b/src/mainboard/intel/common/chromeos.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variants.h> +#include <boot/coreboot_tables.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, + gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_lid_switch(void) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + else + return 1; +} + +int get_developer_mode_switch(void) +{ + /* No physical developer mode switch. It's virtual. */ + return 0; +} + +int get_recovery_mode_switch(void) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Check if the EC has posted the keyboard recovery event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + return 0; +} + +int clear_recovery_mode_switch(void) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Clear keyboard recovery event. */ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + else + return 0; +} + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/common/ec.c b/src/mainboard/intel/common/ec.c new file mode 100644 index 0000000..7a5bda2 --- /dev/null +++ b/src/mainboard/intel/common/ec.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "./include/ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard: EC init\n"); + + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +} diff --git a/src/mainboard/intel/common/include/ec.h b/src/mainboard/intel/common/include/ec.h new file mode 100644 index 0000000..9fe3dad --- /dev/null +++ b/src/mainboard/intel/common/include/ec.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_COMMON_EC_H +#define MAINBOARD_COMMON_EC_H + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#endif diff --git a/src/mainboard/intel/common/include/meminit.h b/src/mainboard/intel/common/include/meminit.h new file mode 100644 index 0000000..bc45200 --- /dev/null +++ b/src/mainboard/intel/common/include/meminit.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_COMMON_MEMINIT_H_ +#define _MAINBOARD_COMMON_MEMINIT_H_ + +#include <stddef.h> +#include <stdint.h> + +/* + * There are 4 physical channels each 32-bits wide. There are 2 logical + * channels using 2 physical channels together to form a 64-bit interface to + * memory for each logical channel. + */ +enum { + DDR_PHYS_CH0A, + DDR_PHYS_CH0B, + DDR_PHYS_CH1A, + DDR_PHYS_CH1B, + DDR_NUM_PHYS_CHANNELS +}; + +/* Logical channel identification. */ +enum { + DDR_LCH0, + DDR_LCH1 +}; + +/* + * The DQs within a physical channel can be bit-swizzled within each byte. + * Within a channel the bytes can be swapped, but the DQs need to be routed + * with the corresponding DQS (strobe). + */ +enum { + DDR_DQS0, + DDR_DQS1, + DDR_DQS2, + DDR_DQS3, + DDR_NUM_BYTE_LANES, + DQ_BITS_PER_DQS = 8, +}; + +enum { + LP4_SPEED_1600, + LP4_SPEED_2133, + LP4_SPEED_2400, +}; + +/* LPDDR4 module density in bits. */ +enum { + DDR_8Gb_DENSITY = 2, + DDR_12Gb_DESNITY, + DDR_16Gb_DENSITY, +}; + +/* Provide bit swizzling per DQS and byte swapping within a channel. */ +struct ddr_chan_swizzle_cfg { + uint8_t dqs[DDR_NUM_BYTE_LANES][DQ_BITS_PER_DQS]; +}; + +struct ddr_swizzle_cfg { + struct ddr_chan_swizzle_cfg phys[DDR_NUM_PHYS_CHANNELS]; +}; + + +struct ddr_sku { + int speed; + int ch0_rank_density; + int ch1_rank_density; + int ch0_dual_rank; + int ch1_dual_rank; + const char *part_num; + bool disable_periodic_retraining; +}; + +struct ddr_cfg { + const struct ddr_sku *skus; + size_t num_skus; + const struct ddr_swizzle_cfg *swizzle_config; +}; + + +void save_lpddr4_dimm_info(const struct ddr_cfg *lpcfg, size_t mem_sku); +void override_ddr_defaults(FSP_M_CONFIG *cfg); +void soc_display_memory_init_params(FSP_M_CONFIG *fspm_cfg); + +#endif /* _MAINBOARD_COMMON_MEMINIT_H_ */ diff --git a/src/mainboard/intel/common/include/variants.h b/src/mainboard/intel/common/include/variants.h new file mode 100644 index 0000000..caa3399 --- /dev/null +++ b/src/mainboard/intel/common/include/variants.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Return the board id for the current variant board. */ +uint8_t variant_board_id(void); + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_sleep_gpio_table(size_t *num); + +/* Baseboard default swizzle. Can be reused if swizzle is same. */ +extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle; +/* Return LPDDR4 configuration structure. */ +const struct ddr_cfg *variant_ddr_config(void); +/* Return memory SKU for the board. */ +size_t variant_memory_sku(void); + +/* Return ChromeOS gpio table and fill in number of entries. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +/* Seed the NHLT tables with the board specific information. */ +struct nhlt; +void variant_nhlt_init(struct nhlt *nhlt); + +uint8_t variant_get_spd_index(void); + +#endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/intel/common/mainboard.c b/src/mainboard/intel/common/mainboard.c new file mode 100644 index 0000000..6b474bb --- /dev/null +++ b/src/mainboard/intel/common/mainboard.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <variants.h> +#include <boardid.h> +#include <console/console.h> +#include <device/device.h> +#include <nhlt.h> +#include <soc/gpio.h> +#include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <variant/ec.h> +#include <variant/gpio.h> + +void mainboard_ec_init(void); + +static void mainboard_init(device_t dev) +{ + size_t num; + const void *pads; + if (IS_ENABLED(CONFIG_MAINBOARD_GPIO_CONFIG)) { + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + } + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); +} + +#if IS_ENABLED(CONFIG_MAINBOARD_WRITE_ACPI_TABLES) +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + variant_nhlt_init(nhlt); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} +#endif + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +#if IS_ENABLED(CONFIG_MAINBOARD_WRITE_ACPI_TABLES) + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +#endif + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/common/meminit_fsp2_atom.c b/src/mainboard/intel/common/meminit_fsp2_atom.c new file mode 100644 index 0000000..2315955 --- /dev/null +++ b/src/mainboard/intel/common/meminit_fsp2_atom.c @@ -0,0 +1,284 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/byteorder.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <string.h> +#include <meminit.h> +#include <variants.h> +#include <smbios.h> +#include <memory_info.h> +#include <cbmem.h> +#include <fsp/util.h> + + +#define CONFIG_CHANNEL(log_num, phys_num, fspm_cfg, sku, chan) \ + fspm_cfg->Ch##phys_num##_DramDensity = \ + sku->ch##log_num##_rank_density; \ + fspm_cfg->Ch##phys_num##_RankEnable = \ + sku->ch##log_num##_dual_rank ? 0x1 : 0x3; \ + memcpy(&fspm_cfg->Ch##phys_num##_Bit_swizzling[0], \ + &(chan)->dqs[DDR_DQS0] ,DQ_BITS_PER_DQS); \ + memcpy(&fspm_cfg->Ch##phys_num##_Bit_swizzling[8], \ + &(chan)->dqs[DDR_DQS1],DQ_BITS_PER_DQS); \ + memcpy(&fspm_cfg->Ch##phys_num##_Bit_swizzling[16], \ + &(chan)->dqs[DDR_DQS2] ,DQ_BITS_PER_DQS); \ + memcpy(&fspm_cfg->Ch##phys_num##_Bit_swizzling[24], \ + &(chan)->dqs[DDR_DQS3],DQ_BITS_PER_DQS); + + +#define PRINT_CHANNEL_CONFIG(fspm_cfg, phys_num) \ +printk(BIOS_SPEW,"RankEnable : %x\n", \ + fspm_cfg->Ch##phys_num##_RankEnable); \ +printk(BIOS_SPEW,"DeviceWidth : %x\n", \ + fspm_cfg->Ch##phys_num##_DeviceWidth); \ +printk(BIOS_SPEW,"DramDensity : %x\n", \ + fspm_cfg->Ch##phys_num##_DramDensity); \ +printk(BIOS_SPEW,"Option : %x\n", \ + fspm_cfg->Ch##phys_num##_Option); \ +printk(BIOS_SPEW,"OdtConfig : %x\n", \ + fspm_cfg->Ch##phys_num##_OdtConfig); \ +printk(BIOS_SPEW,"TristateClk1 : %x\n", \ + fspm_cfg->Ch##phys_num##_TristateClk1); \ +printk(BIOS_SPEW,"Mode2N : %x\n", \ + fspm_cfg->Ch##phys_num##_Mode2N); \ +printk(BIOS_SPEW,"OdtLevels : %x\n", \ + fspm_cfg->Ch##phys_num##_OdtLevels); \ +{ \ +int i; \ + printk(BIOS_SPEW,"Bit_swizzling:\n"); \ + for(i=0; i < 32; i++) \ + { \ + printk(BIOS_SPEW," %02d ", \ + fspm_cfg->Ch##phys_num##_Bit_swizzling[i]); \ + if((i) && (i%8) == 7) \ + printk(BIOS_SPEW,"\n"); \ + } \ + printk(BIOS_SPEW,"\n"); \ +} + +__attribute__((weak)) void override_ddr_defaults(FSP_M_CONFIG *cfg) +{ + return; +} + +static void set_ddr_defaults(FSP_M_CONFIG *cfg) +{ + /* Enable memory down BGA since it's the only LPDDR4 packaging. */ + cfg->Package = 1; + cfg->MemoryDown = 1; + + cfg->ScramblerSupport = 1; + cfg->ChannelHashMask = 0x36; + cfg->SliceHashMask = 0x9; + cfg->InterleavedMode = 2; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 1; + /* Don't enforce a memory size limit. */ + cfg->MemorySizeLimit = 0; + /* Use a 2GiB I/O hole -- field is in MiB units. */ + cfg->LowMemoryMaxValue = 2 * (GiB/MiB); + /* No restrictions on memory above 4GiB */ + cfg->HighMemoryMaxValue = 0; + + /* Always default to attempt to use saved training data. */ + cfg->DisableFastBoot = 0; + + /* memory down so no SPD addresses. */ + cfg->DIMM0SPDAddress = 0; + cfg->DIMM1SPDAddress = 0; + + /* Clear all the rank enables. */ + cfg->Ch0_RankEnable = 0x0; + cfg->Ch1_RankEnable = 0x0; + cfg->Ch2_RankEnable = 0x0; + cfg->Ch3_RankEnable = 0x0; + + /* + * Set the device width to x16 which is half a LPDDR4 module as that's + * what the reference code expects. + */ + cfg->Ch0_DeviceWidth = 0x1; + cfg->Ch1_DeviceWidth = 0x1; + cfg->Ch2_DeviceWidth = 0x1; + cfg->Ch3_DeviceWidth = 0x1; + + /* + * Enable bank hashing (bit 1) and rank interleaving (bit 0) with + * a 1KiB address mapping (bits 5:4). + */ + cfg->Ch0_Option = 0x3; + cfg->Ch1_Option = 0x3; + cfg->Ch2_Option = 0x3; + cfg->Ch3_Option = 0x3; + + /* Weak on-die termination. */ + cfg->Ch0_OdtConfig = 0; + cfg->Ch1_OdtConfig = 0; + cfg->Ch2_OdtConfig = 0; + cfg->Ch3_OdtConfig = 0; + override_ddr_defaults(cfg); +} + +static void set_ddr_profile(FSP_M_CONFIG *cfg, int speed) +{ + uint8_t profile; + + switch (speed) { + case LP4_SPEED_1600: + profile = 0x9; + break; + case LP4_SPEED_2133: + profile = 0xa; + break; + case LP4_SPEED_2400: + profile = 0xb; + break; + default: + printk(BIOS_WARNING, "Invalid DDR speed: %d\n", speed); + /* Set defaults. */ + speed = LP4_SPEED_1600; + profile = 0x9; + } + + printk(BIOS_INFO, "DDR speed is %dMHz\n", speed); + cfg->Profile = profile; +} + +void soc_display_memory_init_params(FSP_M_CONFIG *fspm_cfg) +{ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + printk(BIOS_SPEW, "Channel0:\n"); + PRINT_CHANNEL_CONFIG(fspm_cfg, 0); + printk(BIOS_SPEW, "Channel1:\n"); + PRINT_CHANNEL_CONFIG(fspm_cfg, 1); + printk(BIOS_SPEW, "Channel2:\n"); + PRINT_CHANNEL_CONFIG(fspm_cfg, 2); + printk(BIOS_SPEW, "Channel3:\n"); + PRINT_CHANNEL_CONFIG(fspm_cfg, 3); + +} + +__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *fspm_cfg = &mupd->FspmConfig; + const struct ddr_cfg *mem_cfg = variant_ddr_config(); + size_t sku_id = variant_memory_sku(); + const struct ddr_sku *sku = &mem_cfg->skus[sku_id]; + const struct ddr_swizzle_cfg *scfg= mem_cfg->swizzle_config; + + set_ddr_defaults(fspm_cfg); + set_ddr_profile(fspm_cfg, sku->speed); + if (sku->ch0_rank_density) { + CONFIG_CHANNEL(0, 0, fspm_cfg, sku, + &scfg->phys[DDR_PHYS_CH0A] ); + CONFIG_CHANNEL(0, 1, fspm_cfg, sku, + &scfg->phys[DDR_PHYS_CH0B] ); + } + if (sku->ch1_rank_density) { + CONFIG_CHANNEL(1, 2, fspm_cfg, sku, + &scfg->phys[DDR_PHYS_CH1A] ); + CONFIG_CHANNEL(1, 3, fspm_cfg, sku, + &scfg->phys[DDR_PHYS_CH1B] ); + } + //cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining; + soc_display_memory_init_params(fspm_cfg); +} + +void mainboard_save_dimm_info(void) +{ + const struct ddr_cfg *cfg = variant_ddr_config(); + size_t mem_sku = variant_memory_sku(); + int channel, dimm, dimm_max, index; + size_t hob_size; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const CHANNEL_INFO *channel_info; + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + + if (mem_sku >= cfg->num_skus) { + printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", + mem_sku, cfg->num_skus); + return; + } + + memory_info_hob = fsp_find_smbios_memory_info(&hob_size); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { + if (index >= dimm_max) + break; + channel_info = &memory_info_hob->ChannelInfo[channel]; + for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { + if (index >= dimm_max) + break; + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (!src_dimm->SizeInMb) + continue; + + /* Populate the DIMM information */ + dest_dimm->dimm_size = src_dimm->SizeInMb; + dest_dimm->ddr_type = memory_info_hob->MemoryType; + dest_dimm->ddr_frequency = + memory_info_hob->MemoryFrequencyInMHz; + dest_dimm->channel_num = channel_info->ChannelId; + dest_dimm->dimm_num = src_dimm->DimmId; + strncpy((char *)dest_dimm->module_part_number, + cfg->skus[mem_sku].part_num, + sizeof(dest_dimm->module_part_number)); + + switch (memory_info_hob->DataWidth) { + case 8: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + case 16: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + case 32: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + case 64: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + case 128: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_128; + break; + default: + printk(BIOS_ERR, "Incorrect DIMM Data Width"); + } + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} diff --git a/src/mainboard/intel/common/meminit_fsp2_core.c b/src/mainboard/intel/common/meminit_fsp2_core.c new file mode 100644 index 0000000..2d894a7 --- /dev/null +++ b/src/mainboard/intel/common/meminit_fsp2_core.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <string.h> +#include <spd_bin.h> + +extern const uint8_t dq_map[][]; +extern const uint8_t dqs_map[][]; +extern const uint8_t rcomp_resistor[]; +extern const uint8_t rcomp_target[]; +extern const uint8_t dq_pins_interleaved; + +__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + u8 spd_index = variant_get_spd_index(); + + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); + memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); + + mem_cfg->DqPinsInterleaved = dq_pins_interleaved; + + if (IS_ENABLED(CONFIG_HAVE_SPD_BIN)) { + struct region_device spd_rdev; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + } else if (IS_ENABLED(CONFIG_HAVE_SPD)) { + struct spd_block blk; + + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0]; + } + else { + die("spd data not found\n"); + } + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; +} diff --git a/src/mainboard/intel/common/ramstage.c b/src/mainboard/intel/common/ramstage.c new file mode 100644 index 0000000..b3062cb --- /dev/null +++ b/src/mainboard/intel/common/ramstage.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/i2c.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> + +__attribute__((weak)) +void variant_mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + return; +} + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + variant_mainboard_silicon_init_params(params); +} + +__attribute__((weak)) void dev_init_exit(void *unused) +{ + /* add any board specific init here which needs to be run after + BS_POST_DEVICE */ + return; +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, dev_init_exit, NULL); diff --git a/src/mainboard/intel/common/smihandler.c b/src/mainboard/intel/common/smihandler.c new file mode 100644 index 0000000..8cfa61e --- /dev/null +++ b/src/mainboard/intel/common/smihandler.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <variants.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <soc/gpio.h> +#include "include/ec.h" +#include <variant/ec.h> +#include <variant/gpio.h> + +void mainboard_smi_gpi_handler(const struct gpi_status *sts) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (gpi_status_get(sts, EC_SMI_GPI)) + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(&num); + gpio_configure_pads(pads, num); + + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +}

1 0

New patch to review for coreboot: mainboard/google/poppy: Disable deep S3 on poppy
by Furquan Shaikh 23 Feb '17

23 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18467 -gerrit commit 0ce2359e0a51e67d412e8f27cb090f015872d9db Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Feb 22 16:42:04 2017 -0800 mainboard/google/poppy: Disable deep S3 on poppy BUG=chrome-os-partner:62963 BRANCH=None TEST=Compiles successfully Change-Id: Icb929262fd67362b8e5c5cf31dce04ab1f496695 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/poppy/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 2e60216..ba94713 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake - # Enable deep Sx states - register "deep_s3_enable" = "1" + # Deep Sx states + register "deep_s3_enable" = "0" register "deep_s5_enable" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"

1 0

Patch merged into coreboot/master: intel/minnow3: Implement and configure GPIO tables
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 6530b6d30dd5197ea855c608cecbcdcea8df9e32 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Feb 15 16:13:27 2017 -0700 intel/minnow3: Implement and configure GPIO tables Copy GPIO table implementation from the google/reef board except with board variant features removed. Also exlcude CrOS GPIO functions. Remove previous romstage GPIO implementation in brd_gpio.h and romstage.c. Configure GPIO settings for MinnowBoard 3. Change-Id: Id2817dcf2f8f196ecd13c810f7f0010a115db566 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> Reviewed-on: https://review.coreboot.org/18375 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18375 for details. -gerrit

1 0

Patch set updated for coreboot: intel/minnow3: Implement and configure GPIO tables
by Martin Roth 22 Feb '17

22 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18375 -gerrit commit 7ff6952a11ef6e16a39eaf5eef10ebd69a30dc17 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Feb 15 16:13:27 2017 -0700 intel/minnow3: Implement and configure GPIO tables Copy GPIO table implementation from the google/reef board except with board variant features removed. Also exlcude CrOS GPIO functions. Remove previous romstage GPIO implementation in brd_gpio.h and romstage.c. Configure GPIO settings for MinnowBoard 3. Change-Id: Id2817dcf2f8f196ecd13c810f7f0010a115db566 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/mainboard/intel/minnow3/Makefile.inc | 2 + src/mainboard/intel/minnow3/bootblock.c | 8 + src/mainboard/intel/minnow3/brd_gpio.h | 62 ------ src/mainboard/intel/minnow3/gpio.c | 351 +++++++++++++++++++++++++++++++ src/mainboard/intel/minnow3/gpio.h | 20 ++ src/mainboard/intel/minnow3/mainboard.c | 8 +- src/mainboard/intel/minnow3/romstage.c | 4 - 7 files changed, 388 insertions(+), 67 deletions(-) diff --git a/src/mainboard/intel/minnow3/Makefile.inc b/src/mainboard/intel/minnow3/Makefile.inc index 9e3e892..8d81a76 100644 --- a/src/mainboard/intel/minnow3/Makefile.inc +++ b/src/mainboard/intel/minnow3/Makefile.inc @@ -1,3 +1,5 @@ bootblock-y += bootblock.c +bootblock-y += gpio.c ramstage-y += mainboard.c +ramstage-y += gpio.c \ No newline at end of file diff --git a/src/mainboard/intel/minnow3/bootblock.c b/src/mainboard/intel/minnow3/bootblock.c index 3de44a8..b8da814 100644 --- a/src/mainboard/intel/minnow3/bootblock.c +++ b/src/mainboard/intel/minnow3/bootblock.c @@ -15,8 +15,16 @@ #include <bootblock_common.h> #include <soc/lpc.h> +#include "gpio.h" void bootblock_mainboard_init(void) { + const struct pad_config *pads; + size_t num; + lpc_configure_pads(); + + /* Configure GPIOs needed prior to ramstage. */ + pads = early_gpio_table(&num); + gpio_configure_pads(pads, num); } diff --git a/src/mainboard/intel/minnow3/brd_gpio.h b/src/mainboard/intel/minnow3/brd_gpio.h deleted file mode 100644 index 33b839b..0000000 --- a/src/mainboard/intel/minnow3/brd_gpio.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/gpio.h> - -#if ENV_ROMSTAGE - -static const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ - PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ - PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ - PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ - - PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), - - /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ - PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), - /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ - PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), - - PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ - PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ - PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ - PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ - PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ - - PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ - - PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), - PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), -}; - -#endif diff --git a/src/mainboard/intel/minnow3/gpio.c b/src/mainboard/intel/minnow3/gpio.c new file mode 100644 index 0000000..4e8f926 --- /dev/null +++ b/src/mainboard/intel/minnow3/gpio.c @@ -0,0 +1,351 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include "gpio.h" + +/* + * GPIO Pad configuration in ramstage. + */ +static const struct pad_config gpio_table_config[] = { + PAD_CFG_GPO(GPIO_0, 1, DEEP), + PAD_CFG_GPO(GPIO_1, 1, DEEP), + PAD_CFG_NF(GPIO_2, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_3, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_4, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_5, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_6, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_7, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_8, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_9, DN_20K, DEEP, NF1), + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), + PAD_CFG_NF(GPIO_11, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_12, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_13, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_14, DN_20K, DEEP, NF1), + PAD_CFG_GPO(GPIO_15, 1, DEEP), + PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), + PAD_CFG_NF(GPIO_17, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_18, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_19, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_20, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_21, DN_20K, DEEP, NF1), + PAD_CFG_GPO(GPIO_22, 1, DEEP),/* Power Enable */ + PAD_CFG_GPO(GPIO_23, 1, DEEP),/* LB USB Power */ + PAD_CFG_NF(GPIO_24, DN_20K, DEEP, NF5),/* SATA_DEVSLP0 */ + PAD_CFG_GPI(GPIO_25, DN_20K, DEEP),/* OSS MD/DA SCI */ + PAD_CFG_NF(GPIO_26, DN_20K, DEEP, NF5),/* SATA_LEDN */ + PAD_CFG_GPO(GPIO_27, 1, DEEP),/* DFU */ + PAD_CFG_NF(GPIO_28, DN_20K, DEEP, NF2), + PAD_CFG_NF(GPIO_29, DN_20K, DEEP, NF2), + PAD_CFG_NF(GPIO_30, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_31, DN_20K, DEEP, NF5),/* SUSCLK1 */ + PAD_CFG_NF(GPIO_32, DN_20K, DEEP, NF5), + PAD_CFG_NF(GPIO_33, DN_20K, DEEP, NF5),/* SUSCLK3 */ + /* PWM */ + PAD_CFG_NF(GPIO_34, DN_20K, DEEP, NF1),/* PWM */ + PAD_CFG_GPO(GPIO_35, 1, DEEP),/* Power Enable */ + PAD_CFG_NF(GPIO_36, DN_20K, DEEP, NF1),/* PWM */ + PAD_CFG_NF(GPIO_37, NONE, DEEP, NF1),/* Reset */ + /* UART */ + PAD_CFG_NF(GPIO_38, UP_20K, DEEP, NF1),/* LPSS_UART0_RXD */ + PAD_CFG_NF(GPIO_39, UP_20K, DEEP, NF1),/* LPSS_UART0_TXD */ + PAD_CFG_NF(GPIO_40, UP_20K, DEEP, NF1),/* LPSS_UART0_RTS_B */ + PAD_CFG_NF(GPIO_41, UP_20K, DEEP, NF1),/* LPSS_UART0_CTS_B */ + PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1),/* LPSS_UART1_RXD */ + PAD_CFG_NF(GPIO_43, UP_20K, DEEP, NF1),/* LPSS_UART1_TXD */ + PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1),/* LPSS_UART1_RTS_B */ + PAD_CFG_NF(GPIO_45, NONE, DEEP, NF1),/* LPSS_UART1_CTS_B */ + + PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */ + + PAD_CFG_GPI(GPIO_48, UP_20K, DEEP),/* LPSS_UART2_RTS_B */ + PAD_CFG_NF(GPIO_49, UP_20K, DEEP, NF1),/* LPSS_UART2_CTS_B */ + PAD_CFG_GPO(GPIO_62, 0, DEEP),/* GP_CAMERASB00 */ + PAD_CFG_GPO(GPIO_63, 0, DEEP),/* GP_CAMERASB01 */ + PAD_CFG_GPO(GPIO_64, 0, DEEP),/* GP_CAMERASB02 */ + PAD_CFG_GPO(GPIO_65, 0, DEEP),/* GP_CAMERASB03 */ + PAD_CFG_GPO(GPIO_66, 0, DEEP),/* GP_CAMERASB04 */ + PAD_CFG_GPO(GPIO_67, 0, DEEP),/* GP_CAMERASB05 */ + PAD_CFG_GPO(GPIO_68, 0, DEEP),/* GP_CAMERASB06 */ + PAD_CFG_GPO(GPIO_69, 0, DEEP),/* GP_CAMERASB07 */ + PAD_CFG_GPO(GPIO_70, 0, DEEP),/* GP_CAMERASB08 */ + PAD_CFG_GPO(GPIO_71, 0, DEEP),/* GP_CAMERASB09 */ + PAD_CFG_GPO(GPIO_72, 0, DEEP),/* GP_CAMERASB10 */ + PAD_CFG_GPO(GPIO_73, 0, DEEP),/* GP_CAMERASB11 */ + PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), /* TCK */ + PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1),/* TRST_B */ + PAD_CFG_NF(TMS, UP_20K, DEEP, NF1),/* TMS */ + PAD_CFG_NF(TDI, UP_20K, DEEP, NF1),/* TDI */ + PAD_CFG_NF(CX_PMODE, NONE, DEEP, NF1),/* CX_PMODE */ + PAD_CFG_NF(CX_PREQ_B, UP_20K, DEEP, NF1),/* CX_PREQ_B */ + PAD_CFG_NF(JTAGX, UP_20K, DEEP, NF1),/* JTAGX */ + PAD_CFG_NF(CX_PRDY_B, UP_20K, DEEP, NF1),/* CX_PRDY_B */ + PAD_CFG_NF(TDO, UP_20K, DEEP, NF1),/* TDO */ + PAD_CFG_GPI(CNV_BRI_DT, DN_20K, DEEP),/* CNV_BRI_DT */ + PAD_CFG_GPI(CNV_BRI_RSP, DN_20K, DEEP),/* CNV_BRI_RSP */ + PAD_CFG_GPI(CNV_RGI_DT, DN_20K, DEEP),/* CNV_RGI_DT */ + PAD_CFG_GPI(CNV_RGI_RSP, DN_20K, DEEP),/* CNV_RGI_RSP */ + PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1),/* SVID0_ALERT_B */ + PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1),/* SVID0_DATA */ + PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1),/* SVID0_CLK */ + + /* North West Community */ + PAD_CFG_NF(GPIO_187, UP_20K, DEEP, NF1),/* DDI0_CTRL_DATA */ + PAD_CFG_NF(GPIO_188, UP_20K, DEEP, NF1),/* DDI0_CTRL_CLK */ + PAD_CFG_NF(GPIO_189, UP_20K, DEEP, NF1),/* DDI1_CTRL_DATA */ + PAD_CFG_NF(GPIO_190, UP_20K, DEEP, NF1),/* DDI1_CTRL_CLK */ + PAD_CFG_NF(GPIO_191, DN_20K, DEEP, NF1),/* DBI_SDA */ + PAD_CFG_NF(GPIO_192, DN_20K, DEEP, NF1),/* DBI_SCL */ + PAD_CFG_NF(GPIO_193, DN_20K, DEEP, NF1),/* DISP0_VDDEN */ + PAD_CFG_NF(GPIO_194, DN_20K, DEEP, NF1),/* DISP0_BKLTEN */ + PAD_CFG_NF(GPIO_195, DN_20K, DEEP, NF1),/* DISP0_BLTCTL */ + PAD_CFG_GPO(GPIO_196, 1, DEEP),/* DISP1_VDDEN */ + PAD_CFG_GPO(GPIO_197, 1, DEEP),/* DISP1_BKLTEN */ + PAD_CFG_GPO(GPIO_198, 1, DEEP),/* DISP1_BLTCTL */ + PAD_CFG_NF(GPIO_199, DN_20K, DEEP, NF2),/* HDMI_HPD */ + PAD_CFG_NF(GPIO_200, DN_20K, DEEP, NF2),/* EDP_HPD */ + PAD_CFG_NF(GPIO_201, DN_20K, DEEP, NF1),/* DISP_INTD_TE1 */ + PAD_CFG_NF(GPIO_202, DN_20K, DEEP, NF1),/* DISP_INTD_TE2 */ + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1),/* HOST_USB_OC_N */ + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1),/* OTG_USB_OC_N */ + PAD_CFG_NF(PMC_SPI_FS0, UP_20K, DEEP, NF1),/* PMC_SPI_FS0 */ + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2),/* PMC_SPI_FS1 */ + PAD_CFG_NF(PMC_SPI_FS2, UP_20K, DEEP, NF1),/* PMC_SPI_FS2 */ + PAD_CFG_NF(PMC_SPI_RXD, DN_20K, DEEP, NF1),/* PMC_SPI_RXD */ + PAD_CFG_NF(PMC_SPI_TXD, DN_20K, DEEP, NF1),/* PMC_SPI_TXD */ + PAD_CFG_NF(PMC_SPI_CLK, DN_20K, DEEP, NF1),/* PMC_SPI_CLK */ + PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP),/* PMIC_PWRGOOD */ + PAD_CFG_GPI(PMIC_RESET_B, NONE, DEEP),/* PMIC_RESET_B */ + PAD_CFG_GPO(GPIO_213, 0xFF, DEEP),/* PMIC_SDWN_B */ + PAD_CFG_GPO(GPIO_214, 1, DEEP),/* PMIC_BCUDISW2 */ + PAD_CFG_GPO(GPIO_215, 1, DEEP),/* PMIC_BCUDISCRIT */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1),/* PMIC_THERMTRIP_B */ + PAD_CFG_GPO(PMIC_STDBY, 1, DEEP),/* PMIC_STDBY */ + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1),/* PROCHOT_B */ + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1),/* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1),/* PMIC_I2C_SDA */ + + PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1),/* AVS_I2S1_MCLK */ + PAD_CFG_NF(GPIO_75, DN_20K, DEEP, NF1),/* AVS_I2S1_BCLK */ + PAD_CFG_GPO(GPIO_76, 1, DEEP),/* AVS_I2S1_WS_SYNC */ + PAD_CFG_GPI(GPIO_77, DN_20K, DEEP),/* AVS_I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, DN_20K, DEEP),/* AVS_I2S1_SDO */ + PAD_CFG_NF(GPIO_79, DN_20K, DEEP, NF1),/* AVS_M_CLK_A1 */ + PAD_CFG_NF(GPIO_80, DN_20K, DEEP, NF1),/* AVS_M_CLK_B1 */ + PAD_CFG_NF(GPIO_81, DN_20K, DEEP, NF1),/* AVS_M_DATA_1 */ + PAD_CFG_NF(GPIO_82, DN_20K, DEEP, NF1),/* AVS_M_CLK_AB2 */ + PAD_CFG_NF(GPIO_83, DN_20K, DEEP, NF1),/* AVS_M_DATA_2 */ + PAD_CFG_NF(GPIO_84, DN_20K, DEEP, NF2),/* AVS_I2S2_MCLK */ + PAD_CFG_NF(GPIO_85, DN_20K, DEEP, NF1),/* AVS_I2S2_BCLK */ + PAD_CFG_NF(GPIO_86, DN_20K, DEEP, NF1),/* AVS_I2S2_WS_SYNC */ + PAD_CFG_NF(GPIO_87, DN_20K, DEEP, NF1),/* AVS_I2S2_SDI */ + PAD_CFG_NF(GPIO_88, DN_20K, DEEP, NF1),/* AVS_I2S2_SDO */ + PAD_CFG_NF(GPIO_89, DN_20K, DEEP, NF1),/* AVS_I2S3_BCLK */ + PAD_CFG_NF(GPIO_90, DN_20K, DEEP, NF1),/* AVS_I2S3_WS_SYNC */ + PAD_CFG_NF(GPIO_91, DN_20K, DEEP, NF1),/* AVS_I2S3_SDI */ + PAD_CFG_NF(GPIO_92, DN_20K, DEEP, NF1),/* AVS_I2S3_SDO */ + PAD_CFG_NF(GPIO_97, NONE, DEEP, NF1),/* FST_SPI_CS0_B */ + PAD_CFG_NF(GPIO_98, NONE, DEEP, NF1),/* FST_SPI_CS1_B */ + PAD_CFG_NF(GPIO_99, NONE, DEEP, NF1),/* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF(GPIO_100, NONE, DEEP, NF1),/* FST_SPI_MISO_IO1 */ + PAD_CFG_NF(GPIO_101, NONE, DEEP, NF1),/* FST_SPI_IO2 */ + PAD_CFG_NF(GPIO_102, NONE, DEEP, NF1),/* FST_SPI_IO3 */ + PAD_CFG_NF(GPIO_103, NONE, DEEP, NF1),/* FST_SPI_CLK */ + PAD_CFG_NF(FST_SPI_CLK_FB, NONE, DEEP, NF1),/* FST_SPI_CLK_FB */ + PAD_CFG_NF(GPIO_104, DN_20K, DEEP, NF1),/* GP_SSP_0_CLK */ + PAD_CFG_NF(GPIO_105, DN_20K, DEEP, NF1),/* GP_SSP_0_FS0 */ + PAD_CFG_NF(GPIO_106, DN_20K, DEEP, NF3),/* GP_SSP_0_FS1 */ + PAD_CFG_NF(GPIO_109, DN_20K, DEEP, NF1),/* GP_SSP_0_RXD */ + PAD_CFG_NF(GPIO_110, DN_20K, DEEP, NF1),/* GP_SSP_0_TXD */ + PAD_CFG_GPI(GPIO_111, DN_20K, DEEP),/* GP_SSP_1_CLK */ + PAD_CFG_NF(GPIO_112, DN_20K, DEEP, NF2),/* GP_SSP_1_FS0 */ + PAD_CFG_GPI(GPIO_113, DN_20K, DEEP),/* GP_SSP_1_FS1 */ + PAD_CFG_NF(GPIO_116, DN_20K, DEEP, NF2),/* GP_SSP_1_RXD */ + PAD_CFG_NF(GPIO_117, DN_20K, DEEP, NF2),/* GP_SSP_1_TXD */ + PAD_CFG_NF(GPIO_118, DN_20K, DEEP, NF1),/* GP_SSP_2_CLK */ + PAD_CFG_NF(GPIO_119, DN_20K, DEEP, NF1),/* GP_SSP_2_FS0 */ + PAD_CFG_NF(GPIO_120, DN_20K, DEEP, NF1),/* GP_SSP_2_FS1 */ + PAD_CFG_NF(GPIO_121, DN_20K, DEEP, NF1),/* GP_SSP_2_FS2 */ + PAD_CFG_NF(GPIO_122, DN_20K, DEEP, NF1),/* GP_SSP_2_RXD */ + PAD_CFG_NF(GPIO_123, DN_20K, DEEP, NF1),/* GP_SSP_2_TXD */ + + /* West Community */ + PAD_CFG_NF(GPIO_124, UP_1K, DEEP, NF1),/* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, UP_1K, DEEP, NF1),/* LPSS_I2C0_SCL */ + PAD_CFG_NF(GPIO_126, UP_1K, DEEP, NF1),/* LPSS_I2C1_SDA */ + PAD_CFG_NF(GPIO_127, UP_1K, DEEP, NF1),/* LPSS_I2C1_SCL */ + PAD_CFG_NF(GPIO_128, UP_1K, DEEP, NF1),/* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_1K, DEEP, NF1),/* LPSS_I2C2_SCL */ + PAD_CFG_NF(GPIO_130, UP_1K, DEEP, NF2),/* LPSS_I2C3_SDA */ + PAD_CFG_NF(GPIO_131, UP_1K, DEEP, NF2),/* LPSS_I2C3_SCL */ + PAD_CFG_NF(GPIO_132, UP_1K, DEEP, NF1),/* LPSS_I2C4_SDA */ + PAD_CFG_NF(GPIO_133, UP_1K, DEEP, NF1),/* LPSS_I2C4_SCL */ + + PAD_CFG_NF(GPIO_134, UP_20K, DEEP, NF2),/* ISH_I2C0_SDA */ + PAD_CFG_NF(GPIO_135, UP_20K, DEEP, NF2),/* ISH_I2C0_SCL */ + PAD_CFG_NF(GPIO_136, UP_20K, DEEP, NF2),/* ISH_I2C1_SDA */ + PAD_CFG_NF(GPIO_137, UP_20K, DEEP, NF2),/* ISH_I2C1_SCL */ + + PAD_CFG_NF(GPIO_138, UP_1K, DEEP, NF1),/* LPSS_I2C7_SDA */ + PAD_CFG_NF(GPIO_139, UP_1K, DEEP, NF1),/* LPSS_I2C7_SCL */ + PAD_CFG_NF(GPIO_146, DN_20K, DEEP, NF3),/* ISH_GPIO_0 */ + PAD_CFG_NF(GPIO_147, DN_20K, DEEP, NF3),/* ISH_GPIO_1 */ + PAD_CFG_NF(GPIO_148, DN_20K, DEEP, NF3),/* ISH_GPIO_2 */ + PAD_CFG_NF(GPIO_149, DN_20K, DEEP, NF3),/* ISH_GPIO_3 */ + PAD_CFG_NF(GPIO_150, DN_20K, DEEP, NF2),/* ISH_GPIO_4 */ + + PAD_CFG_GPO(GPIO_151, 0, DEEP),/* ISH_GPIO_5 */ + PAD_CFG_NF(GPIO_152, DN_20K, DEEP, NF2),/* ISH_GPIO_6 */ + PAD_CFG_NF(GPIO_153, DN_20K, DEEP, NF1),/* ISH_GPIO_7 */ + PAD_CFG_GPO(GPIO_154, 1, DEEP),/* ISH_GPIO_8 */ + PAD_CFG_NF(GPIO_155, DN_20K, DEEP, NF2),/* ISH_GPIO_9 */ + + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1),/* PCIE_CLKREQ0_B */ + PAD_CFG_NF(GPIO_210, DN_20K, DEEP, NF1),/* PCIE_CLKREQ1_B */ + PAD_CFG_NF(GPIO_211, DN_20K, DEEP, NF1),/* PCIE_CLKREQ2_B */ + PAD_CFG_NF(GPIO_212, DN_20K, DEEP, NF1),/* PCIE_CLKREQ3_B */ + + PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1),/* OSC_CLK_OUT_0 */ + PAD_CFG_NF(OSC_CLK_OUT_1, DN_20K, DEEP, NF1),/* OSC_CLK_OUT_1 */ + PAD_CFG_NF(OSC_CLK_OUT_2, DN_20K, DEEP, NF1),/* OSC_CLK_OUT_2 */ + PAD_CFG_NF(OSC_CLK_OUT_3, DN_20K, DEEP, NF1),/* OSC_CLK_OUT_3 */ + PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP),/* OSC_CLK_OUT_4 */ + + PAD_CFG_NF(PMU_AC_PRESENT, DN_20K, DEEP, NF1),/*PMU_AC_PRESENT */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1),/* PMU_BATLOW_B */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1),/* PMU_PLTRST_B */ + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1),/* PMU_PWRBTN_B */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1),/* PMU_RESETBUTTON_B */ + PAD_CFG_NF(PMU_SLP_S0_B, NONE, DEEP, NF1),/* PMU_SLP_S0_B */ + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1),/* PMU_SLP_S3_B */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1),/* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP),/* PMU_WAKE_B */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1),/* SUS_STAT_B */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1),/* SUSPWRDNACK */ + + /* South West Community */ + PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1),/* PCIE_WAKE0_B */ + PAD_CFG_NF(GPIO_206, UP_20K, DEEP, NF1),/* PCIE_WAKE1_B */ + PAD_CFG_NF(GPIO_207, UP_20K, DEEP, NF1),/* PCIE_WAKE2_B */ + PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1),/* PCIE_WAKE3_B */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1),/* EMMC0_CLK */ + PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1),/* EMMC0_D0 */ + PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1),/* EMMC0_D1 */ + PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1),/* EMMC0_D2 */ + PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1),/* EMMC0_D3 */ + PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1),/* EMMC0_D4 */ + PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1),/* EMMC0_D5 */ + PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1),/* EMMC0_D6 */ + PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1),/* EMMC0_D7 */ + PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1),/* EMMC0_CMD */ + PAD_CFG_NF(GPIO_166, DN_20K, DEEP, NF1),/* SDIO_CLK */ + PAD_CFG_NF(GPIO_167, UP_20K, DEEP, NF1),/* SDIO_D0 */ + PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1),/* SDIO_D1 */ + PAD_CFG_NF(GPIO_169, UP_20K, DEEP, NF1),/* SDIO_D2 */ + PAD_CFG_NF(GPIO_170, UP_20K, DEEP, NF1),/* SDIO_D3 */ + PAD_CFG_NF(GPIO_171, UP_20K, DEEP, NF1),/* SDIO_CMD */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1),/* SDCARD_CLK */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1),/* SDCARD_CLK_FB */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1),/* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1),/* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1),/* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1),/* SDCARD_D3 */ + PAD_CFG_GPI(GPIO_177, NONE, DEEP),/* SDCARD_CD_B */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1),/* SDCARD_CMD */ + PAD_CFG_GPI(GPIO_186, DN_20K, DEEP),/* SDCARD_LVL_WP */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1),/* EMMC0_STROBE */ + PAD_CFG_GPO(GPIO_183, 0, DEEP),/* SDIO_PWR_DOWN_B */ + PAD_CFG_NF(SMB_ALERTB, UP_20K, DEEP, NF1),/* SMB_ALERTB */ + + PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1),/* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1),/* SMB_DATA */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),/* LPC_ILB_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1),/*LPC_CLKOUT0 */ + PAD_CFG_NF(LPC_CLKOUT1, NONE, DEEP, NF1),/* LPC_CLKOUT1 */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),/* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),/* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),/* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),/* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),/* LPC_CLKRUNB */ + PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1),/* LPC_FRAMEB */ +}; + +const struct pad_config *gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table_config); + return gpio_table_config; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table_config[] = { + PAD_CFG_NF(GPIO_134, UP_20K, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, UP_20K, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, UP_20K, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, UP_20K, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_1, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_2, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_3, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_4, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_5, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_6, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_7, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_8, DN_20K, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, UP_1K, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, UP_1K, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, DN_20K, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NONE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), +}; + +const struct pad_config *early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table_config); + return early_gpio_table_config; +} + +/* GPIO settings before entering sleep. */ +static const struct pad_config sleep_gpio_table_config[] = { +}; + +const struct pad_config *sleep_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(sleep_gpio_table_config); + return sleep_gpio_table_config; +} + diff --git a/src/mainboard/intel/minnow3/gpio.h b/src/mainboard/intel/minnow3/gpio.h new file mode 100644 index 0000000..60d5e31 --- /dev/null +++ b/src/mainboard/intel/minnow3/gpio.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +const struct pad_config *gpio_table(size_t *num); +const struct pad_config *early_gpio_table(size_t *num); +const struct pad_config *sleep_gpio_table(size_t *num); diff --git a/src/mainboard/intel/minnow3/mainboard.c b/src/mainboard/intel/minnow3/mainboard.c index f7a2ef1..f9e932e 100644 --- a/src/mainboard/intel/minnow3/mainboard.c +++ b/src/mainboard/intel/minnow3/mainboard.c @@ -14,10 +14,16 @@ */ #include <device/device.h> +#include "gpio.h" static void mainboard_init(void *chip_info) { - /* Nothing Here Yet */ + const struct pad_config *pads; + size_t num; + + /* Configure GPIOs in Ramstage */ + pads = gpio_table(&num); + gpio_configure_pads(pads, num); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/minnow3/romstage.c b/src/mainboard/intel/minnow3/romstage.c index 04cdad4..451e7b4 100644 --- a/src/mainboard/intel/minnow3/romstage.c +++ b/src/mainboard/intel/minnow3/romstage.c @@ -17,7 +17,6 @@ #include <soc/romstage.h> #include <fsp/api.h> #include <FspmUpd.h> -#include "brd_gpio.h" static const uint8_t Ch0_Bit_swizzling[] = { 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, @@ -46,9 +45,6 @@ static const uint8_t Ch3_Bit_swizzling[] = { void mainboard_memory_init_params(FSPM_UPD *memupd) { - /* setup early gpio before memory */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - /* DRAM Config settings */ memupd->FspmConfig.Package = 0x1; memupd->FspmConfig.Profile = 0xB;

1 0

Patch merged into coreboot/master: intel/minnow3: Configure memory properly
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 97f542efc285a4a2d7245f75cd5f871f5f60b890 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Feb 15 11:50:02 2017 -0700 intel/minnow3: Configure memory properly Set the proper memory configuration for the MinnowBoard 3. The current values are copied from intel/leafhill. Set the proper values for MinnowBoard 3. Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> Reviewed-on: https://review.coreboot.org/18374 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/18374 for details. -gerrit

1 0

Patch set updated for coreboot: intel/minnow3: Configure memory properly
by Martin Roth 22 Feb '17

22 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18374 -gerrit commit fe522eea1128fc942dc9820d2df346c281b73d3c Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Feb 15 11:50:02 2017 -0700 intel/minnow3: Configure memory properly Set the proper memory configuration for the MinnowBoard 3. The current values are copied from intel/leafhill. Set the proper values for MinnowBoard 3. Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/mainboard/intel/minnow3/romstage.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/minnow3/romstage.c b/src/mainboard/intel/minnow3/romstage.c index 5c784ba..04cdad4 100644 --- a/src/mainboard/intel/minnow3/romstage.c +++ b/src/mainboard/intel/minnow3/romstage.c @@ -61,7 +61,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.InterleavedMode = 0x2; memupd->FspmConfig.ChannelsSlicesEnable = 0x0; memupd->FspmConfig.MinRefRate2xEnable = 0x0; - memupd->FspmConfig.DualRankSupportEnable = 0x1; + memupd->FspmConfig.DualRankSupportEnable = 0x0; memupd->FspmConfig.RmtMode = 0x0; memupd->FspmConfig.MemorySizeLimit = 0x1800; memupd->FspmConfig.LowMemoryMaxValue = 0x0; @@ -69,7 +69,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.HighMemoryMaxValue = 0x0; memupd->FspmConfig.DIMM0SPDAddress = 0x0; memupd->FspmConfig.DIMM1SPDAddress = 0x0; - memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_RankEnable = 0x1; memupd->FspmConfig.Ch0_DeviceWidth = 0x1; memupd->FspmConfig.Ch0_DramDensity = 0x2; memupd->FspmConfig.Ch0_Option = 0x3; @@ -77,7 +77,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.Ch0_TristateClk1 = 0x0; memupd->FspmConfig.Ch0_Mode2N = 0x0; memupd->FspmConfig.Ch0_OdtLevels = 0x0; - memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_RankEnable = 0x1; memupd->FspmConfig.Ch1_DeviceWidth = 0x1; memupd->FspmConfig.Ch1_DramDensity = 0x2; memupd->FspmConfig.Ch1_Option = 0x3; @@ -85,7 +85,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.Ch1_TristateClk1 = 0x0; memupd->FspmConfig.Ch1_Mode2N = 0x0; memupd->FspmConfig.Ch1_OdtLevels = 0x0; - memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_RankEnable = 0x1; memupd->FspmConfig.Ch2_DeviceWidth = 0x1; memupd->FspmConfig.Ch2_DramDensity = 0x2; memupd->FspmConfig.Ch2_Option = 0x3; @@ -93,7 +93,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.Ch2_TristateClk1 = 0x0; memupd->FspmConfig.Ch2_Mode2N = 0x0; memupd->FspmConfig.Ch2_OdtLevels = 0x0; - memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_RankEnable = 0x1; memupd->FspmConfig.Ch3_DeviceWidth = 0x1; memupd->FspmConfig.Ch3_DramDensity = 0x2; memupd->FspmConfig.Ch3_Option = 0x3;

1 0

Patch merged into coreboot/master: mainboard/intel: Add MinnowBoard 3
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 35f03d902700e5a9d99a561516588169598b0f07 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Mon Feb 6 16:07:27 2017 -0700 mainboard/intel: Add MinnowBoard 3 This commit adds the initial scaffolding for the MinnowBoard 3 with Apollo Lake silicon. This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with name changes. Special adaptations for MinnowBoard 3 mainboard will follow in separate commits. Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> Reviewed-on: https://review.coreboot.org/18298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18298 for details. -gerrit

1 0

Patch merged into coreboot/master: commonlib/fsp.h: include sys/types.h for ssize_t
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit b89b2c50c591bfe308094e35ae45e32df0cb35e2 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Tue Feb 21 13:10:05 2017 +0100 commonlib/fsp.h: include sys/types.h for ssize_t This file reportedly didn't compile on SUSE Linux with gcc 4.3.4: [...] > HOSTCC cbfstool/fsp_relocate.o > In file included from coreboot/src/commonlib/fsp_relocate.c:18: > coreboot/src/commonlib/include/commonlib/fsp.h:26: error: > expected '=', ',', ';', 'asm' or '__attribute__' before > 'fsp_component_relocate' [...] According to POSIX-2008[1], sys/types.h defines ssize_t, so include it. This should not break coreboot code (as opposed to utils code), as we have a sys/types.h in src/include. [1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/18417 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18417 for details. -gerrit

1 0

Patch set updated for coreboot: commonlib/fsp.h: include sys/types.h for ssize_t
by Martin Roth 22 Feb '17

22 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18417 -gerrit commit 01e6e0e8939793119119fe963c752d35a12a05a4 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Tue Feb 21 13:10:05 2017 +0100 commonlib/fsp.h: include sys/types.h for ssize_t This file reportedly didn't compile on SUSE Linux with gcc 4.3.4: [...] > HOSTCC cbfstool/fsp_relocate.o > In file included from coreboot/src/commonlib/fsp_relocate.c:18: > coreboot/src/commonlib/include/commonlib/fsp.h:26: error: > expected '=', ',', ';', 'asm' or '__attribute__' before > 'fsp_component_relocate' [...] According to POSIX-2008[1], sys/types.h defines ssize_t, so include it. This should not break coreboot code (as opposed to utils code), as we have a sys/types.h in src/include. [1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/commonlib/include/commonlib/fsp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/commonlib/include/commonlib/fsp.h b/src/commonlib/include/commonlib/fsp.h index 84e2c98..a2a2fae 100644 --- a/src/commonlib/include/commonlib/fsp.h +++ b/src/commonlib/include/commonlib/fsp.h @@ -18,6 +18,7 @@ #include <stddef.h> #include <stdint.h> +#include <sys/types.h> /* * Relocate FSP held within buffer defined by size to new_addr. Returns < 0

1 0

Patch merged into coreboot/master: intel/i945: Fix up whitespace and indentation
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit bce7e33f234a498d7437f2677eff0084f540fd15 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Wed Feb 22 18:46:27 2017 +0100 intel/i945: Fix up whitespace and indentation Fix up the whitespace issues introduced in commit 39bfc6cb (nb/i945/raminit.c: Fix dll timings on 945GC). Change-Id: I3a4152866226401bc51c7fb1752aab541a4c72b0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18465 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> See https://review.coreboot.org/18465 for details. -gerrit

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coreboot-gerrit February 2017