coreboot-gerrit February 2017

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Patch set updated for coreboot: nb/i945/raminit: Use common ddr2 decode functions
by Arthur Heymans 22 Feb '17

22 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18305 -gerrit commit a93ba97329931876e6919d5aa1aca835a2a1ba08 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 6 22:40:14 2017 +0100 nb/i945/raminit: Use common ddr2 decode functions This simplifies computing dram timings a lot. This removes computation of rank size based on columns, rows, banks,... and uses the information in SPD byte 31. The result of this is that dimms with multiple asymmetric ranks are not supported anymore. These however are very rare and most likely never tested on this platform. Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/raminit.c | 603 ++++++----------------------------- src/northbridge/intel/i945/raminit.h | 6 +- 2 files changed, 106 insertions(+), 503 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1f79cf6..927965d 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,6 +28,7 @@ #include "i945.h" #include "chip.h" #include <cbmem.h> +#include <device/dram/ddr2.h> /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP @@ -315,8 +316,6 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; - /** * i945 supports two DIMMs, in two configurations: * @@ -357,9 +356,11 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) * */ - for (i = 0; i<(2 * DIMM_SOCKETS); i++) { + int i, j, spd_size; + spd_raw_data raw_spd; + + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i); - u8 reg8; /* Initialize the socket information with a sane value */ sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; @@ -368,31 +369,32 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) if (!sdram_capabilities_dual_channel() && (i >> 1)) continue; - printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + spd_size = spd_decode_spd_size_ddr2(spd_read_byte(device, 0)); + + for (j = 0; j < spd_size; j++) + raw_spd[j] = spd_read_byte(device, j); - if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) { - printk(BIOS_DEBUG, "N/A\n"); + if (spd_decode_ddr2(&sysinfo->dimm_info[i], raw_spd) + != SPD_STATUS_OK) continue; - } + if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + dram_print_spd_ddr2(&sysinfo->dimm_info[i]); - reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); - if (reg8 == ERROR_SCHEME_ECC) + if (sysinfo->dimm_info[i].flags.is_ecc) die("Error: ECC memory not supported by this chipset\n"); - reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); - if (reg8 & MODULE_BUFFERED) - die("Error: Buffered memory not supported by this chipset\n"); - if (reg8 & MODULE_REGISTERED) + if (spd_dimm_is_registered_ddr2(sysinfo->dimm_info[i].dimm_type)) die("Error: Registered memory not supported by this chipset\n"); - switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) { + printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + switch (sysinfo->dimm_info[i].width) { case 0x08: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { - case 1: + switch (sysinfo->dimm_info[i].ranks) { + case 2: printk(BIOS_DEBUG, "x8DDS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; break; - case 0: + case 1: printk(BIOS_DEBUG, "x8DS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; break; @@ -401,12 +403,12 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) } break; case 0x10: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { - case 1: + switch (sysinfo->dimm_info[i].ranks) { + case 2: printk(BIOS_DEBUG, "x16DS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; break; - case 0: + case 1: printk(BIOS_DEBUG, "x16SS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; break; @@ -417,15 +419,14 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) default: die("Unsupported DDR-II memory width.\n"); } - dimm_mask |= (1 << i); } - if (!dimm_mask) { die("No memory installed.\n"); } if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { + /* Possibly does not boot in this case */ printk(BIOS_INFO, "Channel 0 has no memory populated.\n"); } } @@ -438,7 +439,6 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) static void sdram_verify_package_type(struct sys_info * sysinfo) { int i; - /* Assume no stacked DIMMs are available until we find one */ sysinfo->package = 0; for (i = 0; i < 2*DIMM_SOCKETS; i++) { @@ -446,365 +446,86 @@ static void sdram_verify_package_type(struct sys_info * sysinfo) continue; /* Is the current DIMM a stacked DIMM? */ - if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4)) + if (sysinfo->dimm_info[i].flags.stacked) sysinfo->package = 1; } } -static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) -{ - int i; - u8 cas_mask; - - /* Setup CAS mask with all supported CAS Latencies */ - cas_mask = SPD_CAS_LATENCY_DDR2_3 | - SPD_CAS_LATENCY_DDR2_4 | - SPD_CAS_LATENCY_DDR2_5; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) - cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_ACCEPTABLE_CAS_LATENCIES); - } - - if (!cas_mask) { - die("No DDR-II modules with accepted CAS latencies found.\n"); - } - - return cas_mask; -} - -static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask) +static void select_cas_dramfreq(struct sys_info * sysinfo) { - int i, j, idx; - int lowest_common_cas = 0; - int max_ram_speed = 0; - - const u8 ddr2_speeds_table[] = { - 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ - 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ - 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ - }; - - const u8 spd_lookup_table[] = { - SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, - SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, - SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD - }; + u8 selected_cas; + u8 cas_mask = SPD_CAS_LATENCY_DDR2_3 | SPD_CAS_LATENCY_DDR2_4 + | SPD_CAS_LATENCY_DDR2_5; + u32 common_tCLK, min_tCLK = TCK_200MHZ; switch (sdram_capabilities_max_supported_memory_frequency()) { - case 400: max_ram_speed = 0; break; - case 533: max_ram_speed = 1; break; - case 667: max_ram_speed = 2; break; - } - - sysinfo->memory_frequency = 0; - sysinfo->cas = 0; - - if (cas_mask & SPD_CAS_LATENCY_DDR2_3) { - lowest_common_cas = 3; - } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) { - lowest_common_cas = 4; - } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) { - lowest_common_cas = 5; + case 400: min_tCLK = TCK_200MHZ; break; + case 533: min_tCLK = TCK_266MHZ; break; + case 667: min_tCLK = TCK_333MHZ; break; } - PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas); - - for (j = max_ram_speed; j>=0; j--) { - int freq_cas_mask = cas_mask; - - PRINTK_DEBUG("Probing Speed %d\n", j); - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - int device = get_dimm_spd_address(sysinfo, i); - int current_cas_mask; - - PRINTK_DEBUG(" DIMM: %d\n", i); - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { - continue; - } - - current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES); - - while (current_cas_mask) { - int highest_supported_cas = 0, current_cas = 0; - PRINTK_DEBUG(" Current CAS mask: %04x; ", current_cas_mask); - if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - highest_supported_cas = 5; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - highest_supported_cas = 4; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - highest_supported_cas = 3; - } else { - die("Invalid max. CAS.\n"); - } - if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - current_cas = 3; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - current_cas = 4; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - current_cas = 5; - } else { - die("Invalid CAS.\n"); - } - - idx = highest_supported_cas - current_cas; - PRINTK_DEBUG("idx=%d, ", idx); - PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx])); - PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1])); - - if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && - spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { - PRINTK_DEBUG(": OK\n"); - break; - } - - PRINTK_DEBUG(": Not fast enough!\n"); - - current_cas_mask &= ~(1 << (current_cas)); - } - freq_cas_mask &= current_cas_mask; - if (!current_cas_mask) { - PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", i); - break; - } - } - PRINTK_DEBUG(" freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask); - if (freq_cas_mask) { - switch (j) { - case 0: sysinfo->memory_frequency = 400; break; - case 1: sysinfo->memory_frequency = 533; break; - case 2: sysinfo->memory_frequency = 667; break; - } - if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - sysinfo->cas = 3; - } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - sysinfo->cas = 4; - } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - sysinfo->cas = 5; - } - break; - } - } - - if (sysinfo->memory_frequency && sysinfo->cas) { - printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n", - sysinfo->memory_frequency, sysinfo->cas); - } else { + common_tCLK = get_common_freq_cas(cas_mask, sysinfo->dimm_info, + 2 * DIMM_SOCKETS, &selected_cas); + if (common_tCLK == 0) die("Could not find common memory frequency and CAS\n"); - } -} + common_tCLK = MAX(common_tCLK, min_tCLK); -static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo) -{ - int i; - int tRAS_time; - int tRAS_cycles; - int freq_multiplier = 0; + sysinfo->cas = selected_cas; + sysinfo->tclk = common_tCLK; - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ + switch (sysinfo->tclk) { + case TCK_200MHZ: sysinfo->memory_frequency = 400; break; + case TCK_266MHZ: sysinfo->memory_frequency = 533; break; + case TCK_333MHZ: sysinfo->memory_frequency = 667; break; } - - tRAS_cycles = 4; /* 4 clocks minimum */ - tRAS_time = tRAS_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - if (!reg8) { - die("Invalid tRAS value.\n"); - } - - while ((tRAS_time >> 2) < reg8) { - tRAS_time += freq_multiplier; - tRAS_cycles++; - } - } - if (tRAS_cycles > 0x18) { - die("DDR-II Module does not support this frequency (tRAS error)\n"); - } - - printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles); - sysinfo->tras = tRAS_cycles; + printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n", + sysinfo->memory_frequency, sysinfo->cas); } -static void sdram_detect_smallest_tRP(struct sys_info * sysinfo) +static void select_dram_timings(struct sys_info * sysinfo) { int i; - int tRP_time; - int tRP_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tRP_cycles = 2; /* 2 clocks minimum */ - tRP_time = tRP_cycles * freq_multiplier; + int tCLK = sysinfo->tclk; + int tRAS_cycles, tRP_cycles, tRCD_cycles, tWR_cycles, tRFC_cycles; for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME); - if (!reg8) { - die("Invalid tRP value.\n"); - } - - while (tRP_time < reg8) { - tRP_time += freq_multiplier; - tRP_cycles++; - } - } - - if (tRP_cycles > 6) { - die("DDR-II Module does not support this frequency (tRP error)\n"); - } - - printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles); - sysinfo->trp = tRP_cycles; -} - -static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo) -{ - int i; - int tRCD_time; - int tRCD_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tRCD_cycles = 2; /* 2 clocks minimum */ - tRCD_time = tRCD_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY); - if (!reg8) { - die("Invalid tRCD value.\n"); - } - - while (tRCD_time < reg8) { - tRCD_time += freq_multiplier; - tRCD_cycles++; - } - } - if (tRCD_cycles > 6) { - die("DDR-II Module does not support this frequency (tRCD error)\n"); - } - - printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles); - sysinfo->trcd = tRCD_cycles; -} - -static void sdram_detect_smallest_tWR(struct sys_info * sysinfo) -{ - int i; - int tWR_time; - int tWR_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tWR_cycles = 2; /* 2 clocks minimum */ - tWR_time = tWR_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME); - if (!reg8) { - die("Invalid tWR value.\n"); - } - - while (tWR_time < reg8) { - tWR_time += freq_multiplier; - tWR_cycles++; - } - } - if (tWR_cycles > 5) { - die("DDR-II Module does not support this frequency (tWR error)\n"); - } - - printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles); - sysinfo->twr = tWR_cycles; -} - -static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo) -{ - int i, index = 0; - - const u8 tRFC_cycles[] = { - /* 75 105 127.5 */ - 15, 21, 26, /* DDR2-400 */ - 20, 28, 34, /* DDR2-533 */ - 25, 35, 43 /* DDR2-667 */ - }; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = sysinfo->banksize[i*2]; - switch (reg8) { - case 0x04: reg8 = 0; break; - case 0x08: reg8 = 1; break; - case 0x10: reg8 = 2; break; - case 0x20: reg8 = 3; break; - } - - if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS) - reg8++; - - if (reg8 > 3) { - /* Can this happen? Go back to 127.5ns just to be sure - * we don't run out of the array. This may be wrong - */ - printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i); - reg8 = 3; - } - - if (reg8 > index) - index = reg8; - - } - index--; - switch (sysinfo->memory_frequency) { - case 667: index += 3; /* Fallthrough */ - case 533: index += 3; /* Fallthrough */ - case 400: break; - } - - sysinfo->trfc = tRFC_cycles[index]; - printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]); + tRAS_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tRAS, tCLK); + if (tRAS_cycles > 0x18) + die("DDR-II Module does not support this frequency (tRAS error)\n"); + if (tRAS_cycles > sysinfo->tras) + sysinfo->tras = tRAS_cycles; + + tRP_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tRP, tCLK); + if (tRP_cycles > 6) + die("DDR-II Module does not support this frequency (tRP error)\n"); + if (tRP_cycles > sysinfo->trp) + sysinfo->trp = tRP_cycles; + + tRCD_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tRCD, tCLK); + if (tRCD_cycles > 6) + die("DDR-II Module does not support this frequency (tRCD error)\n"); + if (tRCD_cycles > sysinfo->trcd) + sysinfo->trcd = tRCD_cycles; + + tWR_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tWR, tCLK); + if (tWR_cycles > 5) + die("DDR-II Module does not support this frequency (tWR error)\n"); + if (tWR_cycles > sysinfo->twr) + sysinfo->twr = tWR_cycles; + + tRFC_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tRFC, tCLK); + if (tRFC_cycles > sysinfo->trfc) + sysinfo->trfc = tRFC_cycles; + + } + printk(BIOS_DEBUG, "tRAS = %d cycles\n", sysinfo->tras); + printk(BIOS_DEBUG, "tRP = %d cycles\n", sysinfo->trp); + printk(BIOS_DEBUG, "tRCD = %d cycles\n", sysinfo->trcd); + printk(BIOS_DEBUG, "tWR = %d cycles\n", sysinfo->twr); + printk(BIOS_DEBUG, "tRFC = %d cycles\n", sysinfo->trfc); } static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) @@ -819,23 +540,20 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_REFRESH) & ~(1 << 7); - - /* 15.6us */ - if (!refresh) - continue; + refresh = sysinfo->dimm_info[i].tRR; /* Refresh is slower than 15.6us, use 15.6us */ - if (refresh > 2) + /* tRR is decoded in units of 1/256us */ + if (refresh >= 15625 * 256) continue; - if (refresh == 2) { + if (refresh == 15625 * 256 / 2) { sysinfo->refresh = 1; break; } - die("DDR-II module has unsupported refresh value\n"); + if (refresh == 15625 * 256 / 4) + die("DDR-II module has unsupported refresh value\n"); } printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us"); } @@ -848,8 +566,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + if (!sysinfo->dimm_info[i].flags.bl8) die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); } } @@ -1376,121 +1093,26 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo) } } -struct dimm_size { - unsigned long side1; - unsigned long side2; -}; - -static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno) -{ - /* Calculate the log base 2 size of a DIMM in bits */ - struct dimm_size sz; - int value, low, rows, columns, device; - - device = get_dimm_spd_address(sysinfo, dimmno); - sz.side1 = 0; - sz.side2 = 0; - - rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ - if (rows < 0) goto hw_err; - if ((rows & 0xf) == 0) goto val_err; - sz.side1 += rows & 0xf; - - columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ - if (columns < 0) goto hw_err; - if ((columns & 0xf) == 0) goto val_err; - sz.side1 += columns & 0xf; - - value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */ - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side1 += log2(value & 0xff); - - /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */ - if (value < 0) goto hw_err; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */ - if (low < 0) goto hw_err; - value = value | (low & 0xff); - if ((value != 72) && (value != 64)) goto val_err; - sz.side1 += log2(value); - - /* side 2 */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */ - - if (value < 0) goto hw_err; - value &= 7; - value++; - if (value == 1) goto out; - if (value != 2) goto val_err; - - /* Start with the symmetrical case */ - sz.side2 = sz.side1; - - if ((rows & 0xf0) == 0) goto out; /* If symmetrical we are done */ - - /* Don't die here, I have not come across any of these to test what - * actually happens. - */ - printk(BIOS_ERR, "Asymmetric DIMMs are not supported by this chipset\n"); - - sz.side2 -= (rows & 0x0f); /* Subtract out rows on side 1 */ - sz.side2 += ((rows >> 4) & 0x0f); /* Add in rows on side 2 */ - - sz.side2 -= (columns & 0x0f); /* Subtract out columns on side 1 */ - sz.side2 += ((columns >> 4) & 0x0f); /* Add in columns on side 2 */ - - goto out; - - val_err: - die("Bad SPD value\n"); - hw_err: - /* If a hardware error occurs the spd ROM probably does not exist. - * In this case report that there is no memory - */ - sz.side1 = 0; - sz.side2 = 0; -out: - return sz; -} - static void sdram_detect_dimm_size(struct sys_info * sysinfo) { int i; for (i = 0; i < 2 * DIMM_SOCKETS; i++) { - struct dimm_size sz; - sysinfo->banksize[i * 2] = 0; sysinfo->banksize[(i * 2) + 1] = 0; if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - - sz = sdram_get_dimm_size(sysinfo, i); - - sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_NUM_BANKS_PER_SDRAM); /* banks */ - - if (sz.side1 < 30) + if (sysinfo->dimm_info[i].ranksize_mb < 128) die("DDR-II rank size smaller than 128MB is not supported.\n"); - sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28); - + sysinfo->banksize[i * 2] = sysinfo->dimm_info[i].ranksize_mb / 32; printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 ); - if (!sz.side2) + if (sysinfo->dimm_info[i].ranks == 1) continue; - /* If there is a second side, it has to have at least 128M, too */ - if (sz.side2 < 30) - die("DDR-II rank size smaller than 128MB is not supported.\n"); - - sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28); - + sysinfo->banksize[(i * 2) + 1] = sysinfo->dimm_info[i].ranksize_mb / 32; printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32); } } @@ -1564,25 +1186,19 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) static int sdram_set_row_attributes(struct sys_info *sysinfo) { - int i, value; + int i; u16 dra0 = 0, dra1 = 0, dra = 0; printk(BIOS_DEBUG, "Setting row attributes...\n"); for (i = 0; i < 2 * DIMM_SOCKETS; i++) { - u16 device; u8 columnsrows; if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { continue; } - device = get_dimm_spd_address(sysinfo, i); - - value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ - columnsrows = (value & 0x0f); - - value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ - columnsrows |= (value & 0xf) << 4; + columnsrows = (sysinfo->dimm_info[i].row_bits & 0x0f) + | (sysinfo->dimm_info[i].col_bits & 0xf) << 4; switch (columnsrows) { case 0x9d: dra = 2; break; @@ -1630,7 +1246,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (sysinfo->banks[i] != 8) + if (sysinfo->dimm_info[i].banks != 8) continue; printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i); @@ -3033,7 +2649,7 @@ static void sdram_setup_processor_side(void) void sdram_initialize(int boot_path, const u8 *spd_addresses) { struct sys_info sysinfo; - u8 reg8, cas_mask; + u8 reg8; printk(BIOS_DEBUG, "Setting up RAM controller.\n"); @@ -3051,20 +2667,11 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Check whether we have stacked DIMMs */ sdram_verify_package_type(&sysinfo); - /* Determine common CAS */ - cas_mask = sdram_possible_cas_latencies(&sysinfo); + /* Select common CAS latency and dram frequency */ + select_cas_dramfreq(&sysinfo); - /* Choose Common Frequency */ - sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask); - - /* Determine smallest common tRAS */ - sdram_detect_smallest_tRAS(&sysinfo); - - /* Determine tRP */ - sdram_detect_smallest_tRP(&sysinfo); - - /* Determine tRCD */ - sdram_detect_smallest_tRCD(&sysinfo); + /* Select nRAS, nRP, nRCD, nWR, tRFC */ + select_dram_timings(&sysinfo); /* Determine smallest refresh period */ sdram_detect_smallest_refresh(&sysinfo); @@ -3072,15 +2679,9 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Verify all DIMMs support burst length 8 */ sdram_verify_burst_length(&sysinfo); - /* determine tWR */ - sdram_detect_smallest_tWR(&sysinfo); - /* Determine DIMM size parameters (rows, columns banks) */ sdram_detect_dimm_size(&sysinfo); - /* determine tRFC */ - sdram_detect_smallest_tRFC(&sysinfo); - /* Program PLL settings */ sdram_program_pll_settings(&sysinfo); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 0554900..e8e5140 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -23,9 +23,12 @@ /* Burst length is always 8 */ #define BURSTLENGTH 8 +#include <device/dram/ddr2.h> + struct sys_info { u16 memory_frequency; /* 400, 533 or 667 */ u16 fsb_frequency; /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */ + u32 tclk; u8 trp; /* calculated by sdram_detect_smallest_tRP() */ u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */ @@ -50,14 +53,13 @@ struct sys_info { #define SYSINFO_PACKAGE_PLANAR 0x00 #define SYSINFO_PACKAGE_STACKED 0x01 u8 dimm[2 * DIMM_SOCKETS]; + dimm_attr dimm_info[2 * DIMM_SOCKETS]; #define SYSINFO_DIMM_X16DS 0x00 #define SYSINFO_DIMM_X8DS 0x01 #define SYSINFO_DIMM_X16SS 0x02 #define SYSINFO_DIMM_X8DDS 0x03 #define SYSINFO_DIMM_NOT_POPULATED 0x04 - u8 banks[2 * DIMM_SOCKETS]; - u8 banksize[2 * 2 * DIMM_SOCKETS]; const u8 *spd_addresses;

1 0

Patch set updated for coreboot: nb/intel/i945/raminit.c: Refactor tRD selection
by Arthur Heymans 22 Feb '17

22 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18354 -gerrit commit c1ea431fcb31dafe8d3efe377ba9b0899a45c1a3 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 12 23:34:39 2017 +0100 nb/intel/i945/raminit.c: Refactor tRD selection Inspired by gm45 code, which sets this value the same way. Some values for tRD on 800 and 1067MHz FSB were set wrong because the CAS/Freq selection was wrong. PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5 Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/raminit.c | 43 ++++++------------------------------ 1 file changed, 7 insertions(+), 36 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cc227cc..1f79cf6 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1720,21 +1720,11 @@ static void sdram_program_odt_tristate(struct sys_info *sysinfo) static void sdram_set_timing_and_control(struct sys_info *sysinfo) { - u32 reg32, off32; + u32 reg32, tRD_min; u32 tWTR; u32 temp_drt; int i, page_size; - static const u8 drt0_table[] = { - /* CL 3, 4, 5 */ - 3, 4, 5, /* FSB533, DDR667/533/400 */ - 4, 5, 6, /* FSB667, DDR667/533/400 */ - 5, 6, 7, /* FSB800, DDR400/533 */ - 6, 7, 8, /* FSB800, DDR667 */ - 5, 6, 7, /* FSB1066, DDR400 */ - 7, 8, 9, /* FSB1066, DDR533/DDR667 */ - }; - static const u8 cas_table[] = { 2, 1, 0, 3 }; @@ -1787,34 +1777,15 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */ temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) ); - /* Program Write Auto Precharge to Activate */ - off32 = 0; + tRD_min = sysinfo->cas; switch (sysinfo->fsb_frequency) { - case 533: - off32 = 0; - break; - case 667: - off32 = 3; - break; - case 800: - if (sysinfo->memory_frequency <= 533) { - off32 = 6; - break; - } - off32 = 9; - break; - case 1066: - if (sysinfo->memory_frequency == 400) { - off32 = 12; - break; - } - off32 = 15; - break; + case 533: break; + case 667: tRD_min += 1; break; + case 800: tRD_min += 2; break; + case 1066: tRD_min += 3; break; } - off32 += sysinfo->cas - 3; - reg32 = drt0_table[off32]; - temp_drt |= (reg32 << 11); + temp_drt |= (tRD_min << 11); /* Read Auto Precharge to Activate */

1 0

Patch set updated for coreboot: device/dram/ddr2: Add function to select common CAS en freq
by Arthur Heymans 22 Feb '17

22 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18320 -gerrit commit 38870e4f8a07064659fc0da5104ad08d738b7eaf Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 10 12:08:16 2017 +0100 device/dram/ddr2: Add function to select common CAS en freq This function finds highest common CAS and select tCLK based on the dimm with highest minumum tCLK at that selected CAS. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/dram/ddr2.c | 57 ++++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 3 ++- 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index c2bfe0c..835546f 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -635,3 +636,59 @@ void dram_print_spd_ddr2(const dimm_attr *dimm) print_us(" tPLL : ", dimm->tPLL); print_us(" tRR : ", dimm->tRR); } + +u32 get_common_freq_cas(u8 cas_mask, const dimm_attr *dimm, int num_dimms, + u8 *selected_cas) +{ + int i, high_common_cas; + u32 tCLK = 0; + + for (i = 0; i < num_dimms; i++) { + if (dimm[i].dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + cas_mask &= dimm[i].cas_supported; + } + + if (!cas_mask) { + printk(BIOS_DEBUG, "No common supported CAS\n"); + return 0; + } + + high_common_cas = spd_get_msbs(cas_mask); + for (i = 0; i < num_dimms; i++) { + if (dimm[i].dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + if (dimm[i].cycle_time[high_common_cas] == 0) + printk(BIOS_DEBUG, "No minimum tCLK defined for dimm %d at CAS %d\n", + i, high_common_cas); + if (tCLK < dimm[i].cycle_time[high_common_cas]) + tCLK = dimm[i].cycle_time[high_common_cas]; + } + + if (tCLK == 0) { + printk(BIOS_DEBUG, "No valid minimum tCLK found\n"); + return 0; + } + + if (tCLK <= TCK_800MHZ) { + tCLK = TCK_800MHZ; + } else if (tCLK <= TCK_666MHZ) { + tCLK = TCK_666MHZ; + } else if (tCLK <= TCK_533MHZ) { + tCLK = TCK_533MHZ; + } else if (tCLK <= TCK_400MHZ) { + tCLK = TCK_400MHZ; + } else if (tCLK <= TCK_333MHZ) { + tCLK = TCK_333MHZ; + } else if (tCLK <= TCK_266MHZ) { + tCLK = TCK_266MHZ; + } else if (tCLK <= TCK_200MHZ) { + tCLK = TCK_200MHZ; + } else { + printk(BIOS_DEBUG, "Too slow common tCLK found\n"); + return 0; + } + + *selected_cas = high_common_cas; + return tCLK; +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index ae02c40..4c33b1b 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -210,6 +210,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_eeprom_size_ddr2(u8 byte1); int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); void dram_print_spd_ddr2(const dimm_attr *dimm); - +u32 get_common_freq_cas(u8 cas_mask, const dimm_attr *dimm, int num_dimms, + u8 *selected_cas); #endif /* DEVICE_DRAM_DDR2L_H */

1 0

New patch to review for coreboot: google/oak: Add initial support for Rowan
by Patrick Georgi 22 Feb '17

22 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18463 -gerrit commit 2182d144bc105a4a8265f24b9f26ccde3c899787 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Fri Feb 17 15:59:17 2017 +0800 google/oak: Add initial support for Rowan Update GPIO controls and mainboard configurations for Rowan. [pg: use the opportunity to clean-up the gerrit-rebase task list with the entirely unrelated Ignore-CL-Reviewed-on lines] BUG=chrome-os-partner:62672 BRANCH=none TEST=emerge-rowan coreboot Change-Id: I110fb368b3d9fa9dfb2bf091342dfb511ff7c09c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f4252cbe94a7456108aaa522e170bca5dcb1fdd1 Original-Change-Id: I18ebc3ccf4c7d051839d7c50e9b0682ef8f09830 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/430557 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/341513 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/327003 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/355221 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/354670 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361360 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361361 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361362 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361363 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/382320 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405110 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405130 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/419795 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/424139 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430293 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430294 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430295 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427820 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427821 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427822 --- src/mainboard/google/oak/Kconfig | 3 +++ src/mainboard/google/oak/Kconfig.name | 4 ++++ src/mainboard/google/oak/chromeos.c | 2 +- src/mainboard/google/oak/gpio.h | 5 +++-- src/mainboard/google/oak/mainboard.c | 25 ++++++++++++++++++------- 5 files changed, 29 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 01bd0bc..083ed9c 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -81,6 +81,7 @@ config MAINBOARD_PART_NUMBER default "Oak" if BOARD_GOOGLE_OAK default "Elm" if BOARD_GOOGLE_ELM default "Hana" if BOARD_GOOGLE_HANA + default "Rowan" if BOARD_GOOGLE_ROWAN config GBB_HWID string @@ -88,6 +89,7 @@ config GBB_HWID default "OAK TEST 6858" if BOARD_GOOGLE_OAK default "ELM TEST 3839" if BOARD_GOOGLE_ELM default "HANA TEST 5855" if BOARD_GOOGLE_HANA + default "ROWAN TEST 5855" if BOARD_GOOGLE_ROWAN # All Oak-derivatives count their board IDs as 0 being equivalent to Oak rev6. config BOARD_ID_ADJUSTMENT @@ -95,5 +97,6 @@ config BOARD_ID_ADJUSTMENT default 0 if BOARD_GOOGLE_OAK default 7 if BOARD_GOOGLE_ELM default 11 if BOARD_GOOGLE_HANA + default 15 if BOARD_GOOGLE_ROWAN endif # BOARD_GOOGLE_OAK diff --git a/src/mainboard/google/oak/Kconfig.name b/src/mainboard/google/oak/Kconfig.name index 95e4a3d..40a97e6 100644 --- a/src/mainboard/google/oak/Kconfig.name +++ b/src/mainboard/google/oak/Kconfig.name @@ -9,3 +9,7 @@ config BOARD_GOOGLE_ELM config BOARD_GOOGLE_HANA bool "Hana" select BOARD_GOOGLE_OAK_COMMON + +config BOARD_GOOGLE_ROWAN + bool "ROWAN" + select BOARD_GOOGLE_OAK_COMMON diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 60c24e7..fe4574e 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -26,7 +26,7 @@ void setup_chromeos_gpios(void) gpio_input(WRITE_PROTECT); gpio_input_pullup(EC_IN_RW); gpio_input_pullup(EC_IRQ); - gpio_input_pullup(LID); + gpio_input(LID); gpio_input_pullup(POWER_BUTTON); if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 5) gpio_output(EC_SUSPEND_L, 1); diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h index ba74c88..3c0f51a 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/gpio.h @@ -17,8 +17,9 @@ #define __MAINBOARD_GOOGLE_OAK_GPIO_H__ #include <soc/pinmux.h> -#define LID ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? \ - PAD_EINT12 : PAD_SPI_CK) +#define LID ((IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) ? PAD_KPROW1 \ + : ((board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) ? PAD_EINT12 \ + : PAD_SPI_CK)) enum { diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c index ad5ecd4..7cb6a68 100644 --- a/src/mainboard/google/oak/mainboard.c +++ b/src/mainboard/google/oak/mainboard.c @@ -127,11 +127,15 @@ static void configure_usb(void) setup_usb_host(); if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 3) { - /* Enable current limit */ - gpio_output(PAD_CM2MCLK, 1); - /* Configure USB OC pins*/ + /* Type C port 0 Over current alert pin */ gpio_input_pullup(PAD_MSDC3_DSL); - gpio_input_pullup(PAD_CMPCLK); + if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) { + /* Enable USB3 type A port 0 5V load switch */ + gpio_output(PAD_CM2MCLK, 1); + /* USB3 Type A port 0 power over current alert pin */ + gpio_input_pullup(PAD_CMPCLK); + } + /* Type C port 1 over current alert pin */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT < 7) gpio_input_pullup(PAD_PCM_SYNC); } @@ -148,6 +152,9 @@ static void configure_usb(void) static void configure_usb_hub(void) { + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) + return; + /* set usb hub reset pin (low active) to high */ if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 4) gpio_output(PAD_UTXD3, 1); @@ -257,9 +264,13 @@ static void mainboard_init(device_t dev) mtk_dsi_pin_drv_ctrl(); if (display_init_required()) { - configure_backlight(); - configure_display(); - display_startup(); + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) { + /* display initialization for Rowan */ + } else { + configure_backlight(); + configure_display(); + display_startup(); + } } else { printk(BIOS_INFO, "Skipping display init.\n"); }

1 0

New patch to review for coreboot: google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold
by Patrick Georgi 22 Feb '17

22 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18462 -gerrit commit 45149471af8c6e1053c273583020d0ad4322bb10 Author: William wu <wulf(a)rock-chips.com> Date: Mon Jan 23 20:54:22 2017 +0800 google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold According to USB 2.0 Spec Table 7-7, the High-speed squelch detection threshold Min 100mV and Max 150mV, and we set USB 2.0 PHY0 and PHY1 squelch detection threshold to 150mV by default, so if the amplitude of differential voltage envelope is < 150 mV, the USB 2.0 PHYs envelope detector will indicate it as squelch. On Kevin board, if we connect usb device with Samsung U2 cable, we can see that the impedance of U2 cable is too big according to the eye-diagram test report, and this cause serious signal attenuation at the end of receiver, the amplitude of differential voltage falls below 150mV. This patch aims to reduce the PHY0 and PHY1 otg-ports squelch detection threshold to 125mV (host-ports still use 150mV by default), this is helpful to increase USB 2.0 PHY compatibility. BRANCH=gru BUG=chrome-os-partner:62320 TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into Type-C port, check if the USB device can be detected. Change-Id: Ia0a2d354781c2ac757938409490f7c4eecdffe61 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7d74311c25762668386061234df0562f84b7203e Original-Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8 Original-Signed-off-by: William wu <wulf(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/431015 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Inno Park <ih.yoo.park(a)samsung.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/mainboard.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 5926e49..bb9b6fc 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -260,15 +260,20 @@ static void setup_usb(void) RK_CLRSETBITS(0xffff, 0xa7)); /* - * Disable the pre-emphasize in eop state and chirp + * 1. Disable the pre-emphasize in eop state and chirp * state to avoid mis-trigger the disconnect detection * and also avoid high-speed handshake fail for PHY0 * and PHY1 consist of otg-port and host-port. + * + * 2. Configure PHY0 and PHY1 otg-ports squelch detection + * threshold to 125mV (default is 150mV). */ - write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3)); + write32(&rk3399_grf->usbphy0_ctrl[0], + RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13)); + write32(&rk3399_grf->usbphy1_ctrl[0], + RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13)); + write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(3 << 0)); + write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(3 << 0)); /* * ODT auto compensation bypass, and set max driver

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New patch to review for coreboot: google/gru: improve eye diagram for passing the test
by Patrick Georgi 22 Feb '17

22 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18461 -gerrit commit 58b9d30d5ff971efd4be5e7c03036d8eec0b0d4c Author: Caesar Wang <wxt(a)rock-chips.com> Date: Fri Feb 10 11:16:13 2017 +0800 google/gru: improve eye diagram for passing the test The children of Gru should share the benefits. In the real world, Bob can't pass the eye diagram tests. BUG=chrome-os-partner:62714 BRANCH=firmware-gru-8785.B TEST=build coreboot Change-Id: I2470bbc81acdaf2458d660dca5dc307cc3038f83 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d0cb3e718a7571f602a00c08a42019851634e7fd Original-Change-Id: I0ccb48bb52eb770ccc9c8c265b07df46b0308dd3 Original-Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/440745 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/441468 --- src/mainboard/google/gru/mainboard.c | 92 ++++++++++++++++++------------------ 1 file changed, 45 insertions(+), 47 deletions(-) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 4dc677c..5926e49 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -253,53 +253,51 @@ static void setup_usb(void) write32(&rk3399_grf->usbphy0_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3)); write32(&rk3399_grf->usbphy1_ctrl[3], RK_CLRSETBITS(0xfff, 0x2e3)); - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) { - /* Set max pre-emphasis level, only on Kevin PHY0 and PHY1. */ - write32(&rk3399_grf->usbphy0_ctrl[12], - RK_CLRSETBITS(0xffff, 0xa7)); - write32(&rk3399_grf->usbphy1_ctrl[12], - RK_CLRSETBITS(0xffff, 0xa7)); - - /* - * Disable the pre-emphasize in eop state and chirp - * state to avoid mis-trigger the disconnect detection - * and also avoid high-speed handshake fail for PHY0 - * and PHY1 consist of otg-port and host-port. - */ - write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3)); - - /* - * ODT auto compensation bypass, and set max driver - * strength only for PHY0 and PHY1 otg-port. - */ - write32(&rk3399_grf->usbphy0_ctrl[2], - RK_CLRSETBITS(0x7e << 4, 0x60 << 4)); - write32(&rk3399_grf->usbphy1_ctrl[2], - RK_CLRSETBITS(0x7e << 4, 0x60 << 4)); - - /* - * ODT auto refresh bypass, and set the max bias current - * tuning reference only for PHY0 and PHY1 otg-port. - */ - write32(&rk3399_grf->usbphy0_ctrl[3], - RK_CLRSETBITS(0x21c, 1 << 4)); - write32(&rk3399_grf->usbphy1_ctrl[3], - RK_CLRSETBITS(0x21c, 1 << 4)); - - /* - * ODT auto compensation bypass, and set default driver - * strength only for PHY0 and PHY1 host-port. - */ - write32(&rk3399_grf->usbphy0_ctrl[15], RK_SETBITS(1 << 10)); - write32(&rk3399_grf->usbphy1_ctrl[15], RK_SETBITS(1 << 10)); - - /* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */ - write32(&rk3399_grf->usbphy0_ctrl[16], RK_CLRBITS(1 << 9)); - write32(&rk3399_grf->usbphy1_ctrl[16], RK_CLRBITS(1 << 9)); - } + /* Set max pre-emphasis level on PHY0 and PHY1. */ + write32(&rk3399_grf->usbphy0_ctrl[12], + RK_CLRSETBITS(0xffff, 0xa7)); + write32(&rk3399_grf->usbphy1_ctrl[12], + RK_CLRSETBITS(0xffff, 0xa7)); + + /* + * Disable the pre-emphasize in eop state and chirp + * state to avoid mis-trigger the disconnect detection + * and also avoid high-speed handshake fail for PHY0 + * and PHY1 consist of otg-port and host-port. + */ + write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3)); + write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3)); + write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3)); + write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3)); + + /* + * ODT auto compensation bypass, and set max driver + * strength only for PHY0 and PHY1 otg-port. + */ + write32(&rk3399_grf->usbphy0_ctrl[2], + RK_CLRSETBITS(0x7e << 4, 0x60 << 4)); + write32(&rk3399_grf->usbphy1_ctrl[2], + RK_CLRSETBITS(0x7e << 4, 0x60 << 4)); + + /* + * ODT auto refresh bypass, and set the max bias current + * tuning reference only for PHY0 and PHY1 otg-port. + */ + write32(&rk3399_grf->usbphy0_ctrl[3], + RK_CLRSETBITS(0x21c, 1 << 4)); + write32(&rk3399_grf->usbphy1_ctrl[3], + RK_CLRSETBITS(0x21c, 1 << 4)); + + /* + * ODT auto compensation bypass, and set default driver + * strength only for PHY0 and PHY1 host-port. + */ + write32(&rk3399_grf->usbphy0_ctrl[15], RK_SETBITS(1 << 10)); + write32(&rk3399_grf->usbphy1_ctrl[15], RK_SETBITS(1 << 10)); + + /* ODT auto refresh bypass only for PHY0 and PHY1 host-port. */ + write32(&rk3399_grf->usbphy0_ctrl[16], RK_CLRBITS(1 << 9)); + write32(&rk3399_grf->usbphy1_ctrl[16], RK_CLRBITS(1 << 9)); setup_usb_otg0(); setup_usb_otg1();

1 0

New patch to review for coreboot: google/gru: update the pwm regulator
by Patrick Georgi 22 Feb '17

22 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18460 -gerrit commit 2b10d8c46c7264d11f45dbc8ee53c7f5fca69fe6 Author: Caesar Wang <wxt(a)rock-chips.com> Date: Wed Jan 4 18:26:04 2017 +0800 google/gru: update the pwm regulator As David commented the "Bob and other follow-ons match Gru, Kevin should be the special case here", and update the calculations value for gru/bob board. From the actual tests, some regulator voltage than the actual set of less than 20mv on bob board. (e.g: little-cpus and Center-logic) Update the {min, max} regulator voltage for Bob board. Make sure we get the accurate voltage. BUG=chrome-os-partner:61497 BRANCH=none TEST=boot up Bob, measure the voltage for little cpu and C-logic. Change-Id: Iad881b41d67708776bfb681487cf8cec8518064e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 25e133815f49018e7496c75077b8559c207350a4 Original-Change-Id: I3098c742c7ec355c88f45bd1d93f878a7976a6b4 Original-Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao(a)asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/424523 Original-Reviewed-by: David Schneider <dnschneid(a)chromium.org> Original-Reviewed-by: Brian Norris <briannorris(a)chromium.org> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao(a)asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/430403 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/pwm_regulator.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index a81480a..426b989 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -28,29 +28,39 @@ * board design / resistors / capacitors / regulators but due to * clock dividers we actually get 3337. */ -#define PWM_PERIOD 3337 -#define PWM_DESIGN_VOLTAGE_MIN 8000 -#define PWM_DESIGN_VOLTAGE_MAX 15000 +#define PWM_PERIOD 3337 +#define PWM_DESIGN_VOLTAGE_MIN_OUTDATED 8000 +#define PWM_DESIGN_VOLTAGE_MAX_OUTDATED 15000 /* Later boards (Kevin rev6+, Gru rev2+) use different regulator ranges. */ -int pwm_design_voltage_later[][2] = { +int kevin6_pwm_design_voltage[][2] = { [PWM_REGULATOR_GPU] = {7858, 12177}, [PWM_REGULATOR_BIG] = {7987, 13022}, [PWM_REGULATOR_LIT] = {7991, 13037}, [PWM_REGULATOR_CENTERLOG] = {8001, 10497} }; +int pwm_design_voltage[][2] = { + [PWM_REGULATOR_GPU] = {7864, 12177}, + [PWM_REGULATOR_BIG] = {8001, 13022}, + [PWM_REGULATOR_LIT] = {7977, 13078}, + [PWM_REGULATOR_CENTERLOG] = {7994, 10499} +}; + void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) { int duty_ns, voltage_max, voltage_min; int voltage = millivolt * 10; /* for higer calculation accuracy */ - voltage_min = PWM_DESIGN_VOLTAGE_MIN; - voltage_max = PWM_DESIGN_VOLTAGE_MAX; - if (!(IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) && - !(IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) { - voltage_min = pwm_design_voltage_later[pwm][0]; - voltage_max = pwm_design_voltage_later[pwm][1]; + voltage_min = pwm_design_voltage[pwm][0]; + voltage_max = pwm_design_voltage[pwm][1]; + if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) || + (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) { + voltage_min = PWM_DESIGN_VOLTAGE_MIN_OUTDATED; + voltage_max = PWM_DESIGN_VOLTAGE_MAX_OUTDATED; + } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6){ + voltage_min = kevin6_pwm_design_voltage[pwm][0]; + voltage_max = kevin6_pwm_design_voltage[pwm][1]; } assert(voltage <= voltage_max && voltage >= voltage_min);

1 0

Patch set updated for coreboot: nb/i945/raminit: Use common ddr2 decode functions
by Arthur Heymans 22 Feb '17

22 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18305 -gerrit commit 006db418dbcfb1a679a42584fa7b26c748daa713 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 6 22:40:14 2017 +0100 nb/i945/raminit: Use common ddr2 decode functions This simplifies computing dram timings a lot. This removes computation of rank size based on columns, rows, banks,... and uses the information in SPD byte 31. The result of this is that dimms with multiple asymmetric ranks are not supported anymore. These however are very rare and most likely never tested on this platform. Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/raminit.c | 603 ++++++----------------------------- src/northbridge/intel/i945/raminit.h | 6 +- 2 files changed, 106 insertions(+), 503 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1f79cf6..927965d 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,6 +28,7 @@ #include "i945.h" #include "chip.h" #include <cbmem.h> +#include <device/dram/ddr2.h> /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP @@ -315,8 +316,6 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; - /** * i945 supports two DIMMs, in two configurations: * @@ -357,9 +356,11 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) * */ - for (i = 0; i<(2 * DIMM_SOCKETS); i++) { + int i, j, spd_size; + spd_raw_data raw_spd; + + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i); - u8 reg8; /* Initialize the socket information with a sane value */ sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; @@ -368,31 +369,32 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) if (!sdram_capabilities_dual_channel() && (i >> 1)) continue; - printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + spd_size = spd_decode_spd_size_ddr2(spd_read_byte(device, 0)); + + for (j = 0; j < spd_size; j++) + raw_spd[j] = spd_read_byte(device, j); - if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) { - printk(BIOS_DEBUG, "N/A\n"); + if (spd_decode_ddr2(&sysinfo->dimm_info[i], raw_spd) + != SPD_STATUS_OK) continue; - } + if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + dram_print_spd_ddr2(&sysinfo->dimm_info[i]); - reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); - if (reg8 == ERROR_SCHEME_ECC) + if (sysinfo->dimm_info[i].flags.is_ecc) die("Error: ECC memory not supported by this chipset\n"); - reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); - if (reg8 & MODULE_BUFFERED) - die("Error: Buffered memory not supported by this chipset\n"); - if (reg8 & MODULE_REGISTERED) + if (spd_dimm_is_registered_ddr2(sysinfo->dimm_info[i].dimm_type)) die("Error: Registered memory not supported by this chipset\n"); - switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) { + printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + switch (sysinfo->dimm_info[i].width) { case 0x08: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { - case 1: + switch (sysinfo->dimm_info[i].ranks) { + case 2: printk(BIOS_DEBUG, "x8DDS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; break; - case 0: + case 1: printk(BIOS_DEBUG, "x8DS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; break; @@ -401,12 +403,12 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) } break; case 0x10: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { - case 1: + switch (sysinfo->dimm_info[i].ranks) { + case 2: printk(BIOS_DEBUG, "x16DS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; break; - case 0: + case 1: printk(BIOS_DEBUG, "x16SS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; break; @@ -417,15 +419,14 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) default: die("Unsupported DDR-II memory width.\n"); } - dimm_mask |= (1 << i); } - if (!dimm_mask) { die("No memory installed.\n"); } if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { + /* Possibly does not boot in this case */ printk(BIOS_INFO, "Channel 0 has no memory populated.\n"); } } @@ -438,7 +439,6 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) static void sdram_verify_package_type(struct sys_info * sysinfo) { int i; - /* Assume no stacked DIMMs are available until we find one */ sysinfo->package = 0; for (i = 0; i < 2*DIMM_SOCKETS; i++) { @@ -446,365 +446,86 @@ static void sdram_verify_package_type(struct sys_info * sysinfo) continue; /* Is the current DIMM a stacked DIMM? */ - if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4)) + if (sysinfo->dimm_info[i].flags.stacked) sysinfo->package = 1; } } -static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) -{ - int i; - u8 cas_mask; - - /* Setup CAS mask with all supported CAS Latencies */ - cas_mask = SPD_CAS_LATENCY_DDR2_3 | - SPD_CAS_LATENCY_DDR2_4 | - SPD_CAS_LATENCY_DDR2_5; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) - cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_ACCEPTABLE_CAS_LATENCIES); - } - - if (!cas_mask) { - die("No DDR-II modules with accepted CAS latencies found.\n"); - } - - return cas_mask; -} - -static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask) +static void select_cas_dramfreq(struct sys_info * sysinfo) { - int i, j, idx; - int lowest_common_cas = 0; - int max_ram_speed = 0; - - const u8 ddr2_speeds_table[] = { - 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ - 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ - 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ - }; - - const u8 spd_lookup_table[] = { - SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, - SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, - SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD - }; + u8 selected_cas; + u8 cas_mask = SPD_CAS_LATENCY_DDR2_3 | SPD_CAS_LATENCY_DDR2_4 + | SPD_CAS_LATENCY_DDR2_5; + u32 common_tCLK, min_tCLK = TCK_200MHZ; switch (sdram_capabilities_max_supported_memory_frequency()) { - case 400: max_ram_speed = 0; break; - case 533: max_ram_speed = 1; break; - case 667: max_ram_speed = 2; break; - } - - sysinfo->memory_frequency = 0; - sysinfo->cas = 0; - - if (cas_mask & SPD_CAS_LATENCY_DDR2_3) { - lowest_common_cas = 3; - } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) { - lowest_common_cas = 4; - } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) { - lowest_common_cas = 5; + case 400: min_tCLK = TCK_200MHZ; break; + case 533: min_tCLK = TCK_266MHZ; break; + case 667: min_tCLK = TCK_333MHZ; break; } - PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas); - - for (j = max_ram_speed; j>=0; j--) { - int freq_cas_mask = cas_mask; - - PRINTK_DEBUG("Probing Speed %d\n", j); - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - int device = get_dimm_spd_address(sysinfo, i); - int current_cas_mask; - - PRINTK_DEBUG(" DIMM: %d\n", i); - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { - continue; - } - - current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES); - - while (current_cas_mask) { - int highest_supported_cas = 0, current_cas = 0; - PRINTK_DEBUG(" Current CAS mask: %04x; ", current_cas_mask); - if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - highest_supported_cas = 5; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - highest_supported_cas = 4; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - highest_supported_cas = 3; - } else { - die("Invalid max. CAS.\n"); - } - if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - current_cas = 3; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - current_cas = 4; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - current_cas = 5; - } else { - die("Invalid CAS.\n"); - } - - idx = highest_supported_cas - current_cas; - PRINTK_DEBUG("idx=%d, ", idx); - PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx])); - PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1])); - - if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && - spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { - PRINTK_DEBUG(": OK\n"); - break; - } - - PRINTK_DEBUG(": Not fast enough!\n"); - - current_cas_mask &= ~(1 << (current_cas)); - } - freq_cas_mask &= current_cas_mask; - if (!current_cas_mask) { - PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", i); - break; - } - } - PRINTK_DEBUG(" freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask); - if (freq_cas_mask) { - switch (j) { - case 0: sysinfo->memory_frequency = 400; break; - case 1: sysinfo->memory_frequency = 533; break; - case 2: sysinfo->memory_frequency = 667; break; - } - if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - sysinfo->cas = 3; - } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - sysinfo->cas = 4; - } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - sysinfo->cas = 5; - } - break; - } - } - - if (sysinfo->memory_frequency && sysinfo->cas) { - printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n", - sysinfo->memory_frequency, sysinfo->cas); - } else { + common_tCLK = get_common_freq_cas(cas_mask, sysinfo->dimm_info, + 2 * DIMM_SOCKETS, &selected_cas); + if (common_tCLK == 0) die("Could not find common memory frequency and CAS\n"); - } -} + common_tCLK = MAX(common_tCLK, min_tCLK); -static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo) -{ - int i; - int tRAS_time; - int tRAS_cycles; - int freq_multiplier = 0; + sysinfo->cas = selected_cas; + sysinfo->tclk = common_tCLK; - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ + switch (sysinfo->tclk) { + case TCK_200MHZ: sysinfo->memory_frequency = 400; break; + case TCK_266MHZ: sysinfo->memory_frequency = 533; break; + case TCK_333MHZ: sysinfo->memory_frequency = 667; break; } - - tRAS_cycles = 4; /* 4 clocks minimum */ - tRAS_time = tRAS_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - if (!reg8) { - die("Invalid tRAS value.\n"); - } - - while ((tRAS_time >> 2) < reg8) { - tRAS_time += freq_multiplier; - tRAS_cycles++; - } - } - if (tRAS_cycles > 0x18) { - die("DDR-II Module does not support this frequency (tRAS error)\n"); - } - - printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles); - sysinfo->tras = tRAS_cycles; + printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n", + sysinfo->memory_frequency, sysinfo->cas); } -static void sdram_detect_smallest_tRP(struct sys_info * sysinfo) +static void select_dram_timings(struct sys_info * sysinfo) { int i; - int tRP_time; - int tRP_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tRP_cycles = 2; /* 2 clocks minimum */ - tRP_time = tRP_cycles * freq_multiplier; + int tCLK = sysinfo->tclk; + int tRAS_cycles, tRP_cycles, tRCD_cycles, tWR_cycles, tRFC_cycles; for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME); - if (!reg8) { - die("Invalid tRP value.\n"); - } - - while (tRP_time < reg8) { - tRP_time += freq_multiplier; - tRP_cycles++; - } - } - - if (tRP_cycles > 6) { - die("DDR-II Module does not support this frequency (tRP error)\n"); - } - - printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles); - sysinfo->trp = tRP_cycles; -} - -static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo) -{ - int i; - int tRCD_time; - int tRCD_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tRCD_cycles = 2; /* 2 clocks minimum */ - tRCD_time = tRCD_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY); - if (!reg8) { - die("Invalid tRCD value.\n"); - } - - while (tRCD_time < reg8) { - tRCD_time += freq_multiplier; - tRCD_cycles++; - } - } - if (tRCD_cycles > 6) { - die("DDR-II Module does not support this frequency (tRCD error)\n"); - } - - printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles); - sysinfo->trcd = tRCD_cycles; -} - -static void sdram_detect_smallest_tWR(struct sys_info * sysinfo) -{ - int i; - int tWR_time; - int tWR_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tWR_cycles = 2; /* 2 clocks minimum */ - tWR_time = tWR_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME); - if (!reg8) { - die("Invalid tWR value.\n"); - } - - while (tWR_time < reg8) { - tWR_time += freq_multiplier; - tWR_cycles++; - } - } - if (tWR_cycles > 5) { - die("DDR-II Module does not support this frequency (tWR error)\n"); - } - - printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles); - sysinfo->twr = tWR_cycles; -} - -static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo) -{ - int i, index = 0; - - const u8 tRFC_cycles[] = { - /* 75 105 127.5 */ - 15, 21, 26, /* DDR2-400 */ - 20, 28, 34, /* DDR2-533 */ - 25, 35, 43 /* DDR2-667 */ - }; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = sysinfo->banksize[i*2]; - switch (reg8) { - case 0x04: reg8 = 0; break; - case 0x08: reg8 = 1; break; - case 0x10: reg8 = 2; break; - case 0x20: reg8 = 3; break; - } - - if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS) - reg8++; - - if (reg8 > 3) { - /* Can this happen? Go back to 127.5ns just to be sure - * we don't run out of the array. This may be wrong - */ - printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i); - reg8 = 3; - } - - if (reg8 > index) - index = reg8; - - } - index--; - switch (sysinfo->memory_frequency) { - case 667: index += 3; /* Fallthrough */ - case 533: index += 3; /* Fallthrough */ - case 400: break; - } - - sysinfo->trfc = tRFC_cycles[index]; - printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]); + tRAS_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tRAS, tCLK); + if (tRAS_cycles > 0x18) + die("DDR-II Module does not support this frequency (tRAS error)\n"); + if (tRAS_cycles > sysinfo->tras) + sysinfo->tras = tRAS_cycles; + + tRP_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tRP, tCLK); + if (tRP_cycles > 6) + die("DDR-II Module does not support this frequency (tRP error)\n"); + if (tRP_cycles > sysinfo->trp) + sysinfo->trp = tRP_cycles; + + tRCD_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tRCD, tCLK); + if (tRCD_cycles > 6) + die("DDR-II Module does not support this frequency (tRCD error)\n"); + if (tRCD_cycles > sysinfo->trcd) + sysinfo->trcd = tRCD_cycles; + + tWR_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tWR, tCLK); + if (tWR_cycles > 5) + die("DDR-II Module does not support this frequency (tWR error)\n"); + if (tWR_cycles > sysinfo->twr) + sysinfo->twr = tWR_cycles; + + tRFC_cycles = DIV_ROUND_UP(sysinfo->dimm_info[i].tRFC, tCLK); + if (tRFC_cycles > sysinfo->trfc) + sysinfo->trfc = tRFC_cycles; + + } + printk(BIOS_DEBUG, "tRAS = %d cycles\n", sysinfo->tras); + printk(BIOS_DEBUG, "tRP = %d cycles\n", sysinfo->trp); + printk(BIOS_DEBUG, "tRCD = %d cycles\n", sysinfo->trcd); + printk(BIOS_DEBUG, "tWR = %d cycles\n", sysinfo->twr); + printk(BIOS_DEBUG, "tRFC = %d cycles\n", sysinfo->trfc); } static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) @@ -819,23 +540,20 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_REFRESH) & ~(1 << 7); - - /* 15.6us */ - if (!refresh) - continue; + refresh = sysinfo->dimm_info[i].tRR; /* Refresh is slower than 15.6us, use 15.6us */ - if (refresh > 2) + /* tRR is decoded in units of 1/256us */ + if (refresh >= 15625 * 256) continue; - if (refresh == 2) { + if (refresh == 15625 * 256 / 2) { sysinfo->refresh = 1; break; } - die("DDR-II module has unsupported refresh value\n"); + if (refresh == 15625 * 256 / 4) + die("DDR-II module has unsupported refresh value\n"); } printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us"); } @@ -848,8 +566,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + if (!sysinfo->dimm_info[i].flags.bl8) die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); } } @@ -1376,121 +1093,26 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo) } } -struct dimm_size { - unsigned long side1; - unsigned long side2; -}; - -static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno) -{ - /* Calculate the log base 2 size of a DIMM in bits */ - struct dimm_size sz; - int value, low, rows, columns, device; - - device = get_dimm_spd_address(sysinfo, dimmno); - sz.side1 = 0; - sz.side2 = 0; - - rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ - if (rows < 0) goto hw_err; - if ((rows & 0xf) == 0) goto val_err; - sz.side1 += rows & 0xf; - - columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ - if (columns < 0) goto hw_err; - if ((columns & 0xf) == 0) goto val_err; - sz.side1 += columns & 0xf; - - value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */ - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side1 += log2(value & 0xff); - - /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */ - if (value < 0) goto hw_err; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */ - if (low < 0) goto hw_err; - value = value | (low & 0xff); - if ((value != 72) && (value != 64)) goto val_err; - sz.side1 += log2(value); - - /* side 2 */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */ - - if (value < 0) goto hw_err; - value &= 7; - value++; - if (value == 1) goto out; - if (value != 2) goto val_err; - - /* Start with the symmetrical case */ - sz.side2 = sz.side1; - - if ((rows & 0xf0) == 0) goto out; /* If symmetrical we are done */ - - /* Don't die here, I have not come across any of these to test what - * actually happens. - */ - printk(BIOS_ERR, "Asymmetric DIMMs are not supported by this chipset\n"); - - sz.side2 -= (rows & 0x0f); /* Subtract out rows on side 1 */ - sz.side2 += ((rows >> 4) & 0x0f); /* Add in rows on side 2 */ - - sz.side2 -= (columns & 0x0f); /* Subtract out columns on side 1 */ - sz.side2 += ((columns >> 4) & 0x0f); /* Add in columns on side 2 */ - - goto out; - - val_err: - die("Bad SPD value\n"); - hw_err: - /* If a hardware error occurs the spd ROM probably does not exist. - * In this case report that there is no memory - */ - sz.side1 = 0; - sz.side2 = 0; -out: - return sz; -} - static void sdram_detect_dimm_size(struct sys_info * sysinfo) { int i; for (i = 0; i < 2 * DIMM_SOCKETS; i++) { - struct dimm_size sz; - sysinfo->banksize[i * 2] = 0; sysinfo->banksize[(i * 2) + 1] = 0; if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - - sz = sdram_get_dimm_size(sysinfo, i); - - sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_NUM_BANKS_PER_SDRAM); /* banks */ - - if (sz.side1 < 30) + if (sysinfo->dimm_info[i].ranksize_mb < 128) die("DDR-II rank size smaller than 128MB is not supported.\n"); - sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28); - + sysinfo->banksize[i * 2] = sysinfo->dimm_info[i].ranksize_mb / 32; printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 ); - if (!sz.side2) + if (sysinfo->dimm_info[i].ranks == 1) continue; - /* If there is a second side, it has to have at least 128M, too */ - if (sz.side2 < 30) - die("DDR-II rank size smaller than 128MB is not supported.\n"); - - sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28); - + sysinfo->banksize[(i * 2) + 1] = sysinfo->dimm_info[i].ranksize_mb / 32; printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32); } } @@ -1564,25 +1186,19 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) static int sdram_set_row_attributes(struct sys_info *sysinfo) { - int i, value; + int i; u16 dra0 = 0, dra1 = 0, dra = 0; printk(BIOS_DEBUG, "Setting row attributes...\n"); for (i = 0; i < 2 * DIMM_SOCKETS; i++) { - u16 device; u8 columnsrows; if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { continue; } - device = get_dimm_spd_address(sysinfo, i); - - value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ - columnsrows = (value & 0x0f); - - value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ - columnsrows |= (value & 0xf) << 4; + columnsrows = (sysinfo->dimm_info[i].row_bits & 0x0f) + | (sysinfo->dimm_info[i].col_bits & 0xf) << 4; switch (columnsrows) { case 0x9d: dra = 2; break; @@ -1630,7 +1246,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (sysinfo->banks[i] != 8) + if (sysinfo->dimm_info[i].banks != 8) continue; printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i); @@ -3033,7 +2649,7 @@ static void sdram_setup_processor_side(void) void sdram_initialize(int boot_path, const u8 *spd_addresses) { struct sys_info sysinfo; - u8 reg8, cas_mask; + u8 reg8; printk(BIOS_DEBUG, "Setting up RAM controller.\n"); @@ -3051,20 +2667,11 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Check whether we have stacked DIMMs */ sdram_verify_package_type(&sysinfo); - /* Determine common CAS */ - cas_mask = sdram_possible_cas_latencies(&sysinfo); + /* Select common CAS latency and dram frequency */ + select_cas_dramfreq(&sysinfo); - /* Choose Common Frequency */ - sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask); - - /* Determine smallest common tRAS */ - sdram_detect_smallest_tRAS(&sysinfo); - - /* Determine tRP */ - sdram_detect_smallest_tRP(&sysinfo); - - /* Determine tRCD */ - sdram_detect_smallest_tRCD(&sysinfo); + /* Select nRAS, nRP, nRCD, nWR, tRFC */ + select_dram_timings(&sysinfo); /* Determine smallest refresh period */ sdram_detect_smallest_refresh(&sysinfo); @@ -3072,15 +2679,9 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Verify all DIMMs support burst length 8 */ sdram_verify_burst_length(&sysinfo); - /* determine tWR */ - sdram_detect_smallest_tWR(&sysinfo); - /* Determine DIMM size parameters (rows, columns banks) */ sdram_detect_dimm_size(&sysinfo); - /* determine tRFC */ - sdram_detect_smallest_tRFC(&sysinfo); - /* Program PLL settings */ sdram_program_pll_settings(&sysinfo); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 0554900..e8e5140 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -23,9 +23,12 @@ /* Burst length is always 8 */ #define BURSTLENGTH 8 +#include <device/dram/ddr2.h> + struct sys_info { u16 memory_frequency; /* 400, 533 or 667 */ u16 fsb_frequency; /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */ + u32 tclk; u8 trp; /* calculated by sdram_detect_smallest_tRP() */ u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */ @@ -50,14 +53,13 @@ struct sys_info { #define SYSINFO_PACKAGE_PLANAR 0x00 #define SYSINFO_PACKAGE_STACKED 0x01 u8 dimm[2 * DIMM_SOCKETS]; + dimm_attr dimm_info[2 * DIMM_SOCKETS]; #define SYSINFO_DIMM_X16DS 0x00 #define SYSINFO_DIMM_X8DS 0x01 #define SYSINFO_DIMM_X16SS 0x02 #define SYSINFO_DIMM_X8DDS 0x03 #define SYSINFO_DIMM_NOT_POPULATED 0x04 - u8 banks[2 * DIMM_SOCKETS]; - u8 banksize[2 * 2 * DIMM_SOCKETS]; const u8 *spd_addresses;

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Patch set updated for coreboot: nb/intel/i945/raminit.c: Refactor tRD selection
by Arthur Heymans 22 Feb '17

22 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18354 -gerrit commit 121fcfaf82d6e876bd6eccef6d3da97c45c91903 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Feb 12 23:34:39 2017 +0100 nb/intel/i945/raminit.c: Refactor tRD selection Inspired by gm45 code, which sets this value the same way. Some values for tRD on 800 and 1067MHz FSB were set wrong because the CAS/Freq selection was wrong. PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5 Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/raminit.c | 43 ++++++------------------------------ 1 file changed, 7 insertions(+), 36 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cc227cc..1f79cf6 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1720,21 +1720,11 @@ static void sdram_program_odt_tristate(struct sys_info *sysinfo) static void sdram_set_timing_and_control(struct sys_info *sysinfo) { - u32 reg32, off32; + u32 reg32, tRD_min; u32 tWTR; u32 temp_drt; int i, page_size; - static const u8 drt0_table[] = { - /* CL 3, 4, 5 */ - 3, 4, 5, /* FSB533, DDR667/533/400 */ - 4, 5, 6, /* FSB667, DDR667/533/400 */ - 5, 6, 7, /* FSB800, DDR400/533 */ - 6, 7, 8, /* FSB800, DDR667 */ - 5, 6, 7, /* FSB1066, DDR400 */ - 7, 8, 9, /* FSB1066, DDR533/DDR667 */ - }; - static const u8 cas_table[] = { 2, 1, 0, 3 }; @@ -1787,34 +1777,15 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */ temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) ); - /* Program Write Auto Precharge to Activate */ - off32 = 0; + tRD_min = sysinfo->cas; switch (sysinfo->fsb_frequency) { - case 533: - off32 = 0; - break; - case 667: - off32 = 3; - break; - case 800: - if (sysinfo->memory_frequency <= 533) { - off32 = 6; - break; - } - off32 = 9; - break; - case 1066: - if (sysinfo->memory_frequency == 400) { - off32 = 12; - break; - } - off32 = 15; - break; + case 533: break; + case 667: tRD_min += 1; break; + case 800: tRD_min += 2; break; + case 1066: tRD_min += 3; break; } - off32 += sysinfo->cas - 3; - reg32 = drt0_table[off32]; - temp_drt |= (reg32 << 11); + temp_drt |= (tRD_min << 11); /* Read Auto Precharge to Activate */

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Patch set updated for coreboot: device/dram/ddr2: Add common function to select common CAS en freq
by Arthur Heymans 22 Feb '17

22 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18320 -gerrit commit 04c1d6b8e1cac7982ef1fdf1596ab88571ce99f3 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 10 12:08:16 2017 +0100 device/dram/ddr2: Add common function to select common CAS en freq This function finds highest common CAS and select tCLK based on the dimm with highest minumum tCLK at that selected CAS. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/dram/ddr2.c | 57 ++++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 3 ++- 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index c2bfe0c..1ae788d 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -635,3 +636,59 @@ void dram_print_spd_ddr2(const dimm_attr *dimm) print_us(" tPLL : ", dimm->tPLL); print_us(" tRR : ", dimm->tRR); } + +u32 get_common_freq_cas(u8 cas_mask, const dimm_attr *dimm, int num_dimms, + u8 *selected_cas) +{ + int i, high_common_cas; + u32 tCLK = 0; + + for (i = 0; i < num_dimms; i++) { + if (dimm[i].dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + cas_mask &= dimm[i].cas_supported; + } + + if (!cas_mask) { + printk(BIOS_DEBUG, "No common supported CAS\n"); + return 0; + } + + high_common_cas = spd_get_msbs(cas_mask); + for (i = 0; i < num_dimms; i++) { + if (dimm[i].dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + if (dimm[i].cycle_time[high_common_cas] == 0) + printk(BIOS_DEBUG, "No minimum tCLK defined for dimm %d at CAS %d\n", + i, high_common_cas); + if (tCLK < dimm[i].cycle_time[high_common_cas]) + tCLK = dimm[i].cycle_time[high_common_cas]; + } + + if (tCLK == 0) { + printk(BIOS_DEBUG, "No valid minimum tCLK found\n"); + return 0; + } + + if (tCLK <= TCK_800MHZ) { + tCLK = TCK_800MHZ; + } else if (tCLK <= TCK_666MHZ) { + tCLK = TCK_666MHZ; + } else if (tCLK <= TCK_533MHZ) { + tCLK = TCK_533MHZ; + } else if (tCLK <= TCK_400MHZ) { + tCLK = TCK_400MHZ; + } else if (tCLK <= TCK_333MHZ) { + tCLK = TCK_333MHZ; + } else if (tCLK <= TCK_266MHZ) { + tCLK = TCK_266MHZ; + } else if (tCLK <= TCK_200MHZ) { + tCLK = TCK_200MHZ; + } else { + prink(BIOS_DEBUG, "Too slow common tCLK found\n"); + return 0; + } + + *selected_cas = high_common_cas; + return tCLK; +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index ae02c40..4c33b1b 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -210,6 +210,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_eeprom_size_ddr2(u8 byte1); int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); void dram_print_spd_ddr2(const dimm_attr *dimm); - +u32 get_common_freq_cas(u8 cas_mask, const dimm_attr *dimm, int num_dimms, + u8 *selected_cas); #endif /* DEVICE_DRAM_DDR2L_H */

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coreboot-gerrit February 2017