coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: nehalem/Kconfig: Rename TRAINING_CACHE_SIZE to MRC_CACHE_SIZE
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit b29e0b70f856f699d60c219eedf4d9b4146154cb Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Jan 22 21:24:40 2017 +0100 nehalem/Kconfig: Rename TRAINING_CACHE_SIZE to MRC_CACHE_SIZE This is more consistent with newer Intel targets. Change-Id: I52ee8d3f0c330a03bd6c18eed08e578dd6ae284b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18371 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> See https://review.coreboot.org/18371 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/nehalem: Clean nehalem.h
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit bd9548ba7ce670bd53013f089706bcfc91c95c77 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Jan 22 21:17:09 2017 +0100 nb/intel/nehalem: Clean nehalem.h Remove unused definitions, prototypes and macros moslty copied from gm45. Change-Id: I076e204885baec3d40f165785cf4ae4adc9154c5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18370 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18370 for details. -gerrit

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Patch merged into coreboot/master: purism/librem13: Set system type to laptop
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit c61a52a94066ba842ffd8eecad350054f75c4ee2 Author: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> Date: Wed Feb 15 13:18:47 2017 -0500 purism/librem13: Set system type to laptop Change-Id: I3ae80f5727e83a1c9210f0d13fa7fc32c5c79085 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Reviewed-on: https://review.coreboot.org/18412 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18412 for details. -gerrit

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Patch merged into coreboot/master: purism/librem13: Fix HDA codec verbs. Use correct codec vendor id
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 02756b8ffb96bc84c1a60db6d0b8d77d111e3956 Author: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> Date: Wed Feb 15 12:52:50 2017 -0500 purism/librem13: Fix HDA codec verbs. Use correct codec vendor id There was a 'typo' where the subsystem id was set instead of the codec vendor id. This caused the lynxpoint HDA codecs init to fail to find the proper codecid verbs so codecs were never initialized. That caused the headphones jack to not work. Change-Id: I975031643fc42937ecaea2300639b90632543f67 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Reviewed-on: https://review.coreboot.org/18411 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18411 for details. -gerrit

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Patch merged into coreboot/master: purism/librem13: Enable PCIe ports 1 and 2
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 20ec37b80cc6fcc8b38939bad54f26bf3bdd2fea Author: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> Date: Tue Feb 7 14:01:01 2017 -0500 purism/librem13: Enable PCIe ports 1 and 2 Change-Id: I1fa72e59866ee4aad34d4b60e499f6e37acc367f Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Reviewed-on: https://review.coreboot.org/18410 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/18410 for details. -gerrit

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Patch set updated for coreboot: mainboard/google/poppy: Change toucschreen IRQ to level-triggered
by Furquan Shaikh 22 Feb '17

22 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18466 -gerrit commit d8cc094a2ef9bb3fb0f3d4a63fe8cd6e6a5808ff Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Feb 21 15:52:57 2017 -0800 mainboard/google/poppy: Change toucschreen IRQ to level-triggered BUG=chrome-os-partner:62967 BRANCH=None TEST=Verified that touchscreen works on power-on and after suspend-resume as well. Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/poppy/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 07cacc0..2e60216 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -201,7 +201,7 @@ chip soc/intel/skylake chip drivers/i2c/generic register "hid" = ""ATML0001"" register "desc" = ""Atmel Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "probed" = "1" device i2c 4b on end end

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Patch merged into coreboot/master: purism/librem13: Fix M.2 issues.
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit a462c157f8a98e9e115e84a2d9d142c9b878210e Author: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> Date: Tue Feb 7 13:59:29 2017 -0500 purism/librem13: Fix M.2 issues. The M.2 SSD is on the SATA port 3, which also required the DTLE setting to be set. This fixes issues with the M.2 SSD not being detected/stable. Change-Id: Id39d9ec395a2d9d32be4c079678d0708f08b3935 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Reviewed-on: https://review.coreboot.org/18409 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/18409 for details. -gerrit

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Patch merged into coreboot/master: Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 696ebc2dbc64c3a76b45080cebf9949db00348e2 Author: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> Date: Tue Feb 7 13:54:45 2017 -0500 Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3. The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but Browell supports up to 4 ports, so we need to support setting IOBP for ports 2 and 3 as well. The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only guessed by looking at ports 0 and 1 and extrapolating from there. Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work so we can assume that port 2 and 3 magic numbers are valid, but having someone confirm them (through non-public documents?) would be great. Change-Id: I59911cfa677749ceea9a544a99b444722392e72d Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Reviewed-on: https://review.coreboot.org/18408 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/18408 for details. -gerrit

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New patch to review for coreboot: mainboard/google/poppy: Change toucschreen IRQ to level-triggered
by Furquan Shaikh 22 Feb '17

22 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18466 -gerrit commit 93b407e7221c70df0fe5c12008f854553bafb739 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Feb 21 15:52:57 2017 -0800 mainboard/google/poppy: Change toucschreen IRQ to level-triggered BUG=chrome-os-partner:62967 BRANCH=None TEST=Verified that touchscreen works on power-on and after suspend-resume as well. Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85 --- src/mainboard/google/poppy/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 07cacc0..2e60216 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -201,7 +201,7 @@ chip soc/intel/skylake chip drivers/i2c/generic register "hid" = ""ATML0001"" register "desc" = ""Atmel Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "probed" = "1" device i2c 4b on end end

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Patch merged into coreboot/master: src/mainboard/digitallogic: Add license headers to all files
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit c0ebe4a751e264f0cca6f5fbbd17e51285f9ac56 Author: Martin Roth <martinroth(a)google.com> Date: Thu Feb 9 18:05:08 2017 -0800 src/mainboard/digitallogic: Add license headers to all files Change-Id: I6a1810360b5c3210038670aea6e80312798a63cd Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/18406 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> See https://review.coreboot.org/18406 for details. -gerrit

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coreboot-gerrit February 2017