coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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1019 discussions

Patch merged into coreboot/master: src/cpu/x86: Update/Add license headers to all files
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 6add44bd3c462ed25828657cbb329b996aa91c51 Author: Martin Roth <martinroth(a)google.com> Date: Thu Feb 9 17:51:20 2017 -0800 src/cpu/x86: Update/Add license headers to all files Change-Id: I436bf0e7db008ea78e29eaeef10bea101e6c8922 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/18405 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> See https://review.coreboot.org/18405 for details. -gerrit

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Patch merged into coreboot/master: src/cpu/intel: Add license headers to all files
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 996cf797e13c7e192f7b4c8ed6834443206f1f97 Author: Martin Roth <martinroth(a)google.com> Date: Thu Feb 9 17:26:06 2017 -0800 src/cpu/intel: Add license headers to all files Change-Id: I5ba8b186972fb59686dcbe11358cd26408cbaf05 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/18404 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> See https://review.coreboot.org/18404 for details. -gerrit

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Patch merged into coreboot/master: src/cpu/amd: Update/Add license headers to all files
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 869532264a20801a58ccfb4bbca1b52d015a959f Author: Martin Roth <martinroth(a)google.com> Date: Thu Feb 9 17:23:55 2017 -0800 src/cpu/amd: Update/Add license headers to all files Change-Id: I1e0b2b9086db6b3c2f716d9400a83eb60b2ce222 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/18403 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> See https://review.coreboot.org/18403 for details. -gerrit

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Patch merged into coreboot/master: arch/x86/acpigen: Provide helper functions for enabling/disabling GPIO
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit bf4845dd3acf3ce9e9c63ce8c35ee7111351aa78 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Feb 20 22:56:25 2017 -0800 arch/x86/acpigen: Provide helper functions for enabling/disabling GPIO In order to allow GPIOs to be set/clear according to their polarity, provide helper functions that check for polarity and call set/clear SoC functions for generating ACPI code. BUG=None BRANCH=None TEST=Verified that the ACPI code generated remains the same as before for reef. Change-Id: Ie8bdb9dc18e61a4a658f1447d6f1db0b166d9c12 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/18427 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18427 for details. -gerrit

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Patch merged into coreboot/master: acpi: Add ACPI_ prefix to IRQ enum and struct names
by gerrit＠coreboot.org 22 Feb '17

22 Feb '17

the following patch was just integrated into master: commit 5b9b593f2f888c81cc0af8eb2fc2173c83562003 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Feb 21 13:16:30 2017 -0800 acpi: Add ACPI_ prefix to IRQ enum and struct names This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18444 for details. -gerrit

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Patch set updated for coreboot: mainboard/lenovo: Power off USB and mute audio before entering S3
by Nicola Corna 22 Feb '17

22 Feb '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18464 -gerrit commit 2685fea1f23bed0b1bfc2649ad8a8cf3579c464d Author: Nicola Corna <nicola(a)corna.info> Date: Wed Feb 22 16:52:29 2017 +0100 mainboard/lenovo: Power off USB and mute audio before entering S3 Currently, the USB ports are still powered during S3, so turning them off may reduce the power consumption. Note that, when the USB Always on feature is enabled, the USB ports are always powered, regardless of the USBP state. This patch also disables the audio, as it might consume some power or generate some noise. Both the USB power and the audio are reenabled by coreboot during the poweron. Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/mainboard/lenovo/l520/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t400/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t420/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t420s/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t430s/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t520/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t530/acpi/platform.asl | 2 ++ src/mainboard/lenovo/x200/acpi/platform.asl | 2 ++ src/mainboard/lenovo/x220/acpi/platform.asl | 2 ++ src/mainboard/lenovo/x230/acpi/platform.asl | 2 ++ 10 files changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl index 432ed23..c7aea62 100644 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -24,5 +24,7 @@ Method(_WAK,1) Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t400/acpi/platform.asl b/src/mainboard/lenovo/t400/acpi/platform.asl index f60752c..5c6f968 100644 --- a/src/mainboard/lenovo/t400/acpi/platform.asl +++ b/src/mainboard/lenovo/t400/acpi/platform.asl @@ -22,6 +22,8 @@ Method(_PTS,1) { // Call a trap so SMI can prepare for Sleep as well. // TRAP(0x55) + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl index 2ba5b20..6f26c5a 100644 --- a/src/mainboard/lenovo/t420/acpi/platform.asl +++ b/src/mainboard/lenovo/t420/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl index 2ba5b20..6f26c5a 100644 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ b/src/mainboard/lenovo/t420s/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl index 2ba5b20..6f26c5a 100644 --- a/src/mainboard/lenovo/t430s/acpi/platform.asl +++ b/src/mainboard/lenovo/t430s/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl index 2ba5b20..6f26c5a 100644 --- a/src/mainboard/lenovo/t520/acpi/platform.asl +++ b/src/mainboard/lenovo/t520/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl index 3e9225c..9cd327a 100644 --- a/src/mainboard/lenovo/t530/acpi/platform.asl +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index f60752c..5c6f968 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -22,6 +22,8 @@ Method(_PTS,1) { // Call a trap so SMI can prepare for Sleep as well. // TRAP(0x55) + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index 3e9225c..9cd327a 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl index 3e9225c..9cd327a 100644 --- a/src/mainboard/lenovo/x230/acpi/platform.asl +++ b/src/mainboard/lenovo/x230/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) }

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Patch set updated for coreboot: mb/google/poppy: Enable support for DPTF
by Sumeet R Pawnikar 22 Feb '17

22 Feb '17

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17926 -gerrit commit 3b59b2bbfd0d55d874970be9708fb71e2ac3cdb2 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Feb 20 10:34:01 2017 +0530 mb/google/poppy: Enable support for DPTF This patch adds the DPTF settings specfic to the mainboard and enables the CPU and other thermal sensors as participant device for poppy. It enables the DPTF flag in the device tree for poppy. It also includes the DPTF specific ASL file in the main DSDT definition. BUG=None BRANCH=None TEST=Built for poppy. Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/mainboard/google/poppy/acpi/dptf.asl | 83 ++++++++++++++++++++++++++++++++ src/mainboard/google/poppy/devicetree.cb | 4 ++ src/mainboard/google/poppy/dsdt.asl | 6 +++ 3 files changed, 93 insertions(+) diff --git a/src/mainboard/google/poppy/acpi/dptf.asl b/src/mainboard/google/poppy/acpi/dptf.asl new file mode 100644 index 0000000..7f6cd8e --- /dev/null +++ b/src/mainboard/google/poppy/acpi/dptf.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 94 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Ambient" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Charger" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "DRAM" +#define DPTF_TSR2_PASSIVE 52 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 4500, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 3000, /* PowerLimitMinimum */ + 7000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index b3b7623..3beea63 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -19,6 +19,9 @@ chip soc/intel/skylake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Enable DPTF + register "dptf_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" @@ -184,6 +187,7 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tdp_pl2_override" = "7" + register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_G7" diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index c678dfc..2007691 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -61,4 +61,10 @@ DefinitionBlock( /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + Scope (\_SB) + { + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } }

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New patch to review for coreboot: intel/i945: Fix up whitespace and indentation
by Paul Menzel 22 Feb '17

22 Feb '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18465 -gerrit commit 2adc1a61740ac13aaeb3ca662876fd692e7ce2f4 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Wed Feb 22 18:46:27 2017 +0100 intel/i945: Fix up whitespace and indentation Fix up the whitespace issues introduced in commit 39bfc6cb (nb/i945/raminit.c: Fix dll timings on 945GC). Change-Id: I3a4152866226401bc51c7fb1752aab541a4c72b0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/i945/raminit.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 8fe5f24..a8bb5e7 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1238,15 +1238,15 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) /* We drive both channels with the same speed */ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ + case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ + case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ + case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ } } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ - case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ - case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ + case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ + case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ + case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ } } @@ -1258,7 +1258,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = chan0dll & 0xff; MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = chan1dll & 0xff; - } + } } }

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Patch set updated for coreboot: mb/google/poppy: Enable dptf
by Sumeet R Pawnikar 22 Feb '17

22 Feb '17

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17926 -gerrit commit 0af0083195443404a53e55ee8ee833e13f450ed9 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Mon Feb 20 10:34:01 2017 +0530 mb/google/poppy: Enable dptf This patch adds DPTF participants for poppy. BUG=None BRANCH=None TEST=Built for poppy. Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- src/mainboard/google/poppy/acpi/dptf.asl | 83 ++++++++++++++++++++++++++++++++ src/mainboard/google/poppy/devicetree.cb | 4 ++ src/mainboard/google/poppy/dsdt.asl | 7 +++ 3 files changed, 94 insertions(+) diff --git a/src/mainboard/google/poppy/acpi/dptf.asl b/src/mainboard/google/poppy/acpi/dptf.asl new file mode 100644 index 0000000..7f6cd8e --- /dev/null +++ b/src/mainboard/google/poppy/acpi/dptf.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 94 +#define DPTF_CPU_CRITICAL 99 + +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "Ambient" +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "Charger" +#define DPTF_TSR1_PASSIVE 55 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "DRAM" +#define DPTF_TSR2_PASSIVE 52 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 4500, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 3000, /* PowerLimitMinimum */ + 7000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index b3b7623..3beea63 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -19,6 +19,9 @@ chip soc/intel/skylake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Enable DPTF + register "dptf_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" @@ -184,6 +187,7 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "tdp_pl2_override" = "7" + register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_G7" diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index c678dfc..3acd348 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -61,4 +61,11 @@ DefinitionBlock( /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + + Scope (\_SB) + { + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + }

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New patch to review for coreboot: mainboard/lenovo: Power off USB and mute audio before entering S3
by Nicola Corna 22 Feb '17

22 Feb '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18464 -gerrit commit a8c4f61a71fc3a327cd7a9e9944174f6c6d7c3cc Author: Nicola Corna <nicola(a)corna.info> Date: Wed Feb 22 16:52:29 2017 +0100 mainboard/lenovo: Power off USB and mute audio before entering S3 The USB ports were still powered during S3, possibly leading to a higher power consumption. Note that, when the USB Always on feature is enabled, the USB ports are always powered, regardless of the USBP state. The audio has been disabled as well, as it might consume some power or generate some noise. Both the USB power and the audio are reenabled by coreboot during the poweron. Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/mainboard/lenovo/l520/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t400/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t420/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t420s/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t430s/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t520/acpi/platform.asl | 2 ++ src/mainboard/lenovo/t530/acpi/platform.asl | 2 ++ src/mainboard/lenovo/x200/acpi/platform.asl | 2 ++ src/mainboard/lenovo/x220/acpi/platform.asl | 2 ++ src/mainboard/lenovo/x230/acpi/platform.asl | 2 ++ 10 files changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl index 432ed23..c7aea62 100644 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -24,5 +24,7 @@ Method(_WAK,1) Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t400/acpi/platform.asl b/src/mainboard/lenovo/t400/acpi/platform.asl index f60752c..5c6f968 100644 --- a/src/mainboard/lenovo/t400/acpi/platform.asl +++ b/src/mainboard/lenovo/t400/acpi/platform.asl @@ -22,6 +22,8 @@ Method(_PTS,1) { // Call a trap so SMI can prepare for Sleep as well. // TRAP(0x55) + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t420/acpi/platform.asl b/src/mainboard/lenovo/t420/acpi/platform.asl index 2ba5b20..6f26c5a 100644 --- a/src/mainboard/lenovo/t420/acpi/platform.asl +++ b/src/mainboard/lenovo/t420/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl index 2ba5b20..6f26c5a 100644 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ b/src/mainboard/lenovo/t420s/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl index 2ba5b20..6f26c5a 100644 --- a/src/mainboard/lenovo/t430s/acpi/platform.asl +++ b/src/mainboard/lenovo/t430s/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl index 2ba5b20..6f26c5a 100644 --- a/src/mainboard/lenovo/t520/acpi/platform.asl +++ b/src/mainboard/lenovo/t520/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl index 3e9225c..9cd327a 100644 --- a/src/mainboard/lenovo/t530/acpi/platform.asl +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index f60752c..5c6f968 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -22,6 +22,8 @@ Method(_PTS,1) { // Call a trap so SMI can prepare for Sleep as well. // TRAP(0x55) + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index 3e9225c..9cd327a 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) } diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl index 3e9225c..9cd327a 100644 --- a/src/mainboard/lenovo/x230/acpi/platform.asl +++ b/src/mainboard/lenovo/x230/acpi/platform.asl @@ -19,6 +19,8 @@ Method(_PTS,1) { + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) \_SB.PCI0.LPCB.EC.RADI(0) }

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coreboot-gerrit February 2017