coreboot-gerrit February 2017

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Patch set updated for coreboot: soc/intel/glk: Add Kconfig and Makefile.inc for GLK SoC[WIP]
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18449 -gerrit commit f5abe446c3428765cee64d57577f11b4a9551fe6 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 15:01:26 2017 +0530 soc/intel/glk: Add Kconfig and Makefile.inc for GLK SoC[WIP] Copied from APL latest git. Change-Id: Icf1bb95cd2503e12f8ce26d77d2cd940a2ea1b69 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Kconfig | 254 +++++++++++++++++++++++++++++++++++++++++ src/soc/intel/glk/Makefile.inc | 42 +++++++ 2 files changed, 296 insertions(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig new file mode 100644 index 0000000..c882e58 --- /dev/null +++ b/src/soc/intel/glk/Kconfig @@ -0,0 +1,254 @@ +config SOC_INTEL_GLK + bool + help + Intel GLK support + +if SOC_INTEL_GLK + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOTBLOCK_CONSOLE + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + # CPU specific options + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select IOAPIC + select SMP + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + # Audio options + select ACPI_NHLT + select SOC_INTEL_COMMON_NHLT + # Misc options + select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE + select COLLECT_TIMESTAMPS + select COMMON_FADT + select GENERIC_GPIO_LIB + select HAVE_INTEL_FIRMWARE + select HAVE_SMI_HANDLER + select MRC_SETTINGS_PROTECT + select NO_FIXED_XIP_ROM_SIZE + select NO_XIP_EARLY_STAGES + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE + select POSTCAR_CONSOLE + select POSTCAR_STAGE + select REG_SCRIPT + select RELOCATABLE_RAMSTAGE # Build fails if this is not selected + select RTC + select SMM_TSEG + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_LPSS_I2C + select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select UDELAY_TSC + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select HAVE_MONOTONIC_TIMER + select PLATFORM_USES_FSP2_0 + select HAVE_HARD_RESET + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_GFX_OPREGION + select ADD_VBT_DATA_FILE + +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC + select SEPARATE_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + select VIRTUAL_DEV_SWITCH + +config TPM_ON_FAST_SPI + bool + default n + select LPC_TPM + help + TPM part is conntected on Fast SPI interface, but the LPC MMIO + TPM transactions are decoded and serialized over the SPI interface. + +config SOC_INTEL_COMMON_RESET + bool + default y + +config MMCONF_BASE_ADDRESS + hex "PCI MMIO Base Address" + default 0xe0000000 + +config IOSF_BASE_ADDRESS + hex "MMIO Base Address of sideband bus" + default 0xd0000000 + +config DCACHE_RAM_BASE + hex "Base address of cache-as-RAM" + default 0xfef00000 + +config DCACHE_RAM_SIZE + hex "Length in bytes of cache-as-RAM" + default 0xc0000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config CPU_ADDR_BITS + int + default 36 + +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + depends on SOC_INTEL_COMMON_LPSS_I2C + int + default 133 + +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL + hex "MMIO base address for UART" + default 0xde000000 + +config SOC_UART_DEBUG + bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." + default n + select CONSOLE_SERIAL + select DRIVERS_UART + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + +# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + +# This SoC does not map SPI flash like many previous SoC. Therefore we provide +# a custom media driver that facilitates mapping +config X86_TOP4G_BOOTMEDIA_MAP + bool + default n + +config ROMSTAGE_ADDR + hex + default 0xfef20000 + help + The base address (in CAR) where romstage should be linked + +config VERSTAGE_ADDR + hex + default 0xfef40000 + help + The base address (in CAR) where verstage should be linked + +config CACHE_MRC_SETTINGS + bool + default y + +config MRC_SETTINGS_VARIABLE_DATA + bool + default y + +config FSP_M_ADDR + hex + default 0xfef40000 + help + The address FSP-M will be relocated to during build time + +config NEED_LBP2 + bool "Write contents for logical boot partition 2." + default n + help + Write the contents from a file into the logical boot partition 2 + region defined by LBP2_FMAP_NAME. + +config LBP2_FMAP_NAME + string "Name of FMAP region to put logical boot partition 2" + depends on NEED_LBP2 + default "SIGN_CSE" + help + Name of FMAP region to write logical boot partition 2 data. + +config LBP2_FILE_NAME + string "Path of file to write to logical boot partition 2 region" + depends on NEED_LBP2 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin" + help + Name of file to store in the logical boot partition 2 region. + +config NEED_IFWI + bool "Write content into IFWI region" + default n + help + Write the content from a file into IFWI region defined by + IFWI_FMAP_NAME. + +config IFWI_FMAP_NAME + string "Name of FMAP region to pull IFWI into" + depends on NEED_IFWI + default "IFWI" + help + Name of FMAP region to write IFWI. + +config IFWI_FILE_NAME + string "Path of file to write to IFWI region" + depends on NEED_IFWI + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" + help + Name of file to store in the IFWI region. + +config HEAP_SIZE + hex + default 0x8000 + +choice + prompt "Cache-as-ram implementation" + default CAR_CQOS + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config CAR_NEM + bool "Non-evict mode" + help + Traditionally, CAR is set up by using Non-Evict mode. This method + does not allow CAR and cache to co-exist, because cache fills are + block in NEM mode. + +config CAR_CQOS + bool "Cache Quality of Service" + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up portion of L2 cache for + CAR and use remainder for actual caching. + +endchoice + +config SPI_FLASH_INCLUDE_ALL_DRIVERS + bool + default n + +config SMM_RESERVED_SIZE + hex + default 0x100000 + +config IFD_CHIPSET + string + default "aplk" + +endif diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc new file mode 100644 index 0000000..b2a430a --- /dev/null +++ b/src/soc/intel/glk/Makefile.inc @@ -0,0 +1,42 @@ +ifeq ($(CONFIG_SOC_INTEL_GLK),y) + +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache +subdirs-y += ../common/basecode +subdirs-y += ../common/block/* + +CPPFLAGS_common += -I$(src)/soc/intel/glk/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk + +# Since FSP-M runs in CAR we need to relocate it to a specific address +$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) + +ifeq ($(CONFIG_NEED_LBP2),y) +files_added:: + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward +endif + +# Bootblock on GLK platform lies in the IFWI region. In order to place +# the bootblock at the right location in IFWI image - +# a. Using ifwitool: +# 1. Create IFWI image (ifwi.bin.tmp) from input image +# (CONFIG_IFWI_FILE_NAME). +# 2. Delete OBBP sub-partition, if present. +# 3. Replace IBBL directory entry in IBBP sub-partition with currently +# generated bootblock.bin. +# b. Using cbfstool: +# 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME. +ifeq ($(CONFIG_NEED_IFWI),y) +files_added:: $(IFWITOOL) + $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp + $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP + $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward +endif + +endif

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Patch set updated for coreboot: soc/intel/common: Include common block directory [WIP]
by Subrata Banik 23 Feb '17

23 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18378 -gerrit commit b37288fe7fa99ad4019338f477b963c2ffbfe565 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Thu Feb 16 16:15:14 2017 +0530 soc/intel/common: Include common block directory [WIP] Change-Id: Id6561033fc77c64c61ab0341337523e14f55dd80 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/common/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index d6e1e75..cf11ec2 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,5 +1,8 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +subdirs-y += ../common/basecode +subdirs-y += ../common/block/* + bootblock-y += util.c verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c

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New patch to review for coreboot: src/include: Include stdint.h sicne struct dimm_info uses it
by Barnali Sarkar 23 Feb '17

23 Feb '17

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18471 -gerrit commit bf814729024a62fb9a09529ae3c9a8c57ded4cc4 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Thu Feb 23 16:56:54 2017 +0530 src/include: Include stdint.h sicne struct dimm_info uses it struct dimm_info has all the parameter types defined in stdint.h file. So including it. BUG=none BRANCH=none TEST=Build and boot KBLRVP Change-Id: I707523749ecf415e993b460f9613eae7be859c34 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/include/memory_info.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 4613628..02904af 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -16,6 +16,8 @@ #ifndef _MEMORY_INFO_H_ #define _MEMORY_INFO_H_ +#include <stdint.h> + /* * If this table is filled and put in CBMEM, * then these info in CBMEM will be used to generate smbios type 17 table

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Patch set updated for coreboot: soc/intel/apollolake: Extract DIMM Information from FSP MEM INFO HOB
by Barnali Sarkar 23 Feb '17

23 Feb '17

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18451 -gerrit commit 6f2c0b2425da822469d5ffa681fb3398f23650ed Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Tue Feb 21 17:48:53 2017 +0530 soc/intel/apollolake: Extract DIMM Information from FSP MEM INFO HOB Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and save it in CBMEM. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot Reef to verify the type 17 DIMM info coming in SMBIOS table from Kernel command "dmidecode". Change-Id: I33c3a0bebf33c53beadd745bc3d991e1e51050b7 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/apollolake/meminit.c | 39 +++++++++----------------------------- 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 0f553ee..a4cdf40 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -16,7 +16,7 @@ #include <console/console.h> #include <fsp/util.h> #include <memory_info.h> -#include <smbios.h> +#include <soc/intel/common/smbios.h> #include <soc/meminit.h> #include <stddef.h> /* required for FspmUpd.h */ #include <fsp/soc_binding.h> @@ -304,35 +304,14 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku) continue; /* Populate the DIMM information */ - dest_dimm->dimm_size = src_dimm->SizeInMb; - dest_dimm->ddr_type = memory_info_hob->MemoryType; - dest_dimm->ddr_frequency = - memory_info_hob->MemoryFrequencyInMHz; - dest_dimm->channel_num = channel_info->ChannelId; - dest_dimm->dimm_num = src_dimm->DimmId; - strncpy((char *)dest_dimm->module_part_number, - lp4cfg->skus[mem_sku].part_num, - sizeof(dest_dimm->module_part_number)); - - switch (memory_info_hob->DataWidth) { - case 8: - dest_dimm->bus_width = MEMORY_BUS_WIDTH_8; - break; - case 16: - dest_dimm->bus_width = MEMORY_BUS_WIDTH_16; - break; - case 32: - dest_dimm->bus_width = MEMORY_BUS_WIDTH_32; - break; - case 64: - dest_dimm->bus_width = MEMORY_BUS_WIDTH_64; - break; - case 128: - dest_dimm->bus_width = MEMORY_BUS_WIDTH_128; - break; - default: - printk(BIOS_ERR, "Incorrect DIMM Data Width"); - } + dimm_info_fill(dest_dimm, + src_dimm->SizeInMb, + memory_info_hob->MemoryType, + memory_info_hob->MemoryFrequencyInMHz, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)lp4cfg->skus[mem_sku].part_num, + memory_info_hob->DataWidth); index++; } }

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Patch set updated for coreboot: soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOB
by Barnali Sarkar 23 Feb '17

23 Feb '17

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18275 -gerrit commit 96cfc93fc16891ca105db08ae996478b31877f75 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Fri Feb 10 21:36:58 2017 +0530 soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOB Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and save it in CBMEM. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS Table from Kernel command "dmidecode". Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/include/fsp20/soc/romstage.h | 1 + src/soc/intel/skylake/romstage/romstage_fsp20.c | 78 +++++++++++++++++++++- 2 files changed, 78 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index 41658e1..5be8b7c 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -25,6 +25,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); +void save_dimm_info(void); /* Board type */ enum board_type { BOARD_TYPE_MOBILE = 0, diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index a4bb684..67538dd 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -26,10 +26,13 @@ #include <device/pci_def.h> #include <fsp/util.h> #include <fsp/memmap.h> +#include <memory_info.h> +#include <soc/intel/common/smbios.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> +#include <string.h> #include <timestamp.h> #include <vboot/vboot_common.h> @@ -39,6 +42,12 @@ */ #define ROMSTAGE_RAM_STACK_SIZE 0x5000 +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + asmlinkage void *car_stage_c_entry(void) { bool s3wake; @@ -56,7 +65,8 @@ asmlinkage void *car_stage_c_entry(void) s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - + if (!s3wake) + save_dimm_info(); if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); @@ -188,3 +198,69 @@ __attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Do nothing */ } + +/* Save the DIMM information for SMBIOS table 17 */ +void save_dimm_info(void) +{ + int channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = + fsp_find_extension_hob_by_guid(smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + ctrlr_info = &memory_info_hob->Controller[0]; + for (channel = 0; channel < ctrlr_info->ChannelCount; channel++) { + if (index >= dimm_max) + break; + channel_info = &ctrlr_info->Channel[channel]; + for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { + if (index >= dimm_max) + break; + src_dimm = &channel_info->Dimm[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (!src_dimm->DimmCapacity) + continue; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + memory_info_hob->DdrType, + memory_info_hob->Frequency, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + memory_info_hob->DataWidth); + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +}

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Patch set updated for coreboot: soc/intel/common: Save Memory DIMM Information in SMBIOS table
by Barnali Sarkar 23 Feb '17

23 Feb '17

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18418 -gerrit commit c3befb3d522e439fcd4a145be04b2d9082723d62 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Tue Feb 21 16:24:49 2017 +0530 soc/intel/common: Save Memory DIMM Information in SMBIOS table Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM. Add function dimm_info_fill() which populates SMBIOS memory information from FSP MEM_INFO_DATA_HOB data. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS table from Kernel command "dmidecode". Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/smbios.c | 53 +++++++++++++++++++++++++++++++++++++++ src/soc/intel/common/smbios.h | 27 ++++++++++++++++++++ 3 files changed, 81 insertions(+) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index d6e1e75..25e51cd 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -13,6 +13,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c +romstage-y += smbios.c postcar-y += util.c postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c new file mode 100644 index 0000000..3aee9ff --- /dev/null +++ b/src/soc/intel/common/smbios.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include "smbios.h" +#include <string.h> +#include <console/console.h> + +/* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ +void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, + u32 frequency, u8 channel_id, u8 dimm_id, const char *module_part_num, + u16 data_width) +{ + dimm->dimm_size = dimm_capacity; + dimm->ddr_type = ddr_type; + dimm->ddr_frequency = frequency; + dimm->channel_num = channel_id; + dimm->dimm_num = dimm_id; + strncpy((char *)dimm->module_part_number, + module_part_num, + sizeof(dimm->module_part_number)); + switch (data_width) { + case 8: + dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + case 16: + dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + case 32: + dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + case 64: + dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + case 128: + dimm->bus_width = MEMORY_BUS_WIDTH_128; + break; + default: + printk(BIOS_ERR, "Incorrect DIMM Data width"); + } +} diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h new file mode 100644 index 0000000..d38d612 --- /dev/null +++ b/src/soc/intel/common/smbios.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _COMMON_SMBIOS_H_ +#define _COMMON_SMBIOS_H_ + +#include <stdint.h> +#include <memory_info.h> + +/* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ +void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, + u32 frequency, u8 channel_id, u8 dimm_id, const char *module_part_num, + u16 data_width); + +#endif /* _COMMON_SMBIOS_H_ */

1 0

Patch set updated for coreboot: src/vendorcode: Add Memory Info Data HOB Header
by Barnali Sarkar 23 Feb '17

23 Feb '17

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18326 -gerrit commit 1c7682c08f3a22afc8a89c251305439273c54260 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Fri Feb 10 21:46:05 2017 +0530 src/vendorcode: Add Memory Info Data HOB Header Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the MEM_INFO_DATA_HOB. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- .../intel/fsp/fsp2_0/skykabylake/FspmUpd.h | 1 + .../intel/fsp/fsp2_0/skykabylake/MemInfoHob.h | 214 +++++++++++++++++++++ 2 files changed, 215 insertions(+) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h index 89dc419..6bb57a1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h @@ -34,6 +34,7 @@ are permitted provided that the following conditions are met: #define __FSPMUPD_H__ #include <FspUpd.h> +#include "MemInfoHob.h" #pragma pack(1) diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h new file mode 100644 index 0000000..8dc2db9 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h @@ -0,0 +1,214 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 1 +#define MAX_CH 2 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef bmCold +#define bmCold 0 // Cold boot +#endif +#ifndef bmWarm +#define bmWarm 1 // Warm boot +#endif +#ifndef bmS3 +#define bmS3 2 // S3 resume +#endif +#ifndef bmFast +#define bmFast 3 // Fast boot +#endif + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. +} MRC_CH_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT32 Frequency; ///< The system's common memory controller frequency in MT/s. + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + UINT32 FreqMax; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_

1 0

New patch to review for coreboot: mb/google/poppy: Disbale voltage margining
by Rizwan Qureshi 23 Feb '17

23 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18470 -gerrit commit 5e45f5303f6931c5e56fd3ac14dc5493ba6b8cf9 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 23 15:06:56 2017 +0530 mb/google/poppy: Disbale voltage margining Voltage margining should be disabled for S0ix to work, disable the voltage margining when SLP_S0# is asserted. Change-Id: I68d4069563651c65c7b7a9d7fc16f7c12310ac1f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 07cacc0..7f90ad0 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -52,6 +52,7 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" register "SendVrMbxCmd" = "1" # IMVP8 workaround + register "PchPmSlpS0VmEnable" = "0" # Disbale Voltage Margining register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10"

1 0

New patch to review for coreboot: soc/intel/skylake: Add config for enable/disable voltage margining
by Rizwan Qureshi 23 Feb '17

23 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18469 -gerrit commit 147c5d2cffd099f988d25465775cabc24f63f3ed Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 23 14:43:39 2017 +0530 soc/intel/skylake: Add config for enable/disable voltage margining Voltage margining should be disabled for S0ix to work, FSP provides a UPD to enable/disable the voltage margining when SLP_S0# is asserted, expose the same as a config option in devicetree.cb. Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/chip.h | 8 ++++++++ src/soc/intel/skylake/chip_fsp20.c | 1 + 2 files changed, 9 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 07cb8b1..f122a4c 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -332,6 +332,14 @@ struct soc_intel_skylake_config { * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s */ u8 PmConfigPwrBtnOverridePeriod; + + /* + * PCH Pm Slp S0 Voltage Margining Enable + * Indicates platform has support for VCCPrim_Core Voltage Margining + * in SLP_S0# asserted state. + */ + u8 PchPmSlpS0VmEnable; + /* * Reset Power Cycle Duration could be customized in the unit of second. * PCH HW default is 4 seconds, and range is 1~4 seconds. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 2b50d0c..9042451 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -220,6 +220,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; params->PchSirqEnable = config->SerialIrqConfigSirqEnable; params->PchSirqMode = config->SerialIrqConfigSirqMode;

1 0

Patch set updated for coreboot: mainboard/intel: common code for Intel boards
by Hannah Williams 23 Feb '17

23 Feb '17

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18468 -gerrit commit 485771b708bb13b6757836404d064871e7183ede Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Feb 14 09:32:28 2017 -0800 mainboard/intel: common code for Intel boards This is a WIP patch to see if having a common mainboard code for INTEL platforms is feasible. Change-Id: I704951c82ba09b7d8c606f4086ee2404169b3673 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/common/Kconfig | 49 +++++ src/mainboard/intel/common/Makefile.inc | 21 ++ src/mainboard/intel/common/boardid.c | 35 +++ src/mainboard/intel/common/bootblock.c | 32 +++ src/mainboard/intel/common/chromeos.c | 86 ++++++++ src/mainboard/intel/common/ec.c | 46 ++++ src/mainboard/intel/common/include/ec.h | 59 +++++ src/mainboard/intel/common/include/meminit.h | 99 +++++++++ src/mainboard/intel/common/include/variants.h | 48 +++++ src/mainboard/intel/common/mainboard.c | 79 +++++++ src/mainboard/intel/common/meminit_fsp2_atom.c | 284 +++++++++++++++++++++++++ src/mainboard/intel/common/meminit_fsp2_core.c | 64 ++++++ src/mainboard/intel/common/ramstage.c | 40 ++++ src/mainboard/intel/common/smihandler.c | 54 +++++ 14 files changed, 996 insertions(+) diff --git a/src/mainboard/intel/common/Kconfig b/src/mainboard/intel/common/Kconfig new file mode 100644 index 0000000..2eca9f4 --- /dev/null +++ b/src/mainboard/intel/common/Kconfig @@ -0,0 +1,49 @@ +config INTEL_MAINBOARD_COMMON + bool "Using Intel mainboard common" + default n + help + Common code for Intel mainboards + + +config MAINBOARD_COMMON_LPC_CONFIG + bool "Configure LPC from mainboard common" + default n + help + Configure LPC from mainboard common + + +config MAINBOARD_COMMON_GPIO_CONFIG + bool "Configure GPIO from mainboard common" + default n + help + Configure GPIO from mainboard common + +config HAVE_SPD + bool "Read data from SPD on SMBUS" + default n + help + Read data from SPD on SMBUS + +config HAVE_SPD_BIN + bool "Read data from spd.bin" + default n + help + Read data from spd.bin + +config MAINBOARD_COMMON_WRITE_ACPI_TABLES + bool "update acpi tables from mainboard common" + default n + help + update acpi tables from mainboard common + +config MAINBOARD_COMMON_FSP2_CORE + bool "Is this platform using FSP2.0 for CORE SOCs" + default n + help + Is this platform using FSP2.0 for CORE SOCs + +config MAINBOARD_COMMON_FSP2_ATOM + bool "Is this platform using FSP2.0 for ATOM SOCs" + default n + help + Is this platform using FSP2.0 for ATOM SOCs diff --git a/src/mainboard/intel/common/Makefile.inc b/src/mainboard/intel/common/Makefile.inc new file mode 100644 index 0000000..346fe7b --- /dev/null +++ b/src/mainboard/intel/common/Makefile.inc @@ -0,0 +1,21 @@ +#ifeq ($(CONFIG_INTEL_MAINBOARD_COMMON),y) + +bootblock-y += bootblock.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += boardid.c +romstage-$(CONFIG_MAINBOARD_COMMON_FSP2_CORE) += meminit_fsp2_core.c +romstage-$(CONFIG_MAINBOARD_COMMON_FSP2_ATOM) += meminit_fsp2_atom.c + + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c +ramstage-y += mainboard.c +ramstage-y += boardid.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +CPPFLAGS_common += -I$(src)/mainboard/intel/common/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants +#endif diff --git a/src/mainboard/intel/common/boardid.c b/src/mainboard/intel/common/boardid.c new file mode 100644 index 0000000..25e1b17 --- /dev/null +++ b/src/mainboard/intel/common/boardid.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variants.h> +#include <ec/google/chromeec/ec.h> + +uint8_t __attribute__((weak)) variant_board_id(void) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + return google_chromeec_get_board_version(); + else + return 0; +} + +uint8_t __attribute__((weak)) variant_get_spd_index(void) +{ + return 0; +} + +size_t __attribute__((weak)) variant_memory_sku(void ) +{ + return 0; +} diff --git a/src/mainboard/intel/common/bootblock.c b/src/mainboard/intel/common/bootblock.c new file mode 100644 index 0000000..7001220 --- /dev/null +++ b/src/mainboard/intel/common/bootblock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variants.h> +#include <bootblock_common.h> +#include <soc/lpc.h> +#include <soc/gpio.h> +#include <variant/ec.h> + +void mainboard_ec_init(void); + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + if (IS_ENABLED(CONFIG_MAINBOARD_LPC_CONFIG)) + lpc_configure_pads();/* TODO Add bootblock_ec_init into soc folder as lpc_configure_ioport)*/ + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/intel/common/chromeos.c b/src/mainboard/intel/common/chromeos.c new file mode 100644 index 0000000..5b6bd3a --- /dev/null +++ b/src/mainboard/intel/common/chromeos.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variants.h> +#include <boot/coreboot_tables.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, + gpio_get(GPIO_EC_IN_RW), "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_lid_switch(void) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + else + return 1; +} + +int get_developer_mode_switch(void) +{ + /* No physical developer mode switch. It's virtual. */ + return 0; +} + +int get_recovery_mode_switch(void) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Check if the EC has posted the keyboard recovery event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + return 0; +} + +int clear_recovery_mode_switch(void) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Clear keyboard recovery event. */ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + else + return 0; +} + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/intel/common/ec.c b/src/mainboard/intel/common/ec.c new file mode 100644 index 0000000..7a5bda2 --- /dev/null +++ b/src/mainboard/intel/common/ec.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "./include/ec.h" + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard: EC init\n"); + + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + + /* Restore SCI event mask */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake event mask */ + google_chromeec_set_wake_mask(0); +} diff --git a/src/mainboard/intel/common/include/ec.h b/src/mainboard/intel/common/include/ec.h new file mode 100644 index 0000000..9fe3dad --- /dev/null +++ b/src/mainboard/intel/common/include/ec.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_COMMON_EC_H +#define MAINBOARD_COMMON_EC_H + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#endif diff --git a/src/mainboard/intel/common/include/meminit.h b/src/mainboard/intel/common/include/meminit.h new file mode 100644 index 0000000..bc45200 --- /dev/null +++ b/src/mainboard/intel/common/include/meminit.h @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_COMMON_MEMINIT_H_ +#define _MAINBOARD_COMMON_MEMINIT_H_ + +#include <stddef.h> +#include <stdint.h> + +/* + * There are 4 physical channels each 32-bits wide. There are 2 logical + * channels using 2 physical channels together to form a 64-bit interface to + * memory for each logical channel. + */ +enum { + DDR_PHYS_CH0A, + DDR_PHYS_CH0B, + DDR_PHYS_CH1A, + DDR_PHYS_CH1B, + DDR_NUM_PHYS_CHANNELS +}; + +/* Logical channel identification. */ +enum { + DDR_LCH0, + DDR_LCH1 +}; + +/* + * The DQs within a physical channel can be bit-swizzled within each byte. + * Within a channel the bytes can be swapped, but the DQs need to be routed + * with the corresponding DQS (strobe). + */ +enum { + DDR_DQS0, + DDR_DQS1, + DDR_DQS2, + DDR_DQS3, + DDR_NUM_BYTE_LANES, + DQ_BITS_PER_DQS = 8, +}; + +enum { + LP4_SPEED_1600, + LP4_SPEED_2133, + LP4_SPEED_2400, +}; + +/* LPDDR4 module density in bits. */ +enum { + DDR_8Gb_DENSITY = 2, + DDR_12Gb_DESNITY, + DDR_16Gb_DENSITY, +}; + +/* Provide bit swizzling per DQS and byte swapping within a channel. */ +struct ddr_chan_swizzle_cfg { + uint8_t dqs[DDR_NUM_BYTE_LANES][DQ_BITS_PER_DQS]; +}; + +struct ddr_swizzle_cfg { + struct ddr_chan_swizzle_cfg phys[DDR_NUM_PHYS_CHANNELS]; +}; + + +struct ddr_sku { + int speed; + int ch0_rank_density; + int ch1_rank_density; + int ch0_dual_rank; + int ch1_dual_rank; + const char *part_num; + bool disable_periodic_retraining; +}; + +struct ddr_cfg { + const struct ddr_sku *skus; + size_t num_skus; + const struct ddr_swizzle_cfg *swizzle_config; +}; + + +void save_lpddr4_dimm_info(const struct ddr_cfg *lpcfg, size_t mem_sku); +void override_ddr_defaults(FSP_M_CONFIG *cfg); +void soc_display_memory_init_params(FSP_M_CONFIG *fspm_cfg); + +#endif /* _MAINBOARD_COMMON_MEMINIT_H_ */ diff --git a/src/mainboard/intel/common/include/variants.h b/src/mainboard/intel/common/include/variants.h new file mode 100644 index 0000000..caa3399 --- /dev/null +++ b/src/mainboard/intel/common/include/variants.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include <soc/gpio.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Return the board id for the current variant board. */ +uint8_t variant_board_id(void); + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_sleep_gpio_table(size_t *num); + +/* Baseboard default swizzle. Can be reused if swizzle is same. */ +extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle; +/* Return LPDDR4 configuration structure. */ +const struct ddr_cfg *variant_ddr_config(void); +/* Return memory SKU for the board. */ +size_t variant_memory_sku(void); + +/* Return ChromeOS gpio table and fill in number of entries. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +/* Seed the NHLT tables with the board specific information. */ +struct nhlt; +void variant_nhlt_init(struct nhlt *nhlt); + +uint8_t variant_get_spd_index(void); + +#endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/intel/common/mainboard.c b/src/mainboard/intel/common/mainboard.c new file mode 100644 index 0000000..6b474bb --- /dev/null +++ b/src/mainboard/intel/common/mainboard.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <variants.h> +#include <boardid.h> +#include <console/console.h> +#include <device/device.h> +#include <nhlt.h> +#include <soc/gpio.h> +#include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <variant/ec.h> +#include <variant/gpio.h> + +void mainboard_ec_init(void); + +static void mainboard_init(device_t dev) +{ + size_t num; + const void *pads; + if (IS_ENABLED(CONFIG_MAINBOARD_GPIO_CONFIG)) { + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + } + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); +} + +#if IS_ENABLED(CONFIG_MAINBOARD_WRITE_ACPI_TABLES) +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + variant_nhlt_init(nhlt); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} +#endif + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +#if IS_ENABLED(CONFIG_MAINBOARD_WRITE_ACPI_TABLES) + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; +#endif + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/common/meminit_fsp2_atom.c b/src/mainboard/intel/common/meminit_fsp2_atom.c new file mode 100644 index 0000000..2315955 --- /dev/null +++ b/src/mainboard/intel/common/meminit_fsp2_atom.c @@ -0,0 +1,284 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/byteorder.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <string.h> +#include <meminit.h> +#include <variants.h> +#include <smbios.h> +#include <memory_info.h> +#include <cbmem.h> +#include <fsp/util.h> + + +#define CONFIG_CHANNEL(log_num, phys_num, fspm_cfg, sku, chan) \ + fspm_cfg->Ch##phys_num##_DramDensity = \ + sku->ch##log_num##_rank_density; \ + fspm_cfg->Ch##phys_num##_RankEnable = \ + sku->ch##log_num##_dual_rank ? 0x1 : 0x3; \ + memcpy(&fspm_cfg->Ch##phys_num##_Bit_swizzling[0], \ + &(chan)->dqs[DDR_DQS0] ,DQ_BITS_PER_DQS); \ + memcpy(&fspm_cfg->Ch##phys_num##_Bit_swizzling[8], \ + &(chan)->dqs[DDR_DQS1],DQ_BITS_PER_DQS); \ + memcpy(&fspm_cfg->Ch##phys_num##_Bit_swizzling[16], \ + &(chan)->dqs[DDR_DQS2] ,DQ_BITS_PER_DQS); \ + memcpy(&fspm_cfg->Ch##phys_num##_Bit_swizzling[24], \ + &(chan)->dqs[DDR_DQS3],DQ_BITS_PER_DQS); + + +#define PRINT_CHANNEL_CONFIG(fspm_cfg, phys_num) \ +printk(BIOS_SPEW,"RankEnable : %x\n", \ + fspm_cfg->Ch##phys_num##_RankEnable); \ +printk(BIOS_SPEW,"DeviceWidth : %x\n", \ + fspm_cfg->Ch##phys_num##_DeviceWidth); \ +printk(BIOS_SPEW,"DramDensity : %x\n", \ + fspm_cfg->Ch##phys_num##_DramDensity); \ +printk(BIOS_SPEW,"Option : %x\n", \ + fspm_cfg->Ch##phys_num##_Option); \ +printk(BIOS_SPEW,"OdtConfig : %x\n", \ + fspm_cfg->Ch##phys_num##_OdtConfig); \ +printk(BIOS_SPEW,"TristateClk1 : %x\n", \ + fspm_cfg->Ch##phys_num##_TristateClk1); \ +printk(BIOS_SPEW,"Mode2N : %x\n", \ + fspm_cfg->Ch##phys_num##_Mode2N); \ +printk(BIOS_SPEW,"OdtLevels : %x\n", \ + fspm_cfg->Ch##phys_num##_OdtLevels); \ +{ \ +int i; \ + printk(BIOS_SPEW,"Bit_swizzling:\n"); \ + for(i=0; i < 32; i++) \ + { \ + printk(BIOS_SPEW," %02d ", \ + fspm_cfg->Ch##phys_num##_Bit_swizzling[i]); \ + if((i) && (i%8) == 7) \ + printk(BIOS_SPEW,"\n"); \ + } \ + printk(BIOS_SPEW,"\n"); \ +} + +__attribute__((weak)) void override_ddr_defaults(FSP_M_CONFIG *cfg) +{ + return; +} + +static void set_ddr_defaults(FSP_M_CONFIG *cfg) +{ + /* Enable memory down BGA since it's the only LPDDR4 packaging. */ + cfg->Package = 1; + cfg->MemoryDown = 1; + + cfg->ScramblerSupport = 1; + cfg->ChannelHashMask = 0x36; + cfg->SliceHashMask = 0x9; + cfg->InterleavedMode = 2; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 1; + /* Don't enforce a memory size limit. */ + cfg->MemorySizeLimit = 0; + /* Use a 2GiB I/O hole -- field is in MiB units. */ + cfg->LowMemoryMaxValue = 2 * (GiB/MiB); + /* No restrictions on memory above 4GiB */ + cfg->HighMemoryMaxValue = 0; + + /* Always default to attempt to use saved training data. */ + cfg->DisableFastBoot = 0; + + /* memory down so no SPD addresses. */ + cfg->DIMM0SPDAddress = 0; + cfg->DIMM1SPDAddress = 0; + + /* Clear all the rank enables. */ + cfg->Ch0_RankEnable = 0x0; + cfg->Ch1_RankEnable = 0x0; + cfg->Ch2_RankEnable = 0x0; + cfg->Ch3_RankEnable = 0x0; + + /* + * Set the device width to x16 which is half a LPDDR4 module as that's + * what the reference code expects. + */ + cfg->Ch0_DeviceWidth = 0x1; + cfg->Ch1_DeviceWidth = 0x1; + cfg->Ch2_DeviceWidth = 0x1; + cfg->Ch3_DeviceWidth = 0x1; + + /* + * Enable bank hashing (bit 1) and rank interleaving (bit 0) with + * a 1KiB address mapping (bits 5:4). + */ + cfg->Ch0_Option = 0x3; + cfg->Ch1_Option = 0x3; + cfg->Ch2_Option = 0x3; + cfg->Ch3_Option = 0x3; + + /* Weak on-die termination. */ + cfg->Ch0_OdtConfig = 0; + cfg->Ch1_OdtConfig = 0; + cfg->Ch2_OdtConfig = 0; + cfg->Ch3_OdtConfig = 0; + override_ddr_defaults(cfg); +} + +static void set_ddr_profile(FSP_M_CONFIG *cfg, int speed) +{ + uint8_t profile; + + switch (speed) { + case LP4_SPEED_1600: + profile = 0x9; + break; + case LP4_SPEED_2133: + profile = 0xa; + break; + case LP4_SPEED_2400: + profile = 0xb; + break; + default: + printk(BIOS_WARNING, "Invalid DDR speed: %d\n", speed); + /* Set defaults. */ + speed = LP4_SPEED_1600; + profile = 0x9; + } + + printk(BIOS_INFO, "DDR speed is %dMHz\n", speed); + cfg->Profile = profile; +} + +void soc_display_memory_init_params(FSP_M_CONFIG *fspm_cfg) +{ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + printk(BIOS_SPEW, "Channel0:\n"); + PRINT_CHANNEL_CONFIG(fspm_cfg, 0); + printk(BIOS_SPEW, "Channel1:\n"); + PRINT_CHANNEL_CONFIG(fspm_cfg, 1); + printk(BIOS_SPEW, "Channel2:\n"); + PRINT_CHANNEL_CONFIG(fspm_cfg, 2); + printk(BIOS_SPEW, "Channel3:\n"); + PRINT_CHANNEL_CONFIG(fspm_cfg, 3); + +} + +__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *fspm_cfg = &mupd->FspmConfig; + const struct ddr_cfg *mem_cfg = variant_ddr_config(); + size_t sku_id = variant_memory_sku(); + const struct ddr_sku *sku = &mem_cfg->skus[sku_id]; + const struct ddr_swizzle_cfg *scfg= mem_cfg->swizzle_config; + + set_ddr_defaults(fspm_cfg); + set_ddr_profile(fspm_cfg, sku->speed); + if (sku->ch0_rank_density) { + CONFIG_CHANNEL(0, 0, fspm_cfg, sku, + &scfg->phys[DDR_PHYS_CH0A] ); + CONFIG_CHANNEL(0, 1, fspm_cfg, sku, + &scfg->phys[DDR_PHYS_CH0B] ); + } + if (sku->ch1_rank_density) { + CONFIG_CHANNEL(1, 2, fspm_cfg, sku, + &scfg->phys[DDR_PHYS_CH1A] ); + CONFIG_CHANNEL(1, 3, fspm_cfg, sku, + &scfg->phys[DDR_PHYS_CH1B] ); + } + //cfg->PeriodicRetrainingDisable = sku->disable_periodic_retraining; + soc_display_memory_init_params(fspm_cfg); +} + +void mainboard_save_dimm_info(void) +{ + const struct ddr_cfg *cfg = variant_ddr_config(); + size_t mem_sku = variant_memory_sku(); + int channel, dimm, dimm_max, index; + size_t hob_size; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const CHANNEL_INFO *channel_info; + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + + if (mem_sku >= cfg->num_skus) { + printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n", + mem_sku, cfg->num_skus); + return; + } + + memory_info_hob = fsp_find_smbios_memory_info(&hob_size); + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { + if (index >= dimm_max) + break; + channel_info = &memory_info_hob->ChannelInfo[channel]; + for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { + if (index >= dimm_max) + break; + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (!src_dimm->SizeInMb) + continue; + + /* Populate the DIMM information */ + dest_dimm->dimm_size = src_dimm->SizeInMb; + dest_dimm->ddr_type = memory_info_hob->MemoryType; + dest_dimm->ddr_frequency = + memory_info_hob->MemoryFrequencyInMHz; + dest_dimm->channel_num = channel_info->ChannelId; + dest_dimm->dimm_num = src_dimm->DimmId; + strncpy((char *)dest_dimm->module_part_number, + cfg->skus[mem_sku].part_num, + sizeof(dest_dimm->module_part_number)); + + switch (memory_info_hob->DataWidth) { + case 8: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + case 16: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + case 32: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + case 64: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + case 128: + dest_dimm->bus_width = MEMORY_BUS_WIDTH_128; + break; + default: + printk(BIOS_ERR, "Incorrect DIMM Data Width"); + } + index++; + } + } + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} diff --git a/src/mainboard/intel/common/meminit_fsp2_core.c b/src/mainboard/intel/common/meminit_fsp2_core.c new file mode 100644 index 0000000..2d894a7 --- /dev/null +++ b/src/mainboard/intel/common/meminit_fsp2_core.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <string.h> +#include <spd_bin.h> + +extern const uint8_t dq_map[][]; +extern const uint8_t dqs_map[][]; +extern const uint8_t rcomp_resistor[]; +extern const uint8_t rcomp_target[]; +extern const uint8_t dq_pins_interleaved; + +__attribute__((weak)) void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + u8 spd_index = variant_get_spd_index(); + + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); + memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); + + mem_cfg->DqPinsInterleaved = dq_pins_interleaved; + + if (IS_ENABLED(CONFIG_HAVE_SPD_BIN)) { + struct region_device spd_rdev; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + } else if (IS_ENABLED(CONFIG_HAVE_SPD)) { + struct spd_block blk; + + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0]; + } + else { + die("spd data not found\n"); + } + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; +} diff --git a/src/mainboard/intel/common/ramstage.c b/src/mainboard/intel/common/ramstage.c new file mode 100644 index 0000000..b3062cb --- /dev/null +++ b/src/mainboard/intel/common/ramstage.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/i2c.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> + +__attribute__((weak)) +void variant_mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + return; +} + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + variant_mainboard_silicon_init_params(params); +} + +__attribute__((weak)) void dev_init_exit(void *unused) +{ + /* add any board specific init here which needs to be run after + BS_POST_DEVICE */ + return; +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, dev_init_exit, NULL); diff --git a/src/mainboard/intel/common/smihandler.c b/src/mainboard/intel/common/smihandler.c new file mode 100644 index 0000000..8cfa61e --- /dev/null +++ b/src/mainboard/intel/common/smihandler.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <variants.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <soc/gpio.h> +#include "include/ec.h" +#include <variant/ec.h> +#include <variant/gpio.h> + +void mainboard_smi_gpi_handler(const struct gpi_status *sts) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + if (gpi_status_get(sts, EC_SMI_GPI)) + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(&num); + gpio_configure_pads(pads, num); + + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +}

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coreboot-gerrit February 2017