coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: google/oak: Add initial support for Rowan
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit 57debca234af42b2b60aa58d42283871122f6b43 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Fri Feb 17 15:59:17 2017 +0800 google/oak: Add initial support for Rowan Update GPIO controls and mainboard configurations for Rowan. [pg: use the opportunity to clean-up the gerrit-rebase task list with the entirely unrelated Ignore-CL-Reviewed-on lines] BUG=chrome-os-partner:62672 BRANCH=none TEST=emerge-rowan coreboot Change-Id: I110fb368b3d9fa9dfb2bf091342dfb511ff7c09c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f4252cbe94a7456108aaa522e170bca5dcb1fdd1 Original-Change-Id: I18ebc3ccf4c7d051839d7c50e9b0682ef8f09830 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/430557 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/341513 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/327003 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/355221 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/354670 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361360 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361361 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361362 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/361363 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/382320 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405110 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/405130 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/419795 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/424139 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430293 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430294 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/430295 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427820 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427821 Ignore-CL-Reviewed-on: https://chromium-review.googlesource.com/427822 Reviewed-on: https://review.coreboot.org/18463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18463 for details. -gerrit

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Patch merged into coreboot/master: google/gru: improve eye diagram for passing the test
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit 9e588004f6133e671971f352ed4f086c9f938025 Author: Caesar Wang <wxt(a)rock-chips.com> Date: Fri Feb 10 11:16:13 2017 +0800 google/gru: improve eye diagram for passing the test The children of Gru should share the benefits. In the real world, Bob can't pass the eye diagram tests. BUG=chrome-os-partner:62714 BRANCH=firmware-gru-8785.B TEST=build coreboot Change-Id: I2470bbc81acdaf2458d660dca5dc307cc3038f83 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d0cb3e718a7571f602a00c08a42019851634e7fd Original-Change-Id: I0ccb48bb52eb770ccc9c8c265b07df46b0308dd3 Original-Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/440745 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/441468 Reviewed-on: https://review.coreboot.org/18461 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18461 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: Enable Systemagent IMGU
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit c2c8a743d1941998e6c316adec98947509ab387e Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:04:11 2017 +0530 soc/intel/skylake: Enable Systemagent IMGU Camera and Imaging device should be enabled for camera usecase, FSP provides a UPD to enable/disable the SA IMGU (Imaging Unit) expose the same as a config option in devicetree.cb Also remove a redundant assignment for PchCio2Enable. BUG=None BRANCH=None TEST=lspci should list 00:05:00 Change-Id: I4cf7daf41bfaf4dcba414921cac2e7e12bf89f37 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-on: https://review.coreboot.org/18365 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18365 for details. -gerrit

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Patch merged into coreboot/master: mt8173: Enable Kconfig options for ChromeOS
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit 30d4604e5a33e735e59765ff94a61d78ca419654 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Tue Feb 21 23:52:59 2017 +0100 mt8173: Enable Kconfig options for ChromeOS This enables some required Kconfig options when CONFIG_CHROMEOS is set. Change-Id: I290902746c1ea19c8bcb69540e34fde09abb9adf Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: https://review.coreboot.org/18448 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See https://review.coreboot.org/18448 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Add oak config
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit 7a543d2ab9433c1df117a216e04ac96ebd1d3078 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Tue Feb 21 23:49:11 2017 +0100 libpayload: Add oak config This adds an oak libpayload config, that should fit all oak-based devices such as elm. Change-Id: Iabb71404ff84029a5976371a353e8c92e781ca1f Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: https://review.coreboot.org/18447 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See https://review.coreboot.org/18447 for details. -gerrit

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Patch merged into coreboot/master: mb/apple/macbook21: Remove unused cmos parameters
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit 00954f081538bdfb052e7a3eaa86a69de9e1020d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 3 17:30:35 2017 +0100 mb/apple/macbook21: Remove unused cmos parameters These parameters are probably the result of copying from the Thinkpad X60 code. Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18290 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18290 for details. -gerrit

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New patch to review for coreboot: MAINTAINERS: Add myself as me_cleaner maintainer
by Nicola Corna 23 Feb '17

23 Feb '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18474 -gerrit commit 2eec42af4fb69bff98c5a5aee5934a40404ec390 Author: Nicola Corna <nicola(a)corna.info> Date: Thu Feb 23 16:53:45 2017 +0100 MAINTAINERS: Add myself as me_cleaner maintainer Change-Id: Ia95f6beb1546efdb75a49bccfe293822f0785d7a Signed-off-by: Nicola Corna <nicola(a)corna.info> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 015dbbf..e672fd7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -384,6 +384,12 @@ INTELMETOOL M: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> F: util/intelmetool/ +ME_CLEANER +M: Nicola Corna <nicola(a)corna.info> +W: https://github.com/corna/me_cleaner +S: Maintained +F: util/me_cleaner/ + IFDTOOL M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> F: util/ifdtool/

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Patch set updated for coreboot: nb/i945: Clean "Programming DLL Timings" function
by HAOUAS Elyes 23 Feb '17

23 Feb '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18472 -gerrit commit 47c662daf005960e681f1d712358960e4bb5832b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Feb 23 13:14:44 2017 +0100 nb/i945: Clean "Programming DLL Timings" function As we drive both channels with the same speed, chen0dll and chen1dll are the same. Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a8bb5e7..8fada16 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1227,7 +1227,7 @@ static void sdram_enable_rcomp(void) static void sdram_program_dll_timings(struct sys_info *sysinfo) { - u32 chan0dll = 0, chan1dll = 0; + u32 channeldll = 0; int i; printk(BIOS_DEBUG, "Programming DLL Timings...\n"); @@ -1238,26 +1238,26 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) /* We drive both channels with the same speed */ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ + case 400: channeldll = 0x26262626; break; + case 533: channeldll = 0x22222222; break; + case 667: channeldll = 0x11111111; break; } } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ - case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ - case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ + case 400: channeldll = 0x33333333; break; + case 533: channeldll = 0x24242424; break; + case 667: channeldll = 0x25252525; break; } } for (i = 0; i < 4; i++) { - MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll; - MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = chan0dll & 0xff; - MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = chan1dll & 0xff; + MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; + MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } } }

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New patch to review for coreboot: util/me_cleaner: Pull the latest changes from upstream
by Nicola Corna 23 Feb '17

23 Feb '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18473 -gerrit commit 8d09bfb97f9afb7e18cc131b742946a3aae9fe09 Author: Nicola Corna <nicola(a)corna.info> Date: Wed Feb 22 10:16:32 2017 +0100 util/me_cleaner: Pull the latest changes from upstream Relevant changes (commit 250b2ec): * Fix a bug for ME6 Ignition images. * Fix signature checking for ME11 and later. * Add command line arguments. * Add an option to relocate the FTPR partition to the top of the ME region, recovering most of the ME region space. * Print the image minimum size. * Add write boundary checks, to prevent writes on other regions in case of bugs. The new changes have been tested on multiple platforms by the me_cleaner users. They have been tested also on the author's X220T with coreboot, where the ME region has been shrinked up to 84 kB without any issue. Change-Id: I3bd6b4cba9f5eebc3cd4892dd9f188744a06c42b Signed-off-by: Nicola Corna <nicola(a)corna.info> --- util/me_cleaner/README.md | 3 +- util/me_cleaner/me_cleaner.py | 438 ++++++++++++++++++++++++++++++------------ 2 files changed, 317 insertions(+), 124 deletions(-) diff --git a/util/me_cleaner/README.md b/util/me_cleaner/README.md index 9a09b55..0ca3d32 100644 --- a/util/me_cleaner/README.md +++ b/util/me_cleaner/README.md @@ -12,7 +12,8 @@ Currently this tool: * Removes any partition except for the fundamental one (FTPR) * Removes the EFFS presence flag * Corrects the FPT checksum - * Removes any non-essential LZMA or Huffman compressed module (pre-Skylake only) + * Removes any non-essential LZMA or Huffman compressed module from the FTPR partition (pre-Skylake only) + * Relocates the remaining parts of the FTPR partition to the top of the ME region (pre-Skylake only) * Checks the validity of the RSA signature of the FTPR partition Don't forget to power cycle your PC after flashing the modified ME/TXE image diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py index 2ad5898..8ca5498 100755 --- a/util/me_cleaner/me_cleaner.py +++ b/util/me_cleaner/me_cleaner.py @@ -18,12 +18,70 @@ import sys import itertools import binascii import hashlib +import argparse +import shutil from struct import pack, unpack +min_ftpr_offset = 0x400 +spared_blocks = 4 unremovable_modules = ("BUP", "ROMP") +class OutOfRegionException(Exception): + pass + + +class regionFile: + def __init__(self, f, region_start, region_end): + self.f = f + self.region_start = region_start + self.region_end = region_end + + def read(self, n): + return self.f.read(n) + + def readinto(self, b): + return self.f.readinto(b) + + def seek(self, offset): + return self.f.seek(offset) + + def write_to(self, offset, data): + if offset >= self.region_start and \ + offset + len(data) <= self.region_end: + self.f.seek(offset) + return self.f.write(data) + else: + raise OutOfRegionException() + + def fill_range(self, start, end, fill): + if start >= self.region_start and end <= self.region_end: + if start < end: + block = fill * 4096 + self.f.seek(start) + self.f.writelines(itertools.repeat(block, + (end - start) // 4096)) + self.f.write(block[:(end - start) % 4096]) + else: + raise OutOfRegionException() + + def move_range(self, offset_from, size, offset_to, fill): + if offset_from >= self.region_start and \ + offset_from + size <= self.region_end and \ + offset_to >= self.region_start and \ + offset_to + size <= self.region_end: + for i in range(0, size, 4096): + self.f.seek(offset_from + i, 0) + block = self.f.read(4096 if size - i >= 4096 else size - i) + self.f.seek(offset_from + i, 0) + self.f.write(fill * len(block)) + self.f.seek(offset_to + i, 0) + self.f.write(block) + else: + raise OutOfRegionException() + + def get_chunks_offsets(llut, me_start): chunk_count = unpack("<I", llut[0x04:0x08])[0] huffman_stream_end = sum(unpack("<II", llut[0x10:0x18])) + me_start @@ -50,19 +108,13 @@ def get_chunks_offsets(llut, me_start): return offsets -def fill_range(f, start, end, fill): - block = fill * 4096 - f.seek(start) - f.writelines(itertools.repeat(block, (end - start) // 4096)) - f.write(block[:(end - start) % 4096]) - - -def remove_modules(f, mod_headers, ftpr_offset): +def remove_modules(f, mod_headers, ftpr_offset, me_end): comp_str = ("Uncomp.", "Huffman", "LZMA") unremovable_huff_chunks = [] chunks_offsets = [] base = 0 chunk_size = 0 + end_addr = 0 for mod_header in mod_headers: name = mod_header[0x04:0x14].rstrip(b"\x00").decode("ascii") @@ -78,9 +130,11 @@ def remove_modules(f, mod_headers, ftpr_offset): .format(offset, offset + size)) if name in unremovable_modules: + end_addr = max(end_addr, offset + size) print("NOT removed, essential") else: - fill_range(f, offset, offset + size, b"\xff") + end = min(offset + size, me_end) + f.fill_range(offset, end, b"\xff") print("removed") elif comp_type == 0x01: @@ -93,10 +147,9 @@ def remove_modules(f, mod_headers, ftpr_offset): chunk_count = unpack("<I", llut[0x4:0x8])[0] base = unpack("<I", llut[0x8:0xc])[0] + 0x10000000 - huff_data_len = unpack("<I", llut[0x10:0x14])[0] chunk_size = unpack("<I", llut[0x30:0x34])[0] - llut += f.read(chunk_count * 4 + huff_data_len) + llut += f.read(chunk_count * 4) chunks_offsets = get_chunks_offsets(llut, me_start) else: sys.exit("Huffman modules found, but LLUT is not present") @@ -129,14 +182,20 @@ def remove_modules(f, mod_headers, ftpr_offset): for removable_chunk in removable_huff_chunks: if removable_chunk[1] > removable_chunk[0]: - fill_range(f, removable_chunk[0], removable_chunk[1], b"\xff") + end = min(removable_chunk[1], me_end) + f.fill_range(removable_chunk[0], end, b"\xff") + + end_addr = max(end_addr, + max(unremovable_huff_chunks, key=lambda x: x[1])[1]) + + return end_addr def check_partition_signature(f, offset): f.seek(offset) header = f.read(0x80) modulus = int(binascii.hexlify(f.read(0x100)[::-1]), 16) - public_exponent = int(binascii.hexlify(f.read(0x4)[::-1]), 16) + public_exponent = unpack("<I", f.read(4))[0] signature = int(binascii.hexlify(f.read(0x100)[::-1]), 16) header_len = unpack("<I", header[0x4:0x8])[0] * 4 @@ -152,144 +211,274 @@ def check_partition_signature(f, offset): return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME -if len(sys.argv) != 2 or sys.argv[1] == "-h" or sys.argv[1] == "--help": - print("Usage: \n" - " me_cleaner.py me_or_txe_image.bin\n" - "or\n" - " me_cleaner.py full_dump.bin") -else: - with open(sys.argv[1], "r+b") as f: - f.seek(0x10) - magic = f.read(4) - - if magic == b"$FPT": - print("ME/TXE image detected") - me_start = 0 - f.seek(0, 2) - me_end = f.tell() - - elif magic == b"\x5a\xa5\xf0\x0f": - print("Full image detected") - f.seek(0x14) - flmap0 = unpack("<I", f.read(4))[0] - nr = flmap0 >> 24 & 0x7 - frba = flmap0 >> 12 & 0xff0 - if nr >= 2: - f.seek(frba + 0x8) - flreg2 = unpack("<I", f.read(4))[0] - me_start = (flreg2 & 0x1fff) << 12 - me_end = flreg2 >> 4 & 0x1fff000 | 0xfff - - if me_start >= me_end: - sys.exit("The ME/TXE region in this image has been " - "disabled") - - f.seek(me_start + 0x10) - if f.read(4) != b"$FPT": - sys.exit("The ME/TXE region is corrupted or missing") - - print("The ME/TXE region goes from {:#x} to {:#x}" - .format(me_start, me_end)) - else: - sys.exit("This image does not contains a ME/TXE firmware " - "(NR = {})".format(nr)) +def relocate_partition(f, me_start, me_end, partition_header_offset, + new_offset, mod_headers): + + f.seek(partition_header_offset) + name = f.read(4).rstrip(b"\x00").decode("ascii") + f.seek(partition_header_offset + 0x8) + old_offset, partition_size = unpack("<II", f.read(0x8)) + old_offset += me_start + + llut_start = 0 + for mod_header in mod_headers: + if (unpack("<I", mod_header[0x50:0x54])[0] >> 4) & 7 == 0x01: + llut_start = unpack("<I", mod_header[0x38:0x3C])[0] + old_offset + break + + if llut_start != 0: + # Bytes 0x9:0xb of the LLUT (bytes 0x1:0x3 of the AddrBase) are added + # to the SpiBase (bytes 0xc:0x10 of the LLUT) to compute the final + # start of the LLUT. Since AddrBase is not modifiable, we can act only + # on SpiBase and here we compute the minimum allowed new_offset. + f.seek(llut_start + 0x9) + lut_start_corr = unpack("<H", f.read(2))[0] + new_offset = max(new_offset, + lut_start_corr + me_start - llut_start - 0x40 + + old_offset) + new_offset = ((new_offset + 0x1f) // 0x20) * 0x20 + + offset_diff = new_offset - old_offset + print("Relocating {} to {:#x} - {:#x}..." + .format(name, new_offset, new_offset + partition_size)) + + print(" Adjusting FPT entry...") + f.write_to(partition_header_offset + 0x8, + pack("<I", new_offset - me_start)) + + if llut_start != 0: + f.seek(llut_start) + if f.read(4) == b"LLUT": + print(" Adjusting LUT start offset...") + lut_offset = llut_start + offset_diff + 0x40 - \ + lut_start_corr - me_start + f.write_to(llut_start + 0x0c, pack("<I", lut_offset)) + + print(" Adjusting Huffman start offset...") + f.seek(llut_start + 0x14) + old_huff_offset = unpack("<I", f.read(4))[0] + f.write_to(llut_start + 0x14, + pack("<I", old_huff_offset + offset_diff)) + + print(" Adjusting chunks offsets...") + f.seek(llut_start + 0x4) + chunk_count = unpack("<I", f.read(4))[0] + f.seek(llut_start + 0x40) + chunks = bytearray(chunk_count * 4) + f.readinto(chunks) + for i in range(0, chunk_count * 4, 4): + if chunks[i + 3] != 0x80: + chunks[i:i + 3] = \ + pack("<I", unpack("<I", chunks[i:i + 3] + + b"\x00")[0] + offset_diff)[0:3] + f.write_to(llut_start + 0x40, chunks) + else: + sys.exit("Huffman modules present but no LLUT found!") + else: + print(" No Huffman modules found") + + print(" Moving data...") + partition_size = min(partition_size, me_end - old_offset) + f.move_range(old_offset, partition_size, new_offset, b"\xff") + + return new_offset + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description="Tool to remove as much code " + "as possible from Intel ME/TXE firmwares") + parser.add_argument("file", help="ME/TXE image or full dump") + parser.add_argument("-O", "--output", help="save the modified image in a " + "separate file, instead of modifying the original " + "file") + parser.add_argument("-r", "--relocate", help="relocate the FTPR partition " + "to the top of the ME region", action="store_true") + parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR " + "modules, even when possible", action="store_true") + parser.add_argument("-d", "--descriptor", help="remove the ME/TXE " + "Read/Write permissions to the other regions on the " + "flash from the Intel Flash Descriptor (requires a " + "full dump)", action="store_true") + parser.add_argument("-c", "--check", help="verify the integrity of the " + "fundamental parts of the firmware and exit", + action="store_true") + args = parser.parse_args() + + f = open(args.file, "rb" if args.check or args.output else "r+b") + f.seek(0x10) + magic = f.read(4) + + if magic == b"$FPT": + print("ME/TXE image detected") + me_start = 0 + f.seek(0, 2) + me_end = f.tell() + + if args.descriptor: + sys.exit("-d requires a full dump") + + elif magic == b"\x5a\xa5\xf0\x0f": + print("Full image detected") + f.seek(0x14) + flmap0, flmap1 = unpack("<II", f.read(8)) + nr = flmap0 >> 24 & 0x7 + frba = flmap0 >> 12 & 0xff0 + fmba = (flmap1 & 0xff) << 4 + if nr >= 2: + f.seek(frba) + flreg0, flreg1, flreg2 = unpack("<III", f.read(12)) + fd_start = (flreg0 & 0x1fff) << 12 + fd_end = flreg0 >> 4 & 0x1fff000 | 0xfff + 1 + me_start = (flreg2 & 0x1fff) << 12 + me_end = flreg2 >> 4 & 0x1fff000 | 0xfff + 1 + + if me_start >= me_end: + sys.exit("The ME/TXE region in this image has been disabled") + + f.seek(me_start + 0x10) + if f.read(4) != b"$FPT": + sys.exit("The ME/TXE region is corrupted or missing") + + print("The ME/TXE region goes from {:#x} to {:#x}" + .format(me_start, me_end)) else: - sys.exit("Unknown image") + sys.exit("This image does not contains a ME/TXE firmware NR = {})" + .format(nr)) + else: + sys.exit("Unknown image") - print("Found FPT header at {:#x}".format(me_start + 0x10)) + print("Found FPT header at {:#x}".format(me_start + 0x10)) - f.seek(me_start + 0x14) - entries = unpack("<I", f.read(4))[0] - print("Found {} partition(s)".format(entries)) + f.seek(me_start + 0x14) + entries = unpack("<I", f.read(4))[0] + print("Found {} partition(s)".format(entries)) - f.seek(me_start + 0x14) - header_len = unpack("B", f.read(1))[0] + f.seek(me_start + 0x14) + header_len = unpack("B", f.read(1))[0] - f.seek(me_start + 0x30) - partitions = f.read(entries * 0x20) + f.seek(me_start + 0x30) + partitions = f.read(entries * 0x20) - ftpr_header = b"" + ftpr_header = b"" - for i in range(entries): - if partitions[i * 0x20:(i * 0x20) + 4] == b"FTPR": - ftpr_header = partitions[i * 0x20:(i + 1) * 0x20] - break + for i in range(entries): + if partitions[i * 0x20:(i * 0x20) + 4] == b"FTPR": + ftpr_header = partitions[i * 0x20:(i + 1) * 0x20] + break - if ftpr_header == b"": - sys.exit("FTPR header not found, this image doesn't seem to be " - "valid") + if ftpr_header == b"": + sys.exit("FTPR header not found, this image doesn't seem to be valid") - ftpr_offset, ftpr_lenght = unpack("<II", ftpr_header[0x08:0x10]) - ftpr_offset += me_start - print("Found FTPR header: FTPR partition spans from {:#x} to {:#x}" - .format(ftpr_offset, ftpr_offset + ftpr_lenght)) - print("Removing extra partitions...") + ftpr_offset, ftpr_lenght = unpack("<II", ftpr_header[0x08:0x10]) + ftpr_offset += me_start + print("Found FTPR header: FTPR partition spans from {:#x} to {:#x}" + .format(ftpr_offset, ftpr_offset + ftpr_lenght)) + + f.seek(ftpr_offset) + if f.read(4) == b"$CPD": + me11 = True + num_entries = unpack("<I", f.read(4))[0] + ftpr_mn2_offset = 0x10 + num_entries * 0x18 + else: + me11 = False + ftpr_mn2_offset = 0 + + f.seek(ftpr_offset + ftpr_mn2_offset + 0x24) + version = unpack("<HHHH", f.read(0x08)) + print("ME/TXE firmware version {}" + .format('.'.join(str(i) for i in version))) + + if not args.check: + if args.output: + f.close() + shutil.copy(args.file, args.output) + f = open(args.output, "r+b") - fill_range(f, me_start + 0x30, ftpr_offset, b"\xff") - fill_range(f, ftpr_offset + ftpr_lenght, me_end, b"\xff") + mef = regionFile(f, me_start, me_end) + + print("Removing extra partitions...") + mef.fill_range(me_start + 0x30, ftpr_offset, b"\xff") + mef.fill_range(ftpr_offset + ftpr_lenght, me_end, b"\xff") print("Removing extra partition entries in FPT...") - f.seek(me_start + 0x30) - f.write(ftpr_header) - f.seek(me_start + 0x14) - f.write(pack("<I", 1)) + mef.write_to(me_start + 0x30, ftpr_header) + mef.write_to(me_start + 0x14, pack("<I", 1)) print("Removing EFFS presence flag...") - f.seek(me_start + 0x24) - flags = unpack("<I", f.read(4))[0] + mef.seek(me_start + 0x24) + flags = unpack("<I", mef.read(4))[0] flags &= ~(0x00000001) - f.seek(me_start + 0x24) - f.write(pack("<I", flags)) + mef.write_to(me_start + 0x24, pack("<I", flags)) - f.seek(me_start, 0) - header = bytearray(f.read(0x30)) + if args.descriptor: + print("Removing ME/TXE R/W access to the other flash regions...") + fdf = regionFile(f, fd_start, fd_end) + fdf.write_to(fmba + 0x4, pack("<I", 0x04040000)) + + if me11: + mef.seek(me_start + 0x10) + header = bytearray(mef.read(0x20)) + else: + mef.seek(me_start) + header = bytearray(mef.read(0x30)) checksum = (0x100 - (sum(header) - header[0x1b]) & 0xff) & 0xff print("Correcting checksum (0x{:02x})...".format(checksum)) # The checksum is just the two's complement of the sum of the first - # 0x30 bytes (except for 0x1b, the checksum itself). In other words, - # the sum of the first 0x30 bytes must be always 0x00. - f.seek(me_start + 0x1b) - f.write(pack("B", checksum)) - - f.seek(ftpr_offset) - if f.read(4) == b"$CPD": - me11 = True - num_entries = unpack("<I", f.read(4))[0] - f.seek(ftpr_offset + 0x10 + num_entries * 0x18 + 0x24) - else: - me11 = False - f.seek(ftpr_offset + 0x24) - - version = unpack("<HHHH", f.read(0x08)) - print("ME/TXE firmware version {}" - .format('.'.join(str(i) for i in version))) + # 0x30 bytes in ME < 11 or bytes 0x10:0x30 in ME >= 11 (except for + # 0x1b, the checksum itself). In other words, the sum of those bytes + # must be always 0x00. + mef.write_to(me_start + 0x1b, pack("B", checksum)) if not me11: print("Reading FTPR modules list...") - f.seek(ftpr_offset + 0x1c) - tag = f.read(4) + mef.seek(ftpr_offset + 0x1c) + tag = mef.read(4) if tag == b"$MN2": - f.seek(ftpr_offset + 0x20) - num_modules = unpack("<I", f.read(4))[0] - f.seek(ftpr_offset + 0x290) - data = f.read(0x84) + mef.seek(ftpr_offset + 0x20) + num_modules = unpack("<I", mef.read(4))[0] + mef.seek(ftpr_offset + 0x290) + data = mef.read(0x84) module_header_size = 0 if data[0x0:0x4] == b"$MME": - if data[0x60:0x64] == b"$MME": + if data[0x60:0x64] == b"$MME" or num_modules == 1: module_header_size = 0x60 elif data[0x80:0x84] == b"$MME": module_header_size = 0x80 if module_header_size != 0: - f.seek(ftpr_offset + 0x290) - mod_headers = [f.read(module_header_size) + mef.seek(ftpr_offset + 0x290) + mod_headers = [mef.read(module_header_size) for i in range(0, num_modules)] - if all(mod_h.startswith(b"$MME") for mod_h in mod_headers): - remove_modules(f, mod_headers, ftpr_offset) + if all(hdr.startswith(b"$MME") for hdr in mod_headers): + if args.keep_modules: + end_addr = ftpr_offset + ftpr_lenght + else: + end_addr = remove_modules(mef, mod_headers, + ftpr_offset, me_end) + + if args.relocate: + new_ftpr_offset = relocate_partition(mef, + me_start, me_end, + me_start + 0x30, + min_ftpr_offset + me_start, + mod_headers) + end_addr += new_ftpr_offset - ftpr_offset + ftpr_offset = new_ftpr_offset + + end_addr = (end_addr // 0x1000 + 1) * 0x1000 + end_addr += spared_blocks * 0x1000 + + print("The ME minimum size should be {0} bytes " + "({0:#x} bytes)".format(end_addr - me_start)) + + if me_start > 0: + print("The ME region can be reduced up to:\n" + " {:08x}:{:08x} me" + .format(me_start, end_addr - 1)) else: print("Found less modules than expected in the FTPR " "partition; skipping modules removal") @@ -302,12 +491,15 @@ else: else: print("Modules removal in ME v11 or greater is not yet supported") - sys.stdout.write("Checking FTPR RSA signature... ") - if check_partition_signature(f, ftpr_offset): - print("VALID") - else: - print("INVALID!!") - sys.exit("The FTPR partition signature is not valid. Is the input " - "ME/TXE image valid?") + sys.stdout.write("Checking FTPR RSA signature... ") + if check_partition_signature(f, ftpr_offset + ftpr_mn2_offset): + print("VALID") + else: + print("INVALID!!") + sys.exit("The FTPR partition signature is not valid. Is the input " + "ME/TXE image valid?") + + f.close() + if not args.check: print("Done! Good luck!")

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Patch set updated for coreboot: soc/intel/skylake: disable voltage margining
by Rizwan Qureshi 23 Feb '17

23 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18469 -gerrit commit 6143cc8033561e1080b359385d85551b30badb21 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 23 14:43:39 2017 +0530 soc/intel/skylake: disable voltage margining Voltage margining should be disabled for S0ix to work, use the UPD provided by FSP to enable/disable the voltage margining when SLP_S0# is asserted. Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/chip.h | 8 ++++++++ src/soc/intel/skylake/chip_fsp20.c | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 07cb8b1..f122a4c 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -332,6 +332,14 @@ struct soc_intel_skylake_config { * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s */ u8 PmConfigPwrBtnOverridePeriod; + + /* + * PCH Pm Slp S0 Voltage Margining Enable + * Indicates platform has support for VCCPrim_Core Voltage Margining + * in SLP_S0# asserted state. + */ + u8 PchPmSlpS0VmEnable; + /* * Reset Power Cycle Duration could be customized in the unit of second. * PCH HW default is 4 seconds, and range is 1~4 seconds. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 2b50d0c..fe3a9c5 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -220,6 +220,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + + /* Disable Voltage margining if S0ix is enabled */ + if (config->s0ix_enable) + params->PchPmSlpS0VmEnable = 0x0; + params->PchSirqEnable = config->SerialIrqConfigSirqEnable; params->PchSirqMode = config->SerialIrqConfigSirqMode;

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coreboot-gerrit February 2017