coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: lynxpoint bd82x6x: Enable PCI-to-PCI bridge
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit 57d4c30e22b5f35f9103240aa731798a21fe5a24 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 11 17:31:25 2017 +0200 lynxpoint bd82x6x: Enable PCI-to-PCI bridge Once the PCI command register is written the bridge forwards future IO and memory regions, as programmed in the respective base and limit registers, to the secondary PCI bus. It was previously argumented this is copy-paste and never known to be required for these more recent platforms: https://review.coreboot.org/#/c/2706/ Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/18330 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18330 for details. -gerrit

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Patch set updated for coreboot: google/gru: whitespace fix
by Patrick Georgi 23 Feb '17

23 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18475 -gerrit commit 7a96abe2814315b89e662c6a9524b126a00d23d6 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Feb 23 17:44:13 2017 +0100 google/gru: whitespace fix Follow up to https://review.coreboot.org/#/c/18460/ Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/gru/pwm_regulator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 426b989..b85f41f 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -58,7 +58,7 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) { voltage_min = PWM_DESIGN_VOLTAGE_MIN_OUTDATED; voltage_max = PWM_DESIGN_VOLTAGE_MAX_OUTDATED; - } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6){ + } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6) { voltage_min = kevin6_pwm_design_voltage[pwm][0]; voltage_max = kevin6_pwm_design_voltage[pwm][1]; }

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Patch set updated for coreboot: google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold
by Patrick Georgi 23 Feb '17

23 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18462 -gerrit commit c09180f275ae6566dae53a7689381f3aed457c93 Author: William wu <wulf(a)rock-chips.com> Date: Mon Jan 23 20:54:22 2017 +0800 google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold According to USB 2.0 Spec Table 7-7, the High-speed squelch detection threshold Min 100mV and Max 150mV, and we set USB 2.0 PHY0 and PHY1 squelch detection threshold to 150mV by default, so if the amplitude of differential voltage envelope is < 150 mV, the USB 2.0 PHYs envelope detector will indicate it as squelch. On Kevin board, if we connect usb device with Samsung U2 cable, we can see that the impedance of U2 cable is too big according to the eye-diagram test report, and this cause serious signal attenuation at the end of receiver, the amplitude of differential voltage falls below 150mV. This patch aims to reduce the PHY0 and PHY1 otg-ports squelch detection threshold to 125mV (host-ports still use 150mV by default), this is helpful to increase USB 2.0 PHY compatibility. BRANCH=gru BUG=chrome-os-partner:62320 TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into Type-C port, check if the USB device can be detected. Change-Id: Ia0a2d354781c2ac757938409490f7c4eecdffe61 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7d74311c25762668386061234df0562f84b7203e Original-Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8 Original-Signed-off-by: William wu <wulf(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/431015 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Inno Park <ih.yoo.park(a)samsung.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/mainboard.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 5926e49..bb9b6fc 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -260,15 +260,20 @@ static void setup_usb(void) RK_CLRSETBITS(0xffff, 0xa7)); /* - * Disable the pre-emphasize in eop state and chirp + * 1. Disable the pre-emphasize in eop state and chirp * state to avoid mis-trigger the disconnect detection * and also avoid high-speed handshake fail for PHY0 * and PHY1 consist of otg-port and host-port. + * + * 2. Configure PHY0 and PHY1 otg-ports squelch detection + * threshold to 125mV (default is 150mV). */ - write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3)); + write32(&rk3399_grf->usbphy0_ctrl[0], + RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13)); + write32(&rk3399_grf->usbphy1_ctrl[0], + RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13)); + write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(3 << 0)); + write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(3 << 0)); /* * ODT auto compensation bypass, and set max driver

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Patch set updated for coreboot: google/gru: update the pwm regulator
by Patrick Georgi 23 Feb '17

23 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18460 -gerrit commit 940af6a05600ad5ebc7cc84c1d9a61cce667858f Author: Caesar Wang <wxt(a)rock-chips.com> Date: Wed Jan 4 18:26:04 2017 +0800 google/gru: update the pwm regulator As David commented the "Bob and other follow-ons match Gru, Kevin should be the special case here", and update the calculations value for gru/bob board. From the actual tests, some regulator voltage than the actual set of less than 20mv on bob board. (e.g: little-cpus and Center-logic) Update the {min, max} regulator voltage for Bob board. Make sure we get the accurate voltage. BUG=chrome-os-partner:61497 BRANCH=none TEST=boot up Bob, measure the voltage for little cpu and C-logic. Change-Id: Iad881b41d67708776bfb681487cf8cec8518064e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 25e133815f49018e7496c75077b8559c207350a4 Original-Change-Id: I3098c742c7ec355c88f45bd1d93f878a7976a6b4 Original-Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao(a)asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/424523 Original-Reviewed-by: David Schneider <dnschneid(a)chromium.org> Original-Reviewed-by: Brian Norris <briannorris(a)chromium.org> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao(a)asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/430403 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/pwm_regulator.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index a81480a..426b989 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -28,29 +28,39 @@ * board design / resistors / capacitors / regulators but due to * clock dividers we actually get 3337. */ -#define PWM_PERIOD 3337 -#define PWM_DESIGN_VOLTAGE_MIN 8000 -#define PWM_DESIGN_VOLTAGE_MAX 15000 +#define PWM_PERIOD 3337 +#define PWM_DESIGN_VOLTAGE_MIN_OUTDATED 8000 +#define PWM_DESIGN_VOLTAGE_MAX_OUTDATED 15000 /* Later boards (Kevin rev6+, Gru rev2+) use different regulator ranges. */ -int pwm_design_voltage_later[][2] = { +int kevin6_pwm_design_voltage[][2] = { [PWM_REGULATOR_GPU] = {7858, 12177}, [PWM_REGULATOR_BIG] = {7987, 13022}, [PWM_REGULATOR_LIT] = {7991, 13037}, [PWM_REGULATOR_CENTERLOG] = {8001, 10497} }; +int pwm_design_voltage[][2] = { + [PWM_REGULATOR_GPU] = {7864, 12177}, + [PWM_REGULATOR_BIG] = {8001, 13022}, + [PWM_REGULATOR_LIT] = {7977, 13078}, + [PWM_REGULATOR_CENTERLOG] = {7994, 10499} +}; + void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) { int duty_ns, voltage_max, voltage_min; int voltage = millivolt * 10; /* for higer calculation accuracy */ - voltage_min = PWM_DESIGN_VOLTAGE_MIN; - voltage_max = PWM_DESIGN_VOLTAGE_MAX; - if (!(IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) && - !(IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) { - voltage_min = pwm_design_voltage_later[pwm][0]; - voltage_max = pwm_design_voltage_later[pwm][1]; + voltage_min = pwm_design_voltage[pwm][0]; + voltage_max = pwm_design_voltage[pwm][1]; + if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) || + (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) { + voltage_min = PWM_DESIGN_VOLTAGE_MIN_OUTDATED; + voltage_max = PWM_DESIGN_VOLTAGE_MAX_OUTDATED; + } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6){ + voltage_min = kevin6_pwm_design_voltage[pwm][0]; + voltage_max = kevin6_pwm_design_voltage[pwm][1]; } assert(voltage <= voltage_max && voltage >= voltage_min);

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Patch merged into coreboot/master: intel/minnow3: follow up with recent changes in master
by gerrit＠coreboot.org 23 Feb '17

23 Feb '17

the following patch was just integrated into master: commit a5c029f235d07707f2d6d9600c0ea3af55c88b81 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Feb 23 18:14:15 2017 +0100 intel/minnow3: follow up with recent changes in master minnow3 doesn't build right now due to API divergence on master branch. Follow up with recent changes. Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/18476 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18476 for details. -gerrit

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New patch to review for coreboot: intel/minnow3: follow up with recent changes in master
by Patrick Georgi 23 Feb '17

23 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18476 -gerrit commit cbae65fd8cb207b569c674ae8dfe54e7e5cd3f38 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Feb 23 18:14:15 2017 +0100 intel/minnow3: follow up with recent changes in master minnow3 doesn't build right now due to API divergence on master branch. Follow up with recent changes. Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/intel/minnow3/devicetree.cb | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index 2ccf277..b0c82e2 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -146,7 +146,7 @@ chip soc/intel/apollolake device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 chip drivers/i2c/da7219 - register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)" register "btn_cfg" = "50" register "mic_det_thr" = "500" register "jack_ins_deb" = "20" @@ -167,7 +167,7 @@ chip soc/intel/apollolake device pci 16.2 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" - register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)" device i2c 50 on end end end # - I2C 2 @@ -175,7 +175,7 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "reset_delay_ms" = "20" @@ -189,20 +189,17 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)" register "wake" = "GPE0_DW1_15" register "probed" = "1" device i2c 15 on end end end # - I2C 4 device pci 17.1 on - chip drivers/i2c/wacom - register "generic" = "{ - .hid = WCOM50C1_HID, - .cid = PNP0C50_CID, - .desc = WCOM_DT_DESC, - .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), - }" + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end

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Patch set updated for coreboot: nb/i945: Clean "Programming DLL Timings" function
by HAOUAS Elyes 23 Feb '17

23 Feb '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18472 -gerrit commit a3a30e9a05201b793a9225f8614a554abf33cc0f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Feb 23 13:14:44 2017 +0100 nb/i945: Clean "Programming DLL Timings" function As we drive both channels with the same speed, chen0dll and chen1dll are the same. Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a8bb5e7..8fada16 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1227,7 +1227,7 @@ static void sdram_enable_rcomp(void) static void sdram_program_dll_timings(struct sys_info *sysinfo) { - u32 chan0dll = 0, chan1dll = 0; + u32 channeldll = 0; int i; printk(BIOS_DEBUG, "Programming DLL Timings...\n"); @@ -1238,26 +1238,26 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) /* We drive both channels with the same speed */ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ + case 400: channeldll = 0x26262626; break; + case 533: channeldll = 0x22222222; break; + case 667: channeldll = 0x11111111; break; } } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ - case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ - case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ + case 400: channeldll = 0x33333333; break; + case 533: channeldll = 0x24242424; break; + case 667: channeldll = 0x25252525; break; } } for (i = 0; i < 4; i++) { - MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll; - MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = chan0dll & 0xff; - MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = chan1dll & 0xff; + MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; + MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } } }

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New patch to review for coreboot: google/gru: whitespace fix
by Patrick Georgi 23 Feb '17

23 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18475 -gerrit commit c94b4e7adbda92f962b7409395663baf5958b423 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Feb 23 17:44:13 2017 +0100 google/gru: whitespace fix Follow up to https://review.coreboot.org/#/c/18460/ Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/gru/pwm_regulator.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 426b989..b85f41f 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -58,7 +58,7 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) { voltage_min = PWM_DESIGN_VOLTAGE_MIN_OUTDATED; voltage_max = PWM_DESIGN_VOLTAGE_MAX_OUTDATED; - } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6){ + } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6) { voltage_min = kevin6_pwm_design_voltage[pwm][0]; voltage_max = kevin6_pwm_design_voltage[pwm][1]; }

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Patch set updated for coreboot: google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold
by Patrick Georgi 23 Feb '17

23 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18462 -gerrit commit 069e83c3e9fc268024b5bca78d017bbf4feb91e9 Author: William wu <wulf(a)rock-chips.com> Date: Mon Jan 23 20:54:22 2017 +0800 google/gru: Tuning USB 2.0 PHY0 and PHY1 squelch detection threshold According to USB 2.0 Spec Table 7-7, the High-speed squelch detection threshold Min 100mV and Max 150mV, and we set USB 2.0 PHY0 and PHY1 squelch detection threshold to 150mV by default, so if the amplitude of differential voltage envelope is < 150 mV, the USB 2.0 PHYs envelope detector will indicate it as squelch. On Kevin board, if we connect usb device with Samsung U2 cable, we can see that the impedance of U2 cable is too big according to the eye-diagram test report, and this cause serious signal attenuation at the end of receiver, the amplitude of differential voltage falls below 150mV. This patch aims to reduce the PHY0 and PHY1 otg-ports squelch detection threshold to 125mV (host-ports still use 150mV by default), this is helpful to increase USB 2.0 PHY compatibility. BRANCH=gru BUG=chrome-os-partner:62320 TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into Type-C port, check if the USB device can be detected. Change-Id: Ia0a2d354781c2ac757938409490f7c4eecdffe61 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7d74311c25762668386061234df0562f84b7203e Original-Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8 Original-Signed-off-by: William wu <wulf(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/431015 Original-Commit-Ready: Caesar Wang <wxt(a)rock-chips.com> Original-Tested-by: Inno Park <ih.yoo.park(a)samsung.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/mainboard.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 5926e49..bb9b6fc 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -260,15 +260,20 @@ static void setup_usb(void) RK_CLRSETBITS(0xffff, 0xa7)); /* - * Disable the pre-emphasize in eop state and chirp + * 1. Disable the pre-emphasize in eop state and chirp * state to avoid mis-trigger the disconnect detection * and also avoid high-speed handshake fail for PHY0 * and PHY1 consist of otg-port and host-port. + * + * 2. Configure PHY0 and PHY1 otg-ports squelch detection + * threshold to 125mV (default is 150mV). */ - write32(&rk3399_grf->usbphy0_ctrl[0], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy1_ctrl[0], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(0x3)); - write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(0x3)); + write32(&rk3399_grf->usbphy0_ctrl[0], + RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13)); + write32(&rk3399_grf->usbphy1_ctrl[0], + RK_CLRSETBITS(7 << 13 | 3 << 0, 6 << 13)); + write32(&rk3399_grf->usbphy0_ctrl[13], RK_CLRBITS(3 << 0)); + write32(&rk3399_grf->usbphy1_ctrl[13], RK_CLRBITS(3 << 0)); /* * ODT auto compensation bypass, and set max driver

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Patch set updated for coreboot: google/gru: update the pwm regulator
by Patrick Georgi 23 Feb '17

23 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18460 -gerrit commit a6f150f290e82b9ecb2d29ce8a317a8743ff23c1 Author: Caesar Wang <wxt(a)rock-chips.com> Date: Wed Jan 4 18:26:04 2017 +0800 google/gru: update the pwm regulator As David commented the "Bob and other follow-ons match Gru, Kevin should be the special case here", and update the calculations value for gru/bob board. From the actual tests, some regulator voltage than the actual set of less than 20mv on bob board. (e.g: little-cpus and Center-logic) Update the {min, max} regulator voltage for Bob board. Make sure we get the accurate voltage. BUG=chrome-os-partner:61497 BRANCH=none TEST=boot up Bob, measure the voltage for little cpu and C-logic. Change-Id: Iad881b41d67708776bfb681487cf8cec8518064e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 25e133815f49018e7496c75077b8559c207350a4 Original-Change-Id: I3098c742c7ec355c88f45bd1d93f878a7976a6b4 Original-Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao(a)asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/424523 Original-Reviewed-by: David Schneider <dnschneid(a)chromium.org> Original-Reviewed-by: Brian Norris <briannorris(a)chromium.org> Original-Signed-off-by: Shasha Zhao <Sarah_Zhao(a)asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/430403 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/pwm_regulator.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index a81480a..426b989 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -28,29 +28,39 @@ * board design / resistors / capacitors / regulators but due to * clock dividers we actually get 3337. */ -#define PWM_PERIOD 3337 -#define PWM_DESIGN_VOLTAGE_MIN 8000 -#define PWM_DESIGN_VOLTAGE_MAX 15000 +#define PWM_PERIOD 3337 +#define PWM_DESIGN_VOLTAGE_MIN_OUTDATED 8000 +#define PWM_DESIGN_VOLTAGE_MAX_OUTDATED 15000 /* Later boards (Kevin rev6+, Gru rev2+) use different regulator ranges. */ -int pwm_design_voltage_later[][2] = { +int kevin6_pwm_design_voltage[][2] = { [PWM_REGULATOR_GPU] = {7858, 12177}, [PWM_REGULATOR_BIG] = {7987, 13022}, [PWM_REGULATOR_LIT] = {7991, 13037}, [PWM_REGULATOR_CENTERLOG] = {8001, 10497} }; +int pwm_design_voltage[][2] = { + [PWM_REGULATOR_GPU] = {7864, 12177}, + [PWM_REGULATOR_BIG] = {8001, 13022}, + [PWM_REGULATOR_LIT] = {7977, 13078}, + [PWM_REGULATOR_CENTERLOG] = {7994, 10499} +}; + void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) { int duty_ns, voltage_max, voltage_min; int voltage = millivolt * 10; /* for higer calculation accuracy */ - voltage_min = PWM_DESIGN_VOLTAGE_MIN; - voltage_max = PWM_DESIGN_VOLTAGE_MAX; - if (!(IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) && - !(IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) { - voltage_min = pwm_design_voltage_later[pwm][0]; - voltage_max = pwm_design_voltage_later[pwm][1]; + voltage_min = pwm_design_voltage[pwm][0]; + voltage_max = pwm_design_voltage[pwm][1]; + if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) || + (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) { + voltage_min = PWM_DESIGN_VOLTAGE_MIN_OUTDATED; + voltage_max = PWM_DESIGN_VOLTAGE_MAX_OUTDATED; + } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6){ + voltage_min = kevin6_pwm_design_voltage[pwm][0]; + voltage_max = kevin6_pwm_design_voltage[pwm][1]; } assert(voltage <= voltage_max && voltage >= voltage_min);

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coreboot-gerrit February 2017