coreboot-gerrit February 2017

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Patch set updated for coreboot: ec/lenovo/h8: Fix mute LEDs
by Nicola Corna 24 Feb '17

24 Feb '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18329 -gerrit commit e59aec02b01baef82038c35ac8518c61e6f073f7 Author: Nicola Corna <nicola(a)corna.info> Date: Sat Feb 11 14:52:24 2017 +0100 ec/lenovo/h8: Fix mute LEDs thinkpad_acpi expects a SSMS method to turn on/off the mute LED and a MMTS method to turn on/off the microphone mute LED. With these methods implemented the driver can correctly sync the LEDs with the corresponding statuses. There seems to be two different bits to mute the audio in the Lenovo H8 EC: * AMUT, used internally (for example to disable the audio before entering S3). * ALMT, controllable by the OS, which also toggles the mute LED (if present). Tested on a X220T and on a X201. Change-Id: I578f95f9619a53fd35f8a8bfe5564aeb6c789212 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/ec/lenovo/h8/acpi/ec.asl | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 497dde4..b8350ad 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -39,8 +39,11 @@ Device(EC) DKR2, 1, /* Dock register 2 */ Offset (0x2a), EVNT, 8, /* write will trigger EC event */ + Offset (0x30), + , 6, + ALMT, 1, /* Audio Mute + LED */ Offset (0x3a), - AMUT, 1, /* Audio Mute */ + AMUT, 1, /* Audio Mute (internal use) */ , 3, BTEB, 1, WLEB, 1, @@ -362,6 +365,23 @@ Device(EC) { Return (TBSW << 3) } + /* Mute audio */ + Method (SSMS, 1, NotSerialized) + { + Store(Arg0, ALMT) + } + /* Control mute microphone LED */ + Method (MMTS, 1, NotSerialized) + { + If (Arg0) + { + TLED(0x8E) + } + Else + { + TLED(0x0E) + } + } /* Version */ Method (MHKV, 0, NotSerialized) {

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Patch set updated for coreboot: ec/lenovo/h8: Fix mute LEDs
by Nicola Corna 24 Feb '17

24 Feb '17

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18329 -gerrit commit 1120053ef34cfd81015c5de5ace676f08e8f9657 Author: Nicola Corna <nicola(a)corna.info> Date: Sat Feb 11 14:52:24 2017 +0100 ec/lenovo/h8: Fix mute LEDs thinkpad_acpi expects a SSMS method to turn on/off the mute LED and a MMTS method to turn on/off the microphone mute LED. With these methods implemented the driver can correctly sync the LEDs LEDs with the corresponding statuses. There seems to be two different bits to mute the audio in the Lenovo H8 EC: * AMUT, used internally (for example to disable the audio before entering S3). * ALMT, controllable by the OS, which also toggles the mute LED (if present). Tested on a X220T and on a X201. Change-Id: I578f95f9619a53fd35f8a8bfe5564aeb6c789212 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/ec/lenovo/h8/acpi/ec.asl | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 497dde4..b8350ad 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -39,8 +39,11 @@ Device(EC) DKR2, 1, /* Dock register 2 */ Offset (0x2a), EVNT, 8, /* write will trigger EC event */ + Offset (0x30), + , 6, + ALMT, 1, /* Audio Mute + LED */ Offset (0x3a), - AMUT, 1, /* Audio Mute */ + AMUT, 1, /* Audio Mute (internal use) */ , 3, BTEB, 1, WLEB, 1, @@ -362,6 +365,23 @@ Device(EC) { Return (TBSW << 3) } + /* Mute audio */ + Method (SSMS, 1, NotSerialized) + { + Store(Arg0, ALMT) + } + /* Control mute microphone LED */ + Method (MMTS, 1, NotSerialized) + { + If (Arg0) + { + TLED(0x8E) + } + Else + { + TLED(0x0E) + } + } /* Version */ Method (MHKV, 0, NotSerialized) {

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New patch to review for coreboot: autoport: add "-d" option to ectool to dump registers
by Iru Cai 24 Feb '17

24 Feb '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18481 -gerrit commit 90702af1b4c60f7d64bf7edc8442abf009db5426 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Fri Feb 24 15:19:25 2017 +0800 autoport: add "-d" option to ectool to dump registers Change-Id: I7de37a026a0899c2d07ea17c9377c8d2283450ab Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- util/autoport/log_maker.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go index 7c8240e..86fc9b2 100644 --- a/util/autoport/log_maker.go +++ b/util/autoport/log_maker.go @@ -93,7 +93,7 @@ func MakeLogs(outDir string) { } RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", inteltoolArgs) - RunAndSave(outDir+"/ectool.log", "../ectool/ectool") + RunAndSave(outDir+"/ectool.log", "../ectool/ectool", "-d") SysDir := "/sys/class/sound/card0/" files, _ := ioutil.ReadDir(SysDir)

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New patch to review for coreboot: superiotool: add SMSC KBC1126
by Iru Cai 24 Feb '17

24 Feb '17

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18480 -gerrit commit 0c9ba9f488c30bbebdb6240f2e949b5a2a525ada Author: Iru Cai <mytbk920423(a)gmail.com> Date: Fri Feb 24 15:35:55 2017 +0800 superiotool: add SMSC KBC1126 Device ID is read from HP Elitebook 2760p. LDNs are from superio/smsc/kbc1100/kbc1100.h, and the register indices come from the existing code in smsc.c. Keyboard and EC registers can be seen from superio/sms/kbc1100/early_init.c. COM1 registers can be seen from the DSDT dump of HP Elitebook 2760p running OEM firmware. Change-Id: Id172ae42411a6d42a4ae7c7f30f96aeda3e6c384 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- util/superiotool/smsc.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index 15ba131..1f30959 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -68,6 +68,26 @@ static const struct superio_registers reg_table[] = { {0x03, "FDC37C93xFR", { /* FIXME: There's another 0x03 but found on port 0x0d/0x0e! */ {EOT}}}, + {0x07, "KBC1126", { + {0x1, "Power management (PM1)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x4, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x7, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x8, "Embedded controller (EC)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x62,EOT}}, + {0x9, "Mailbox", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0xa, "LPC/8051 addressable GPIO (LGPIO)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {EOT}}}, {0x0a, "FDC37N971", { {NOLDN, NULL, {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,

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New patch to review for coreboot: mainboard/intel/leafhill: Clean up
by Andrey Petrov 24 Feb '17

24 Feb '17

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18479 -gerrit commit ebe0b489814916008a75e3aec422f5248a459fb7 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 23 14:10:11 2017 -0800 mainboard/intel/leafhill: Clean up This patch tries to clean the code by: o removing duplication of LPC GPIO pads o removing incorrect definitions from devicetree o removing irrelevant entries from FMD file Also adds vital defaults in Kconfig so it is possible to build an image. Change-Id: Id9913f3b053189166392271152ce5300d82a7de8 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/leafhill/Kconfig | 62 +++++- src/mainboard/intel/leafhill/Makefile.inc | 1 + src/mainboard/intel/leafhill/brd_gpio.h | 15 +- src/mainboard/intel/leafhill/devicetree.cb | 259 ++++-------------------- src/mainboard/intel/leafhill/leafhill.fmd | 40 ---- src/mainboard/intel/leafhill/leafhill.fmd.16384 | 14 ++ src/mainboard/intel/leafhill/leafhill.fmd.8192 | 14 ++ 7 files changed, 132 insertions(+), 273 deletions(-) diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig index ddef0e7..2ec2e03 100644 --- a/src/mainboard/intel/leafhill/Kconfig +++ b/src/mainboard/intel/leafhill/Kconfig @@ -4,11 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_16384 - select DRIVERS_I2C_HID select HAVE_ACPI_TABLES -# select HAVE_INTEL_FIRMWARE -# select HAVE_ME_BIN -# select LOCK_MANAGEMENT_ENGINE config MAINBOARD_DIR string @@ -22,4 +18,62 @@ config MAINBOARD_PART_NUMBER string default "Leafhill" +config MAINBOARD_VENDOR + string + default "Intel" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/leafhill.fmd.$(CONFIG_COREBOOT_ROMSIZE_KB)" + +config UART_FOR_CONSOLE + int + default 2 + +config NEED_IFWI + def_bool y + +config IFWI_FMAP_NAME + string + default "IFWI" + +config IFWI_FILE_NAME + string + default "3rdparty/blobs/mainboard/intel/leafhill/fitimage.bin" + +config HAVE_IFWI + def_bool y + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/intel/leafhill/descriptor.bin" + +config HAVE_IFD_BIN + def_bool y + +config SOC_UART_DEBUG + def_bool y + +config FSP_M_FILE + string + default "3rdparty/blobs/mainboard/intel/leafhill/FSP-M.Fv" + +config FSP_S_FILE + string + default "3rdparty/blobs/mainboard/intel/leafhill/FSP-S.Fv" + +config PLATFORM_USES_FSP2_0 + def_bool y + +config ADD_FSP_BINARIES + def_bool y + +config FSP_S_CBFS + string + default "fsps.bin" + +config FSP_M_CBFS + string + default "fspm.bin" + endif # BOARD_INTEL_LEAFHILL diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc index 9e3e892..c3077e7 100644 --- a/src/mainboard/intel/leafhill/Makefile.inc +++ b/src/mainboard/intel/leafhill/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += bootblock.c +romstage-y += romstage.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h index 33b839b..18d130b 100644 --- a/src/mainboard/intel/leafhill/brd_gpio.h +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * Copyright (C) 2017 Intel Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,8 +15,6 @@ #include <soc/gpio.h> -#if ENV_ROMSTAGE - static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ @@ -48,15 +46,4 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), }; - -#endif diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index b0c82e2..2a284d2 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -1,227 +1,56 @@ chip soc/intel/apollolake - device cpu_cluster 0 on - device lapic 0 on end - end - - register "pcie_rp0_clkreq_pin" = "0" # wifi/bt - # Disable unused clkreq of PCIe root ports + register "pcie_rp0_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" - # GPIO for PERST_0 - # If the Board has PERST_0 signal, assign the GPIO - # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF - register "prt0_gpio" = "GPIO_122" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [14:8] steps of delay for HS400, each 125ps. - # [6:0] steps of delay for SDR104/HS200, each 125ps. - register "emmc_tx_data_cntl1" = "0x0C16" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_tx_data_cntl2" = "0x28162828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-22.3. - # [30:24] steps of delay for SDR50, each 125ps. - # [22:16] steps of delay for DDR50, each 125ps. - # [14:8] steps of delay for SDR25/HS50, each 125ps. - # [6:0] steps of delay for SDR12, each 125ps. - register "emmc_rx_cmd_data_cntl1" = "0x00181717" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-22.3. - # [17:16] stands for Rx Clock before Output Buffer - # [14:8] steps of delay for Auto Tuning Mode, each 125ps. - # [6:0] steps of delay for HS200, each 125ps. - register "emmc_rx_cmd_data_cntl2" = "0x10008" - - # Enable DPTF - register "dptf_enable" = "1" - - # PL1 override 12000 mW: the energy calculation is wrong with the - # current VR solution. Experiments show that SoC TDP max (6W) can - # be reached when RAPL PL1 is set to 12W. - register "tdp_pl1_override_mw" = "12000" - # Set RAPL PL2 to 15W. - register "tdp_pl2_override_mw" = "15000" - - # Enable Audio Clock and Power gating - register "hdaudio_clk_gate_enable" = "1" - register "hdaudio_pwr_gate_enable" = "1" - register "hdaudio_bios_config_lockdown" = "1" - - # Enable lpss s0ix - register "lpss_s0ix_enable" = "1" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route, i.e., if this route changes then the affected GPE - # offset bits also need to be changed. This sets the PMC register - # GPE_CFG fields. - register "gpe0_dw1" = "PMC_GPE_N_31_0" - register "gpe0_dw2" = "PMC_GPE_N_63_32" - register "gpe0_dw3" = "PMC_GPE_SW_31_0" - - # Enable I2C0 for audio codec at 400kHz - register "i2c[0]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 104, - .fall_time_ns = 52, - }" - - # Enable I2C2 bus early for TPM at 400kHz - register "i2c[2]" = "{ - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 57, - .fall_time_ns = 28, - }" - - # touchscreen at 400kHz - register "i2c[3]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 76, - .fall_time_ns = 164, - }" - - # trackpad at 400kHz - register "i2c[4]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 114, - .fall_time_ns = 164, - }" - - # digitizer at 400kHz - register "i2c[5]" = "{ - .speed = I2C_SPEED_FAST, - .rise_time_ns = 152, - .fall_time_ns = 30, - }" - - # Minimum SLP S3 assertion width 28ms. - register "slp_s3_assertion_width_usecs" = "28000" + device cpu_cluster 0 on + device lapic 0 on end + end device domain 0 on - device pci 00.0 on end # - Host Bridge - device pci 00.1 on end # - DPTF - device pci 00.2 on end # - NPK - device pci 02.0 on end # - Gen - device pci 03.0 on end # - Iunit - device pci 0d.0 on end # - P2SB - device pci 0d.1 on end # - PMC - device pci 0d.2 on end # - SPI - device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on # - Audio - chip drivers/generic/max98357a - register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" - register "sdmode_delay" = "5" - device generic 0 on end - end - end - device pci 11.0 off end # - ISH - device pci 12.0 off end # - SATA - device pci 13.0 off end # - Root Port 2 - PCIe-A 0 - device pci 13.1 off end # - Root Port 3 - PCIe-A 1 - device pci 13.2 off end # - Root Port 4 - PCIe-A 2 - device pci 13.3 off end # - Root Port 5 - PCIe-A 3 - device pci 14.0 on - chip drivers/intel/wifi - register "wake" = "GPE0_DW3_00" - device pci 00.0 on end - end - end # - Root Port 0 - PCIe-B 0 - Wifi - device pci 14.1 off end # - Root Port 1 - PCIe-B 1 - device pci 15.0 on end # - XHCI - device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - chip drivers/i2c/da7219 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end - device pci 16.1 on end # - I2C 1 - device pci 16.2 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)" - device i2c 50 on end - end - end # - I2C 2 - device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" - register "reset_delay_ms" = "20" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" - register "enable_delay_ms" = "1" - register "has_power_resource" = "1" - device i2c 10 on end - end - end # - I2C 3 - device pci 17.0 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)" - register "wake" = "GPE0_DW1_15" - register "probed" = "1" - device i2c 15 on end - end - end # - I2C 4 - device pci 17.1 on - chip drivers/i2c/hid - register "generic.hid" = ""WCOM50C1"" - register "generic.desc" = ""WCOM Digitizer"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)" - register "hid_desc_reg_offset" = "0x1" - device i2c 0x9 on end - end - end # - I2C 5 - device pci 17.2 off end # - I2C 6 - device pci 17.3 off end # - I2C 7 - device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 - device pci 18.3 off end # - UART 3 - device pci 19.0 on end # - SPI 0 - device pci 19.1 off end # - SPI 1 - device pci 19.2 off end # - SPI 2 - device pci 1a.0 on end # - PWM - device pci 1b.0 on end # - SDCARD - device pci 1c.0 on end # - eMMC - device pci 1e.0 off end # - SDIO - device pci 1f.0 on # - LPC - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end - device pci 1f.1 on end # - SMBUS + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS end end diff --git a/src/mainboard/intel/leafhill/leafhill.fmd b/src/mainboard/intel/leafhill/leafhill.fmd deleted file mode 100644 index 3da8467..0000000 --- a/src/mainboard/intel/leafhill/leafhill.fmd +++ /dev/null @@ -1,40 +0,0 @@ -FLASH 16M { - WP_RO@0x0 0x400000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x1bb000 - RO_UNUSED@0x1bc000 0x40000 - } - } - MISC_RW@0x400000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 - } - RW_ELOG@0x21000 0x3000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 - } - RW_LEGACY(CBFS)@0xd30000 0x200000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 - # Currently, it is required that the BIOS region be a multiple of 8KiB. - # This is required so that the recovery mechanism can find SIGN_CSE - # region aligned to 4K at the center of BIOS region. Since the - # descriptor at the beginning uses 4K and BIOS starts at an offset of - # 4K, a hole of 4K is created towards the end of the flash to compensate - # for the size requirement of BIOS region. - # FIT tool thus creates descriptor with following regions: - # Descriptor --> 0 to 4K - # BIOS --> 4K to 0xf7f000 - # Device ext --> 0xf7f000 to 0xfff000 - UNUSED_HOLE@0xfff000 0x1000 -} diff --git a/src/mainboard/intel/leafhill/leafhill.fmd.16384 b/src/mainboard/intel/leafhill/leafhill.fmd.16384 new file mode 100644 index 0000000..a91ba9a --- /dev/null +++ b/src/mainboard/intel/leafhill/leafhill.fmd.16384 @@ -0,0 +1,14 @@ +FLASH 16M { + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x2ff000 + FMAP@0x300000 0x800 + COREBOOT(CBFS)@0x300800 0xc1d800 + UNIFIED_MRC_CACHE@0xf1e000 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + BIOS_UNUSABLE@0xf3f000 0x40000 + DEVICE_EXTENSION@0xf7f000 0x7f000 + UNUSED_HOLE@0xfff000 0x1000 +} diff --git a/src/mainboard/intel/leafhill/leafhill.fmd.8192 b/src/mainboard/intel/leafhill/leafhill.fmd.8192 new file mode 100644 index 0000000..3f4d21b --- /dev/null +++ b/src/mainboard/intel/leafhill/leafhill.fmd.8192 @@ -0,0 +1,14 @@ +FLASH 8M { + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x300000 + FMAP@0x321000 0x800 + COREBOOT(CBFS)@0x321800 0x300000 + UNIFIED_MRC_CACHE@0x621800 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + BIOS_UNUSABLE@0x740000 0x40000 + DEVICE_EXTENSION@0x780000 0x7f000 + UNUSED_HOLE@0x7ff000 0x1000 +}

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Patch set updated for coreboot: [Needs test] i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs
by HAOUAS Elyes 24 Feb '17

24 Feb '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18387 -gerrit commit 33cc2ca8bf134a465f05ea3f753c57d68f6a8b84 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Feb 18 14:22:33 2017 +0100 [Needs test] i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs Change-Id: Ib1f999447b37a1524d589552ea2eec640c2a2c7e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 37 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cc227cc..214bebd 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -857,33 +857,30 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) static void sdram_program_dram_width(struct sys_info * sysinfo) { u16 c0dramw = 0, c1dramw = 0; - int idx; + int i, idx; if (sysinfo->dual_channel) idx = 2; else idx = 1; - switch (sysinfo->dimm[0]) { - case 0: c0dramw = 0x0000; break; /* x16DS */ - case 1: c0dramw = 0x0001; break; /* x8DS */ - case 2: c0dramw = 0x0000; break; /* x16SS */ - case 3: c0dramw = 0x0005; break; /* x8DDS */ - case 4: c0dramw = 0x0000; break; /* NC */ - } - - switch (sysinfo->dimm[idx]) { - case 0: c1dramw = 0x0000; break; /* x16DS */ - case 1: c1dramw = 0x0010; break; /* x8DS */ - case 2: c1dramw = 0x0000; break; /* x16SS */ - case 3: c1dramw = 0x0050; break; /* x8DDS */ - case 4: c1dramw = 0x0000; break; /* NC */ + for (i = 0; i < DIMM_SOCKETS; i++) { /* Channel A */ + switch (sysinfo->dimm[i]) { + case SYSINFO_DIMM_X16DS: c0dramw |= (0x0000) << 4*(i%2); break; + case SYSINFO_DIMM_X8DS: c0dramw |= (0x0001) << 4*(i%2); break; + case SYSINFO_DIMM_X16SS: c0dramw |= (0x0000) << 4*(i%2); break; + case SYSINFO_DIMM_X8DDS: c0dramw |= (0x0005) << 4*(i%2); break; + case SYSINFO_DIMM_NOT_POPULATED: c0dramw |= (0x0000) << 4*(i%2); break; + } } - - if ( !sdram_capabilities_dual_channel() ) { - /* Single Channel */ - c0dramw |= c1dramw; - c1dramw = 0; + for (i = DIMM_SOCKETS; i < idx * DIMM_SOCKETS; i++) { /* Channel B */ + switch (sysinfo->dimm[i]) { + case SYSINFO_DIMM_X16DS: c1dramw |= (0x0000) << 4*(i%2); break; + case SYSINFO_DIMM_X8DS: c1dramw |= (0x0001) << 4*(i%2); break; + case SYSINFO_DIMM_X16SS: c1dramw |= (0x0000) << 4*(i%2); break; + case SYSINFO_DIMM_X8DDS: c1dramw |= (0x0005) << 4*(i%2); break; + case SYSINFO_DIMM_NOT_POPULATED: c1dramw |= (0x0000) << 4*(i%2); break; + } } MCHBAR16(C0DRAMW) = c0dramw;

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Patch set updated for coreboot: nb/i945: Clean "Programming DLL Timings" function
by HAOUAS Elyes 24 Feb '17

24 Feb '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18472 -gerrit commit 869f29e6f82102095519f4f969d954ef7c21bb30 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Feb 23 13:14:44 2017 +0100 nb/i945: Clean "Programming DLL Timings" function As we drive both channels with the same speed, chan0dll and chan1dll are the same. Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a8bb5e7..8fada16 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1227,7 +1227,7 @@ static void sdram_enable_rcomp(void) static void sdram_program_dll_timings(struct sys_info *sysinfo) { - u32 chan0dll = 0, chan1dll = 0; + u32 channeldll = 0; int i; printk(BIOS_DEBUG, "Programming DLL Timings...\n"); @@ -1238,26 +1238,26 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) /* We drive both channels with the same speed */ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ + case 400: channeldll = 0x26262626; break; + case 533: channeldll = 0x22222222; break; + case 667: channeldll = 0x11111111; break; } } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ - case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ - case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ + case 400: channeldll = 0x33333333; break; + case 533: channeldll = 0x24242424; break; + case 667: channeldll = 0x25252525; break; } } for (i = 0; i < 4; i++) { - MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll; - MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = chan0dll & 0xff; - MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = chan1dll & 0xff; + MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; + MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } } }

1 0

Patch merged into coreboot/master: src/arch/x86: Remove non-ascii characters
by gerrit＠coreboot.org 24 Feb '17

24 Feb '17

the following patch was just integrated into master: commit cb69fbaa870a105d2585d2b76a82cf2a16b002b5 Author: Martin Roth <martinroth(a)google.com> Date: Wed Feb 15 16:37:29 2017 -0700 src/arch/x86: Remove non-ascii characters Change-Id: Ie0d35c693ed5cc3e890279eda289bd6d4416d9e6 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/18376 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/18376 for details. -gerrit

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Patch merged into coreboot/master: payloads/external/GRUB2: Add "git revision" to the GRUB2 version menu
by gerrit＠coreboot.org 24 Feb '17

24 Feb '17

the following patch was just integrated into master: commit 08cf195f4c1165412fd2286d19c20c08a2a4300e Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Sep 14 14:41:36 2016 +0200 payloads/external/GRUB2: Add "git revision" to the GRUB2 version menu This change is based on the following commit: 3aa91dc payloads/seabios: Add "git revision" to the SeaBIOS version menu Change-Id: I9987e3673e70b5cb20173d1ddff6060f42a5374a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: https://review.coreboot.org/18352 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18352 for details. -gerrit

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Patch merged into coreboot/master: ec/lenovo/h8: Guard against EC bugs in the battery status logic.
by gerrit＠coreboot.org 24 Feb '17

24 Feb '17

the following patch was just integrated into master: commit 9b798d7904f50b8ad83fe43442a5a3da85789bdd Author: Tobias Diedrich <ranma+openocd(a)tdiedrich.de> Date: Sun Feb 12 13:35:37 2017 +0100 ec/lenovo/h8: Guard against EC bugs in the battery status logic. On my Thinkpad with an H8-compatible ENE KB9012 EC (GDHT92WW 1.52), when the battery is nearly full and we switch from battery to AC by plugging in the cable, the current rate will not drop to 0 immediately, but the discharging state is cleared immediately. This leads to the code trying to process an invalid rate value >0x8000, leading to a displayed rate of >1000W. This patch changes the logic to deal with these corner cases. Change-Id: Ideb588d00757f259792e5ae97729e371b63a096c Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Reviewed-on: https://review.coreboot.org/18349 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18349 for details. -gerrit

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coreboot-gerrit February 2017