coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: cpu/amd/pi: Allow stoney to use cbmem in heapmanager
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18431 -gerrit commit bf3344b4d3306a8cc984a13cbb8514767242f4ac Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 29 16:40:22 2017 -0700 cpu/amd/pi: Allow stoney to use cbmem in heapmanager Allocate memory for AGESA's heap from cbmem. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit d1f3191d8213eba431299f3cdcd91dc2ade7ca59) Change-Id: I1eff2fddcec13a53618eeb553bace3b0eca16e95 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/heapmanager.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index 7fc8fb8..efbd9e7 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -37,7 +37,9 @@ void EmptyHeap(void) memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); } -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) && !defined(__PRE_RAM__) +#if (IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) \ + || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00670F00)) \ + && !defined(__PRE_RAM__) #define AGESA_RUNTIME_SIZE 4096 @@ -83,7 +85,9 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) && !defined(__PRE_RAM__) +#if (IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) \ + || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00670F00)) \ + && !defined(__PRE_RAM__) /* if the allocation is for runtime use simple CBMEM data */ if (Data == HEAP_CALLOUT_RUNTIME) return alloc_cbmem(AllocParams);

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Patch set updated for coreboot: amd/pi/stoney: Simplify UMA calculations
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18430 -gerrit commit fc98760ad4f8961295f024b22c1ad415647611df Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Jan 17 18:27:18 2017 -0500 amd/pi/stoney: Simplify UMA calculations Use the new top of memory functions to ease the UMA base and size. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 781b329effc5242c05991aea438c3e2c80244b0f) Change-Id: Ic83fa766dc4aa912612f0073b7027bf868d2d989 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00670F00/northbridge.c | 43 +++++---------------------- 1 file changed, 7 insertions(+), 36 deletions(-) diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index c21d030..69478d6 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -37,6 +37,7 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include "northbridge.h" +#include "memmap.h" #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> @@ -696,50 +697,17 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB_SHIFT 20 -#define ONE_GB_SHIFT 30 - static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint64_t topmem = bsp_topmem(); - uint64_t topmem2 = bsp_topmem2(); - uint32_t sysmem_mb, sysmem_gb; - - /* refer to UMA_AUTO size computation in Family15h BKDG. */ - /* Please reference MemNGetUmaSizeML() */ - /* - * Total system memory UMASize - * >= 6G 1024M - * >= 4G 512M - * >= 2G 256M - * < 2G 128M - */ - - sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; // Ignore 16MB allocated for C6 when finding UMA size - sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0; - sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT); - printk(BIOS_SPEW, "%s: system memory size %luGB, topmem2 size %lluMB, topmem size %lluMB\n", - __func__, (unsigned long)sysmem_gb, (topmem2 >> ONE_MB_SHIFT), (topmem >> ONE_MB_SHIFT)); - if (sysmem_gb >= 6) { - uma_memory_size = 1024 << ONE_MB_SHIFT; - } else if (sysmem_gb >= 4) { - uma_memory_size = 512 << ONE_MB_SHIFT; - } else if (sysmem_gb >= 2) { - uma_memory_size = 256 << ONE_MB_SHIFT; - } else { - uma_memory_size = 128 << ONE_MB_SHIFT; - } - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ + uma_memory_size = uma_size_auto(); + uma_memory_base = uma_base_auto(); printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } - static void domain_set_resources(device_t dev) { unsigned long mmio_basek; @@ -751,7 +719,6 @@ static void domain_set_resources(device_t dev) struct hw_mem_hole_info mem_hole; u32 reset_memhole = 1; #endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -838,12 +805,16 @@ static void domain_set_resources(device_t dev) ramtop = limitk * 1024; } +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if CONFIG_GFXUMA set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else set_top_of_ram(ramtop); #endif +#else /* IS_ENABLED(CONFIG_LATE_CBMEM_INIT) */ + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#endif for (link = dev->link_list; link; link = link->next) { if (link->children) {

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Patch set updated for coreboot: amd/pi/stoney: Add memmap file
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18428 -gerrit commit 1a662fb0453ab12fb608a0ceace8d5be7b67e7eb Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 8 14:36:46 2017 -0500 amd/pi/stoney: Add memmap file In preparation for supporting EARLY_CBMEM_INIT, add a new file that will contain cbmem_top() and that can be used in all stages. Later patches will also be able to use the support routines. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 4fec9f6754675bbe0c8fbfc031c5c5665dace34b) Change-Id: I8ddaa8359536081752fb8e47e49f4d5958416620 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00670F00/Makefile.inc | 3 + src/northbridge/amd/pi/00670F00/memmap.c | 101 +++++++++++++++++++++++++++ src/northbridge/amd/pi/00670F00/memmap.h | 25 +++++++ 3 files changed, 129 insertions(+) diff --git a/src/northbridge/amd/pi/00670F00/Makefile.inc b/src/northbridge/amd/pi/00670F00/Makefile.inc index 7107d84..46617b9 100644 --- a/src/northbridge/amd/pi/00670F00/Makefile.inc +++ b/src/northbridge/amd/pi/00670F00/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += memmap.c +ramstage-y += memmap.c \ No newline at end of file diff --git a/src/northbridge/amd/pi/00670F00/memmap.c b/src/northbridge/amd/pi/00670F00/memmap.c new file mode 100644 index 0000000..02bfc13 --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/memmap.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cbmem.h> +#include <cpu/amd/mtrr.h> +#include "Porting.h" +#include <AMD.h> +#include "amdlib.h" +#include "memmap.h" + +static uint32_t installed_dram(void) +{ + uint64_t topmem, topmem2; + uint32_t sysmem_mb, sysmem_gb; + AMD_CONFIG_PARAMS StdHeader; + + LibAmdMsrRead (TOP_MEM, &topmem, &StdHeader); + LibAmdMsrRead (TOP_MEM2, &topmem2, &StdHeader); + + if (!topmem && !topmem2) + return 0; + + sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; + sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0; + sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT); + + return sysmem_gb; +} + +/* + * Return the size likely assigned to UMA when UMA_AUTO is specified. + * This is the only setting the wrapper currently implements. Refer to the + * BKDG for Family 15h Model 70h-7Fh Procesors (PID #55072) to find the + * following recommended configurations: + * Total system memory UMASize + * 6G+ 1024M + * 4G 512M + * 2G 256M + */ +uint32_t uma_size_auto(void) +{ + uint32_t sysmem_gb = installed_dram(); + + if (sysmem_gb >= 6) + return 1024 << ONE_MB_SHIFT; + if (sysmem_gb >= 4) + return 512 << ONE_MB_SHIFT; + if (sysmem_gb >= 2) + return 256 << ONE_MB_SHIFT; + if (sysmem_gb > 0) + return 128 << ONE_MB_SHIFT; + return 0; +} + +/* + * The BinaryPI image is compiled to always assign UMA below 4GB. It will + * also adjust TOM/TOM2 for the C6 storage, as well as the audio controller. + */ +uint32_t uma_base_auto(void) +{ + uint64_t topmem; + AMD_CONFIG_PARAMS StdHeader; + + LibAmdMsrRead (TOP_MEM, &topmem, &StdHeader); + + if (!topmem) + return 0; + + return (uint32_t)topmem - uma_size_auto(); +} + +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) +unsigned long get_top_of_ram(void) +{ + AMD_CONFIG_PARAMS StdHeader; + UINT64 MsrReg; + + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + return (unsigned long)MsrReg; +} +#endif + +#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT) +void *cbmem_top(void) +{ + return (void *)uma_base_auto(); +} +#endif diff --git a/src/northbridge/amd/pi/00670F00/memmap.h b/src/northbridge/amd/pi/00670F00/memmap.h new file mode 100644 index 0000000..01fcdc5 --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/memmap.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef NORTHBRIDGE_AMD_MEMMAP_H +#define NORTHBRIDGE_AMD_MEMMAP_H + +#define ONE_MB_SHIFT 20 +#define ONE_GB_SHIFT 30 + +uint32_t uma_base_auto(void); +uint32_t uma_size_auto(void); + +#endif /* NORTHBRIDGE_AMD_MEMMAP_H */

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Patch set updated for coreboot: amd/pi/mainboards: Consolidate early duplicated code
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18434 -gerrit commit d619b6b2bd1a7cce83bbb3695217d2689f2bfd51 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Feb 9 09:15:05 2017 -0700 amd/pi/mainboards: Consolidate early duplicated code Make a common entry function for cache_as_ram_main for use with the PI-based mainboards. The new function drives the typical setup, BIST checking, product reporting, and other common functions. This work takes hints from commit e6af4be. Add a new car.c file that contains the early steps. This has weak functions to hook for southbridge and mainboard setup. Some APUs also get BIST bits masked off. This patch is intended to prepare for an upcoming change that will split the CAR setup from the teardown, so that CAR setup may be used in verstage. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 9d1d92826216dee35f80ec40d722a3e8a587e996) Change-Id: Id10580ecc439df10df26ca99881772f328e7bdd0 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00660F01/fixme.c | 7 ++ src/cpu/amd/pi/00670F00/fixme.c | 7 ++ src/cpu/amd/pi/Makefile.inc | 2 + src/cpu/amd/pi/car.c | 88 +++++++++++++++++++++++ src/cpu/amd/pi/car.h | 30 ++++++++ src/mainboard/amd/bettong/romstage.c | 30 +------- src/mainboard/amd/db-ft3b-lc/Makefile.inc | 1 + src/mainboard/amd/db-ft3b-lc/early_mainboard.c | 31 ++++++++ src/mainboard/amd/db-ft3b-lc/romstage.c | 39 +--------- src/mainboard/amd/gardenia/romstage.c | 29 +------- src/mainboard/amd/lamar/Makefile.inc | 2 + src/mainboard/amd/lamar/early_mainboard.c | 44 ++++++++++++ src/mainboard/amd/lamar/romstage.c | 48 +------------ src/mainboard/amd/olivehillplus/Makefile.inc | 1 + src/mainboard/amd/olivehillplus/early_mainboard.c | 44 ++++++++++++ src/mainboard/amd/olivehillplus/romstage.c | 47 +----------- src/mainboard/bap/ode_e21XX/Makefile.inc | 1 + src/mainboard/bap/ode_e21XX/early_mainboard.c | 37 ++++++++++ src/mainboard/bap/ode_e21XX/romstage.c | 43 +---------- src/mainboard/pcengines/apu2/Makefile.inc | 1 + src/mainboard/pcengines/apu2/early_mainboard.c | 67 +++++++++++++++++ src/mainboard/pcengines/apu2/romstage.c | 74 +------------------ src/southbridge/amd/pi/hudson/early_setup.c | 11 +++ 23 files changed, 388 insertions(+), 296 deletions(-) diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index f244b98..fb1dfd7 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -16,6 +16,7 @@ #include <cpu/x86/mtrr.h> #include <northbridge/amd/pi/agesawrapper.h> #include "amdlib.h" +#include <cpu/amd/pi/car.h> void amd_initcpuio(void) { @@ -91,3 +92,9 @@ void amd_initmmio(void) LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); #endif } + +unsigned long car_bist_mask_bist(unsigned long bist) +{ + /* Mask bit 31. One result of Silicon Observation */ + return bist & 0x7FFFFFFF; +} diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index 272552d..3f02d7a 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -16,6 +16,7 @@ #include <cpu/x86/mtrr.h> #include <northbridge/amd/pi/agesawrapper.h> #include "amdlib.h" +#include <cpu/amd/pi/car.h> void amd_initcpuio(void) { @@ -95,3 +96,9 @@ void amd_initmmio(void) LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); #endif } + +unsigned long car_bist_mask_bist(unsigned long bist) +{ + /* Mask bit 31. One result of Silicon Observation */ + return bist & 0x7FFFFFFF; +} diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 0e31d9f..ce60833 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -18,6 +18,8 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 +romstage-y += car.c + romstage-y += s3_resume.c ramstage-y += s3_resume.c ramstage-$(CONFIG_SPI_FLASH) += spi.c diff --git a/src/cpu/amd/pi/car.c b/src/cpu/amd/pi/car.c new file mode 100644 index 0000000..62c5338 --- /dev/null +++ b/src/cpu/amd/pi/car.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> +#include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <timestamp.h> + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + +#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) + /* Initialize timestamp book keeping only once. */ + timestamp_init(timestamp_get()); +#endif + + post_code(0x30); + + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()){ + /* Call into pre-console init code then initialize console. */ + post_code(0x31); + car_sb_pre_console_init(); + + post_code(0x32); + car_mainboard_pre_console_init(); + + post_code(0x33); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(car_bist_mask_bist(bist)); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x35); + car_sb_post_console_init(); + post_code(0x36); + car_mainboard_post_console_init(); + + cache_as_ram_stage_main(); +} + +unsigned long __attribute__((weak)) car_bist_mask_bist(unsigned long bist) +{ + return bist; +} + +void __attribute__((weak)) car_mainboard_pre_console_init(void) +{ +} + +void __attribute__((weak)) car_sb_pre_console_init(void) +{ +} + +void __attribute__((weak)) car_mainboard_post_console_init(void) +{ +} + +void __attribute__((weak)) car_sb_post_console_init(void) +{ +} diff --git a/src/cpu/amd/pi/car.h b/src/cpu/amd/pi/car.h new file mode 100644 index 0000000..98da75d --- /dev/null +++ b/src/cpu/amd/pi/car.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef PI_SPLIT_CAR_H +#define PI_SPLIT_CAR_H + +/* Early initialization immediately after CAR setup */ +void cache_as_ram_stage_main(void); + +unsigned long car_bist_mask_bist(unsigned long bist); +void car_mainboard_pre_console_init(void); +void car_sb_pre_console_init(void); + +void car_mainboard_post_console_init(void); +void car_sb_post_console_init(void); + +#endif diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 6b12afc..c881337 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -17,45 +17,19 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - -#if IS_ENABLED(CONFIG_HUDSON_UART) - configure_hudson_uart(); -#endif - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */ - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc index 97c761f..01d99ac 100644 --- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc +++ b/src/mainboard/amd/db-ft3b-lc/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c +romstage-y += early_mainboard.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/db-ft3b-lc/early_mainboard.c b/src/mainboard/amd/db-ft3b-lc/early_mainboard.c new file mode 100644 index 0000000..7d471eb --- /dev/null +++ b/src/mainboard/amd/db-ft3b-lc/early_mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); +} diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 79cc0f9..e67f1fb 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -26,49 +26,14 @@ #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index eca9d3b..1d2d05b 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -17,44 +17,19 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif - amd_initmmio(); - hudson_lpc_port80(); - hudson_lpc_decode(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - -#if IS_ENABLED(CONFIG_HUDSON_UART) - configure_hudson_uart(); -#endif - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */ - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc index 37c1dce..794c6dc 100644 --- a/src/mainboard/amd/lamar/Makefile.inc +++ b/src/mainboard/amd/lamar/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +romstage-y += early_mainboard.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/lamar/early_mainboard.c b/src/mainboard/amd/lamar/early_mainboard.c new file mode 100644 index 0000000..65aace1 --- /dev/null +++ b/src/mainboard/amd/lamar/early_mainboard.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> +#include <southbridge/amd/common/amd_defs.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include "superio/fintek/f81216h/f81216h.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) + + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + outb(0x24, 0xCD6); + outb(0x01, 0xCD7); + *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ + *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ + + f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); +} diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index bda8c0f..9204e90 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -21,11 +21,11 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> @@ -34,53 +34,9 @@ #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> #include "cbmem.h" -#include "superio/fintek/f81216h/f81216h.h" -#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_decode(); - - outb(0x24, 0xCD6); - outb(0x01, 0xCD7); - *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ - *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ - - hudson_lpc_port80(); - - if (!cpu_init_detectedx) { - post_code(0x30); - f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); diff --git a/src/mainboard/amd/olivehillplus/Makefile.inc b/src/mainboard/amd/olivehillplus/Makefile.inc index 37c1dce..c1ac631 100644 --- a/src/mainboard/amd/olivehillplus/Makefile.inc +++ b/src/mainboard/amd/olivehillplus/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c +romstage-y += early_mainboard.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehillplus/early_mainboard.c b/src/mainboard/amd/olivehillplus/early_mainboard.c new file mode 100644 index 0000000..d394c9a --- /dev/null +++ b/src/mainboard/amd/olivehillplus/early_mainboard.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); +} + +void car_mainboard_post_console_init(void) +{ + /* + * This refers to LpcClkDrvSth settling time. Without this setting, processor + * initialization is slow or incorrect, so this wait has been replicated from + * earlier development boards. + */ + { + int i; + for(i = 0; i < 200000; i++) inb(0xCD6); + } +} diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 534a8e5..02fa3d1 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -26,6 +26,7 @@ #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> @@ -33,52 +34,8 @@ #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* - * This refers to LpcClkDrvSth settling time. Without this setting, processor - * initialization is slow or incorrect, so this wait has been replicated from - * earlier development boards. - */ - { - int i; - for(i = 0; i < 200000; i++) inb(0xCD6); - } - post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc index b0ce627..f6a27ad 100644 --- a/src/mainboard/bap/ode_e21XX/Makefile.inc +++ b/src/mainboard/bap/ode_e21XX/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c +romstage-y += early_mainboard.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c diff --git a/src/mainboard/bap/ode_e21XX/early_mainboard.c b/src/mainboard/bap/ode_e21XX/early_mainboard.c new file mode 100644 index 0000000..b7ffbbb --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/early_mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> + +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 5deeaa8..b82b13f 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -26,53 +26,14 @@ #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f81866d/f81866d.h> - -#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 77c6d78..2936f36 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -16,6 +16,7 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c +romstage-y += early_mainboard.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c diff --git a/src/mainboard/pcengines/apu2/early_mainboard.c b/src/mainboard/pcengines/apu2/early_mainboard.c new file mode 100644 index 0000000..9bd4ba3 --- /dev/null +++ b/src/mainboard/pcengines/apu2/early_mainboard.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <Fch/Fch.h> +#include "gpio_ftns.h" + +static void early_lpc_init(void) +{ + u32 setting = 0x0; + + // + // Configure output disabled, value low, pull up/down disabled + // + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting); + // + // Configure output enabled, value low, pull up/down disabled + // + setting = 0x1 << GPIO_OUTPUT_ENABLE; + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting); + // + // Configure output enabled, value high, pull up/down disabled + // + setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE; + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting); +} + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + early_lpc_init(); + + hudson_clk_output_48Mhz(); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63c..9dbf06c 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -26,54 +26,13 @@ #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> -#include <Fch/Fch.h> -#include "gpio_ftns.h" - -static void early_lpc_init(void); -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - amd_initmmio(); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - early_lpc_init(); - - hudson_clk_output_48Mhz(); - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); @@ -114,32 +73,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x54); /* Should never see this post code. */ } - - -static void early_lpc_init(void) -{ - u32 setting = 0x0; - - // - // Configure output disabled, value low, pull up/down disabled - // - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting); - // - // Configure output enabled, value low, pull up/down disabled - // - setting = 0x1 << GPIO_OUTPUT_ENABLE; - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting); - // - // Configure output enabled, value high, pull up/down disabled - // - setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE; - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting); -} diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 0ac2316..fa68624 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -26,6 +26,7 @@ #include "hudson.h" #include "pci_devs.h" #include <Fch/Fch.h> +#include <cpu/amd/pi/car.h> #if IS_ENABLED(CONFIG_HUDSON_UART) @@ -53,6 +54,16 @@ void configure_hudson_uart(void) #endif +void car_sb_pre_console_init(void) +{ + hudson_lpc_port80(); + hudson_lpc_decode(); + +#if IS_ENABLED(CONFIG_HUDSON_UART) + configure_hudson_uart(); +#endif +} + void hudson_pci_port80(void) { u8 byte;

1 0

Patch set updated for coreboot: amd/pi/hudson: Add early SPI setup
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18442 -gerrit commit 3996fbbf44e31d0974847baa31f45c18709c3d54 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Feb 10 16:03:54 2017 -0700 amd/pi/hudson: Add early SPI setup Add some generic functions that can configure the SPI interface to have faster performance. Given that the hudson files are used across many generations of FCHs, make sure to refer to the appropriate BKDG or RRG before using the functions. Notable differences: * Hudson 1 defines read mode in CNTRL0 differently than later gens * Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows setting FastSpeed as well * Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100 controller Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0) Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/early_setup.c | 43 +++++++++++++++++++++++++++++ src/southbridge/amd/pi/hudson/hudson.h | 4 +++ 2 files changed, 47 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index c3b14df..0ac2316 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -186,4 +186,47 @@ void hudson_clk_output_48Mhz(void) *memptr = data; } +static void hudson_default_spibase(void) +{ + /* Make sure the base address is predictable */ + device_t dev = PCI_DEV(0, 0x14, 3); + + u32 base = pci_read_config32(dev, 0xa0) & 0xfffffff0; + base |= SPI_BASE_ADDRESS | SPI_ROM_ENABLE; + pci_write_config32(dev, 0xa0, base); +} + +void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) +{ + hudson_default_spibase(); + write16(SPI100_SPEED_CONFIG, + (norm << SPI_NORM_SPEED_NEW_SH) | + (fast << SPI_FAST_SPEED_NEW_SH) | + (alt << SPI_ALT_SPEED_NEW_SH) | + (tpm << SPI_TPM_SPEED_NEW_SH)); + write16(SPI100_ENABLE, SPI_USE_SPI100); +} + +void hudson_disable_4dw_burst(void) +{ + hudson_default_spibase(); + write16(SPI100_HOST_PREF_CONFIG, read16(SPI100_HOST_PREF_CONFIG) + & ~SPI_RD4DW_EN_HOST); +} + +/* Hudson 1-3 only. For Hudson 1, call with fast=1 */ +void hudson_set_readspeed(u16 norm, u16 fast) +{ + hudson_default_spibase(); + write16(SPI_CNTRL1, (read16(SPI_CNTRL1) & ~SPI_CNTRL1_SPEED_MASK) | + (norm << SPI_NORM_SPEED_SH) | + (fast << SPI_FAST_SPEED_SH)); +} + +void hudson_read_mode(u32 mode) +{ + hudson_default_spibase(); + write32(SPI_CNTRL0, (read32(SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode); +} + #endif diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 73dd0e9..d055572 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -182,6 +182,10 @@ void hudson_lpc_port80(void); void hudson_lpc_decode(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); +void hudson_read_mode(u32 mode); +void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); +void hudson_disable_4dw_burst(void); +void hudson_set_readspeed(u16 norm, u16 fast); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);

1 0

Patch set updated for coreboot: amd/pi/hudson: Add SPI definitions to header
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18441 -gerrit commit dc75cfd025c0002576624bcdf707f996ea6796fd Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 29 17:29:46 2017 -0700 amd/pi/hudson: Add SPI definitions to header Add defines that will be used later for setting the fastest settings in the SPI controller. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c) Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/hudson.h | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 7835f68..73dd0e9 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -120,6 +120,44 @@ #define DECODE_ENABLE_ACPIUC_PORT (BIT30) #define DECODE_ENABLE_ADLIB_PORT (BIT31) +#define SPI_CNTRL0 ((void *)(SPI_BASE_ADDRESS + 0x00)) +#define SPI_READ_MODE_MASK (BIT30 | BIT29 | BIT18) +/* Nominal is 16.7MHz on older devices, 33MHz on newer */ +#define SPI_READ_MODE_NOM 0x00000000 +#define SPI_READ_MODE_DUAL112 ( BIT29 ) +#define SPI_READ_MODE_QUAD114 ( BIT29 | BIT18) +#define SPI_READ_MODE_DUAL122 (BIT30 ) +#define SPI_READ_MODE_QUAD144 (BIT30 | BIT18) +#define SPI_READ_MODE_NORMAL66 (BIT30 | BIT29 ) +/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */ +#define SPI_READ_MODE_FAST_HUDSON1 ( BIT18) +#define SPI_READ_MODE_FAST (BIT30 | BIT29 | BIT18) +#define SPI_ARB_ENABLE BIT19 + +#define SPI_CNTRL1 ((void *)(SPI_BASE_ADDRESS + 0x0c)) +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ +#define SPI_CNTRL1_SPEED_MASK (BIT15 | BIT14 | BIT13 | BIT12) +#define SPI_NORM_SPEED_SH 12 +#define SPI_FAST_SPEED_SH 8 + +#define SPI100_ENABLE ((void *)(SPI_BASE_ADDRESS + 0x20)) +#define SPI_USE_SPI100 (BIT0) + +#define SPI100_SPEED_CONFIG ((void *)(SPI_BASE_ADDRESS + 0x22)) +#define SPI_SPEED_66M (0x0) +#define SPI_SPEED_33M ( BIT0) +#define SPI_SPEED_22M ( BIT1 ) +#define SPI_SPEED_16M ( BIT1 | BIT0) +#define SPI_SPEED_100M (BIT2 ) +#define SPI_SPEED_800K (BIT2 | BIT0) +#define SPI_NORM_SPEED_NEW_SH 12 +#define SPI_FAST_SPEED_NEW_SH 8 +#define SPI_ALT_SPEED_NEW_SH 4 +#define SPI_TPM_SPEED_NEW_SH 0 + +#define SPI100_HOST_PREF_CONFIG ((void *)(SPI_BASE_ADDRESS + 0x2c)) +#define SPI_RD4DW_EN_HOST BIT15 + static inline int hudson_sata_enable(void) { /* True if IDE or AHCI. */

1 0

Patch set updated for coreboot: amd/pi/hudson: Add alternate method for including amdfw
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18435 -gerrit commit acea966e958f19c02e530976c58701ec52759268 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Jan 7 18:17:32 2017 -0500 amd/pi/hudson: Add alternate method for including amdfw For systems using Chrome OS, place the amdfw outside of cbfs control. The firmware must go to a fixed position at an offset of 0x20000 into the flash device. Potentially improve by adding a warning or error message for the condition when sizeof(amdfw) + sizeof(cbfs and metadata) > sizeof(flash). Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 2d9d631b39d7850576438a5b0979936bd33893e1) Change-Id: I38029bc03e5db260424cca293b1a7bceea4d0d75 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/Kconfig | 7 +++++++ src/southbridge/amd/pi/hudson/Makefile.inc | 13 +++++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index f6e3355..0afeeec 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -220,3 +220,10 @@ config HUDSON_UART controller 0 registers range from FEDC_6000h to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh. + +config AMDFW_OUTSIDE_CBFS + def_bool n + help + The AMDFW (PSP) is typically locatable in cbfs. Select this + option to manually attach the generated amdfw.rom at an + offset of 0x20000 from the bottom of the coreboot ROM image. diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 24a757c..2153c62 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -264,7 +264,20 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ --flashsize $(CONFIG_ROM_SIZE) \ --output $@ +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) +PHONY+=add_amdfw +INTERMEDIATE+=add_amdfw + +add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom + printf " DD Adding AMD Firmware\n" + dd if=$(obj)/amdfw.rom \ + of=$(obj)/coreboot.pre conv=notrunc bs=1 seek=131072 >/dev/null 2>&1 + +else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) + cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(HUDSON_FWM_POSITION) apu/amdfw-type := raw + +endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)

1 0

Patch set updated for coreboot: amd/pi/hudson: Move APIC enable to CPU file
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18436 -gerrit commit bafd986c3cef3cba10704d20ef32f81824316ec0 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Feb 12 10:31:15 2017 -0700 amd/pi/hudson: Move APIC enable to CPU file Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00630F01/fixme.c | 6 ++++++ src/cpu/amd/pi/00660F01/fixme.c | 6 ++++++ src/cpu/amd/pi/00670F00/fixme.c | 6 ++++++ src/cpu/amd/pi/00730F01/fixme.c | 6 ++++++ src/southbridge/amd/pi/hudson/early_setup.c | 4 ---- 5 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index fcdc925..e33a3c9 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -77,4 +77,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + +#if IS_ENABLED(CONFIG_UDELAY_LAPIC) + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); +#endif } diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 6770287..f244b98 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -84,4 +84,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + +#if IS_ENABLED(CONFIG_UDELAY_LAPIC) + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); +#endif } diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index 86f5acf..272552d 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -88,4 +88,10 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + +#if IS_ENABLED(CONFIG_UDELAY_LAPIC) + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); +#endif } diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index fcdf498..f6405a5 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -89,4 +89,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + +#if IS_ENABLED(CONFIG_UDELAY_LAPIC) + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); +#endif } diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 553add9..c3b14df 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -34,12 +34,8 @@ void configure_hudson_uart(void) { - msr_t msr; u8 byte; - msr = rdmsr(0x1B); - msr.lo |= 1 << 11; - wrmsr(0x1B, msr); byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2); byte |= 1 << 3; write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2, byte);

1 0

Patch set updated for coreboot: amd/pi/hudson: Move BITn definitions to header file
by Marc Jones 25 Feb '17

25 Feb '17

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18440 -gerrit commit 90d3021a509bf1d98ec25db4b9ddb1b86aa849e2 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 29 17:22:36 2017 -0700 amd/pi/hudson: Move BITn definitions to header file In preparation for subsequent patches, move definitions from a .c file to hudson.h. Also change the method for generating the values from LSH and update some existing defintions to use BINn. Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c) Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/hudson.h | 99 +++++++++++++++++++++++----------- src/southbridge/amd/pi/hudson/sm.c | 35 ------------ 2 files changed, 67 insertions(+), 67 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 23d9b31..7835f68 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -21,6 +21,41 @@ #include <device/device.h> #include "chip.h" +#ifndef BIT0 +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#endif + /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 @@ -52,38 +87,38 @@ #define SPI_BASE_ADDRESS 0xFEC10000 #define LPC_IO_PORT_DECODE_ENABLE 0x44 -#define DECODE_ENABLE_PARALLEL_PORT0 (1 << 0) -#define DECODE_ENABLE_PARALLEL_PORT1 (1 << 1) -#define DECODE_ENABLE_PARALLEL_PORT2 (1 << 2) -#define DECODE_ENABLE_PARALLEL_PORT3 (1 << 3) -#define DECODE_ENABLE_PARALLEL_PORT4 (1 << 4) -#define DECODE_ENABLE_PARALLEL_PORT5 (1 << 5) -#define DECODE_ENABLE_SERIAL_PORT0 (1 << 6) -#define DECODE_ENABLE_SERIAL_PORT1 (1 << 7) -#define DECODE_ENABLE_SERIAL_PORT2 (1 << 8) -#define DECODE_ENABLE_SERIAL_PORT3 (1 << 9) -#define DECODE_ENABLE_SERIAL_PORT4 (1 << 10) -#define DECODE_ENABLE_SERIAL_PORT5 (1 << 11) -#define DECODE_ENABLE_SERIAL_PORT6 (1 << 12) -#define DECODE_ENABLE_SERIAL_PORT7 (1 << 13) -#define DECODE_ENABLE_AUDIO_PORT0 (1 << 14) -#define DECODE_ENABLE_AUDIO_PORT1 (1 << 15) -#define DECODE_ENABLE_AUDIO_PORT2 (1 << 16) -#define DECODE_ENABLE_AUDIO_PORT3 (1 << 17) -#define DECODE_ENABLE_MIDI_PORT0 (1 << 18) -#define DECODE_ENABLE_MIDI_PORT1 (1 << 19) -#define DECODE_ENABLE_MIDI_PORT2 (1 << 20) -#define DECODE_ENABLE_MIDI_PORT3 (1 << 21) -#define DECODE_ENABLE_MSS_PORT0 (1 << 22) -#define DECODE_ENABLE_MSS_PORT1 (1 << 23) -#define DECODE_ENABLE_MSS_PORT2 (1 << 24) -#define DECODE_ENABLE_MSS_PORT3 (1 << 25) -#define DECODE_ENABLE_FDC_PORT0 (1 << 26) -#define DECODE_ENABLE_FDC_PORT1 (1 << 27) -#define DECODE_ENABLE_GAME_PORT (1 << 28) -#define DECODE_ENABLE_KBC_PORT (1 << 29) -#define DECODE_ENABLE_ACPIUC_PORT (1 << 30) -#define DECODE_ENABLE_ADLIB_PORT (1 << 31) +#define DECODE_ENABLE_PARALLEL_PORT0 (BIT0) +#define DECODE_ENABLE_PARALLEL_PORT1 (BIT1) +#define DECODE_ENABLE_PARALLEL_PORT2 (BIT2) +#define DECODE_ENABLE_PARALLEL_PORT3 (BIT3) +#define DECODE_ENABLE_PARALLEL_PORT4 (BIT4) +#define DECODE_ENABLE_PARALLEL_PORT5 (BIT5) +#define DECODE_ENABLE_SERIAL_PORT0 (BIT6) +#define DECODE_ENABLE_SERIAL_PORT1 (BIT7) +#define DECODE_ENABLE_SERIAL_PORT2 (BIT8) +#define DECODE_ENABLE_SERIAL_PORT3 (BIT9) +#define DECODE_ENABLE_SERIAL_PORT4 (BIT10) +#define DECODE_ENABLE_SERIAL_PORT5 (BIT11) +#define DECODE_ENABLE_SERIAL_PORT6 (BIT12) +#define DECODE_ENABLE_SERIAL_PORT7 (BIT13) +#define DECODE_ENABLE_AUDIO_PORT0 (BIT14) +#define DECODE_ENABLE_AUDIO_PORT1 (BIT15) +#define DECODE_ENABLE_AUDIO_PORT2 (BIT16) +#define DECODE_ENABLE_AUDIO_PORT3 (BIT17) +#define DECODE_ENABLE_MIDI_PORT0 (BIT18) +#define DECODE_ENABLE_MIDI_PORT1 (BIT19) +#define DECODE_ENABLE_MIDI_PORT2 (BIT20) +#define DECODE_ENABLE_MIDI_PORT3 (BIT21) +#define DECODE_ENABLE_MSS_PORT0 (BIT22) +#define DECODE_ENABLE_MSS_PORT1 (BIT23) +#define DECODE_ENABLE_MSS_PORT2 (BIT24) +#define DECODE_ENABLE_MSS_PORT3 (BIT25) +#define DECODE_ENABLE_FDC_PORT0 (BIT26) +#define DECODE_ENABLE_FDC_PORT1 (BIT27) +#define DECODE_ENABLE_GAME_PORT (BIT28) +#define DECODE_ENABLE_KBC_PORT (BIT29) +#define DECODE_ENABLE_ACPIUC_PORT (BIT30) +#define DECODE_ENABLE_ADLIB_PORT (BIT31) static inline int hudson_sata_enable(void) { diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 74367a7..db29d10 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -36,41 +36,6 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -#define BIT0 (1 << 0) -#define BIT1 (1 << 1) -#define BIT2 (1 << 2) -#define BIT3 (1 << 3) -#define BIT4 (1 << 4) -#define BIT5 (1 << 5) -#define BIT6 (1 << 6) -#define BIT7 (1 << 7) - -#define BIT8 (1 << 8 ) -#define BIT9 (1 << 9 ) -#define BIT10 (1 << 10) -#define BIT11 (1 << 11) -#define BIT12 (1 << 12) -#define BIT13 (1 << 13) -#define BIT14 (1 << 14) -#define BIT15 (1 << 15) - -#define BIT16 (1 << 16) -#define BIT17 (1 << 17) -#define BIT18 (1 << 18) -#define BIT19 (1 << 19) -#define BIT20 (1 << 20) -#define BIT21 (1 << 21) -#define BIT22 (1 << 22) -#define BIT23 (1 << 23) -#define BIT24 (1 << 24) -#define BIT25 (1 << 25) -#define BIT26 (1 << 26) -#define BIT27 (1 << 27) -#define BIT28 (1 << 28) -#define BIT29 (1 << 29) -#define BIT30 (1 << 30) -#define BIT31 (1 << 31) - /* * HUDSON enables all USB controllers by default in SMBUS Control. * HUDSON enables SATA by default in SMBUS Control.

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New patch to review for coreboot: mainboard/google/reef: keep LPSS_UART2_TXD high in suspend state
by Aaron Durbin 24 Feb '17

24 Feb '17

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18491 -gerrit commit 8f3cfe00e2a87e9882f97e1a3e6d195cb0f894cc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 24 15:56:27 2017 -0600 mainboard/google/reef: keep LPSS_UART2_TXD high in suspend state The cr50 part on reef is connected to the SoC's UART lines. However, when the tx signal is low it causes an interrupt to fire on cr50. Therefore, keep the tx signal high in suspend state so that it doesn't cause an interrupt storm on cr50 which prevents cr50 from sleeping. BUG=chrome-os-partner:63283 BRANCH=reef TEST=s0ix no longer causes interrupt storm on cr50. Power consumption normal. Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index a9a6248..ae89da1 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -327,7 +327,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */

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coreboot-gerrit February 2017